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spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3E2F96F64A; Fri, 21 May 2021 13:23:52 +0000 (UTC) Received: from mail-wr1-x42f.google.com (mail-wr1-x42f.google.com [IPv6:2a00:1450:4864:20::42f]) by gabe.freedesktop.org (Postfix) with ESMTPS id 5762F6F64A for ; Fri, 21 May 2021 13:23:51 +0000 (UTC) Received: by mail-wr1-x42f.google.com with SMTP id x7so1463346wrt.12 for ; Fri, 21 May 2021 06:23:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fooishbar-org.20150623.gappssmtp.com; s=20150623; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=zBr2qa8weJ1fN+pyrA9yHt47NZiiPugqQIjjkfzP+jw=; b=Vo39h2GhwMLbJLo+/rJ8jKdDxxx7yt/+DuSYtdRMJYd/ewYSQQsrwCnOCge0+aOIM2 9/KcfjejnPY8GM8mZ7TLh9EDtHEL/1jvG9ThrG9zg8eAz/GKa3MaVPVSMLnA4tV2yryY wubn8HMprLTyeofXBSRountcrg6j1SBLsPKvAsbxcvpmEVW7xAfjiqMlhxwraaQJlRHQ RBb6DN/tULEGgiS/IonVr9QgSxe37CitIuX4+gnFggRx+HHuCHA5loPr60vmuDY9nqZD rfQA3gO4qDA/z8bt5atk4ADkTZhfdIHY0OqxfaTHUZQut/UlgKWx4Let826C6h8Ly2d/ GudQ== X-Google-DKIM-Signature: v=1; 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charset="utf-8" Content-Transfer-Encoding: base64 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" T24gRnJpLCAyMSBNYXkgMjAyMSBhdCAxNDowOSwgQ2hyaXN0aWFuIEvDtm5pZyA8Y2hyaXN0aWFu LmtvZW5pZ0BhbWQuY29tPiB3cm90ZToKPiBBbSAyMS4wNS4yMSB1bSAxNDo1NCBzY2hyaWViIERh bmllbCBTdG9uZToKPiA+IElmIHlvdSdyZSBjdXJpb3VzLCB0aGUgaW50ZXJmYWNlIGRlZmluaXRp b25zIGFyZSBpbiB0aGUgY3NmLyBkaXJlY3RvcnkKPiA+IGluIHRoZSAnQmlmcm9zdCBrZXJuZWwg ZHJpdmVyJyByMzBwMCBkb3dubG9hZCB5b3UgY2FuIGdldCBmcm9tIHRoZSBBcm0KPiA+IGRldmVs b3BlciBzaXRlLiBVbmZvcnR1bmF0ZWx5IHRoZSBleGFjdCBzZW1hbnRpY3MgYXJlbid0IGNvbXBs ZXRlbHkKPiA+IGNsZWFyLgo+Cj4gV2VsbCBpdCBpcyBhY3R1YWxseSByZWxhdGl2ZWx5IHNpbXBs ZS4gVGFrZSBhIGxvb2sgYXQgdGhlIHRpbWVsaW5lCj4gc2VtYXBob3JlcyBmcm9tIFZ1bGthbiwg ZXZlcnlib2R5IGlzIGJhc2ljYWxseSBpbXBsZW1lbnRpbmcgdGhlIHNhbWUKPiBzZW1hbnRpY3Mg bm93Lgo+Cj4gV2hlbiB5b3UgcXVldWVkIHVwIGEgYnVuY2ggb2YgY29tbWFuZHMgb24geW91ciBo YXJkd2FyZSwgdGhlIGZpcnN0IG9uZQo+IHdpbGwgd3JpdGUgdmFsdWUgMSB0byBhIDY0Yml0IG1l bW9yeSBsb2NhdGlvbiwgdGhlIHNlY29uZCBvbmUgd2lsbCB3cml0ZQo+IHZhbHVlIDIsIHRoZSB0 aGlyZCB2YWx1ZSAzIGFuZCBzbyBvbi4gQWZ0ZXIgd3JpdGluZyB0aGUgdmFsdWUgdGhlCj4gaGFy ZHdhcmUgcmFpc2VzIGFuZCBpbnRlcnJ1cHQgc2lnbmFsIHRvIGV2ZXJ5Ym9keSBpbnRlcmVzdGVk Lgo+Cj4gSW4gb3RoZXIgd29yZHMgcHJldHR5IHN0YW5kYXJkIG1lbW9yeSBmZW5jZSBiZWhhdmlv ci4KPgo+IFdoZW4geW91IG5vdyBoYXZlIGEgc2Vjb25kIHF1ZXVlIHdoaWNoIGRlcGVuZHMgb24g d29yayBvZiB0aGUgZmlyc3Qgb25lCj4geW91IGxvb2sgYXQgdGhlIG1lbW9yeSBsb2NhdGlvbiBh bmQgZG8gYSBjb21wYXJlLiBJZiB5b3UgZGVwZW5kIG9uIHRoZQo+IHRoaXJkIHN1Ym1pc3Npb24g eW91IGp1c3Qgd2FpdCBmb3IgdGhlIHZhbHVlIHRvIGJlID4zIGFuZCBhcmUgZG9uZS4KClJpZ2h0 LCBpdCBpcyBjbGVhcmx5IGRlZmluZWQgdG8gdGhlIHRpbWVsaW5lIHNlbWFwaG9yZSBzZW1hbnRp Y3MsIEkKanVzdCBtZWFudCB0aGF0IGl0J3Mgbm90IGNsZWFyIGhvdyBpdCB3b3JrcyBhdCBhIGxv d2VyIGxldmVsIHdydCB0aGUKc3luY2hyb25pc2F0aW9uIGFuZCBzaWduYWxpbmcuIFRoZSBzaW1w bGVzdCBwb3NzaWJsZSBpbnRlcnByZXRhdGlvbiBpcwp0aGF0IHdhaXRfYWRkcnZhbCBibG9ja3Mg aW5maW5pdGVseSBiZWZvcmUga2ljay1jbWRidWYsIGJ1dCB0aGF0IHNlZW1zCnBhaW5mdWwgd2l0 aCBvbmx5IDMyIHF1ZXVlcy4gQW5kIHRoZSBzYW1lIGZvciBmZW5jZXMsIHdoaWNoIGFyZSBhCmJp bmFyeSBzaWduYWwuIEkgZ3Vlc3Mgd2UnbGwgZmluZCBvdXQuIE15IHRvb3RoIGh1cnRzLgoKQ2hl ZXJzLApEYW5pZWwKX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X18KSW50ZWwtZ2Z4IG1haWxpbmcgbGlzdApJbnRlbC1nZnhAbGlzdHMuZnJlZWRlc2t0b3Aub3Jn Cmh0dHBzOi8vbGlzdHMuZnJlZWRlc2t0b3Aub3JnL21haWxtYW4vbGlzdGluZm8vaW50ZWwtZ2Z4 Cg== From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.5 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9CEFAC43461 for ; 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Fri, 21 May 2021 06:23:49 -0700 (PDT) MIME-Version: 1.0 References: <20210521090959.1663703-1-daniel.vetter@ffwll.ch> <20210521090959.1663703-4-daniel.vetter@ffwll.ch> <39aa30e4-2726-a0ba-3537-3be609dbc0b5@amd.com> In-Reply-To: <39aa30e4-2726-a0ba-3537-3be609dbc0b5@amd.com> From: Daniel Stone Date: Fri, 21 May 2021 14:23:38 +0100 Message-ID: Subject: Re: [Linaro-mm-sig] [PATCH 04/11] drm/panfrost: Fix implicit sync To: =?UTF-8?Q?Christian_K=C3=B6nig?= Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Tomeu Vizoso , Daniel Vetter , Intel Graphics Development , DRI Development , Steven Price , "moderated list:DMA BUFFER SHARING FRAMEWORK" , Alyssa Rosenzweig , Daniel Vetter , "open list:DMA BUFFER SHARING FRAMEWORK" Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On Fri, 21 May 2021 at 14:09, Christian K=C3=B6nig wrote: > Am 21.05.21 um 14:54 schrieb Daniel Stone: > > If you're curious, the interface definitions are in the csf/ directory > > in the 'Bifrost kernel driver' r30p0 download you can get from the Arm > > developer site. Unfortunately the exact semantics aren't completely > > clear. > > Well it is actually relatively simple. Take a look at the timeline > semaphores from Vulkan, everybody is basically implementing the same > semantics now. > > When you queued up a bunch of commands on your hardware, the first one > will write value 1 to a 64bit memory location, the second one will write > value 2, the third value 3 and so on. After writing the value the > hardware raises and interrupt signal to everybody interested. > > In other words pretty standard memory fence behavior. > > When you now have a second queue which depends on work of the first one > you look at the memory location and do a compare. If you depend on the > third submission you just wait for the value to be >3 and are done. Right, it is clearly defined to the timeline semaphore semantics, I just meant that it's not clear how it works at a lower level wrt the synchronisation and signaling. The simplest possible interpretation is that wait_addrval blocks infinitely before kick-cmdbuf, but that seems painful with only 32 queues. And the same for fences, which are a binary signal. I guess we'll find out. My tooth hurts. Cheers, Daniel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 02603C433ED for ; Fri, 21 May 2021 13:24:22 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D91FA61164 for ; Fri, 21 May 2021 13:24:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235021AbhEUNZm (ORCPT ); Fri, 21 May 2021 09:25:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54834 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235046AbhEUNZS (ORCPT ); Fri, 21 May 2021 09:25:18 -0400 Received: from mail-wr1-x42a.google.com (mail-wr1-x42a.google.com [IPv6:2a00:1450:4864:20::42a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 75847C061346 for ; Fri, 21 May 2021 06:23:51 -0700 (PDT) Received: by mail-wr1-x42a.google.com with SMTP id n2so21157316wrm.0 for ; Fri, 21 May 2021 06:23:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fooishbar-org.20150623.gappssmtp.com; s=20150623; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=zBr2qa8weJ1fN+pyrA9yHt47NZiiPugqQIjjkfzP+jw=; b=Vo39h2GhwMLbJLo+/rJ8jKdDxxx7yt/+DuSYtdRMJYd/ewYSQQsrwCnOCge0+aOIM2 9/KcfjejnPY8GM8mZ7TLh9EDtHEL/1jvG9ThrG9zg8eAz/GKa3MaVPVSMLnA4tV2yryY wubn8HMprLTyeofXBSRountcrg6j1SBLsPKvAsbxcvpmEVW7xAfjiqMlhxwraaQJlRHQ RBb6DN/tULEGgiS/IonVr9QgSxe37CitIuX4+gnFggRx+HHuCHA5loPr60vmuDY9nqZD rfQA3gO4qDA/z8bt5atk4ADkTZhfdIHY0OqxfaTHUZQut/UlgKWx4Let826C6h8Ly2d/ GudQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=zBr2qa8weJ1fN+pyrA9yHt47NZiiPugqQIjjkfzP+jw=; b=A2iVD6QHnloIL+dO4kxQJYnhjQVBuELNmo4fUCoutY9SYcLai/iotJFwXbIErpi0Dz r9j7TczW/qXAKgdfnSB/XguGQDd8nEXnoXNtlNe05mb3GbrQT6crnHH9t+pOrHfD/dpF /UB/VsVLWQLoht6Mrmd2bSvyEZdKjRRhN+fG87J5KjzUrCG5cb+tBfZfIrcqc3CzwxMt WRBFXp1YLQZ8w0Fawt5+JOKJQQxKunBcphmO3xINpMSfdvDTa0bM2JJ0+pdSNdswHJIH KSzQBwy3oLJy3RDBDS/mwIDjC0x6ozB0bLDsmqHfhdeYe2L+0WrwhjfcruGSba4Fpvqr RIFg== X-Gm-Message-State: AOAM533L2HWughJMkgb+nX6vTwrBGo85Y2vBI5FFcJQ9AcEF8r3o98qT f77VdT1YFLz9rI7cLSAN2uoKc127L/sF9qxK8YKZPw== X-Google-Smtp-Source: ABdhPJyU8TEmXK/S6OXq7q8k124HIgHp5J7hILQzz4PXVCcZY3JiYAj8Ouwu177Y0/InrwMU7WBJIc4BjzJuyR8pTms= X-Received: by 2002:a5d:6e04:: with SMTP id h4mr9422676wrz.256.1621603429939; Fri, 21 May 2021 06:23:49 -0700 (PDT) MIME-Version: 1.0 References: <20210521090959.1663703-1-daniel.vetter@ffwll.ch> <20210521090959.1663703-4-daniel.vetter@ffwll.ch> <39aa30e4-2726-a0ba-3537-3be609dbc0b5@amd.com> In-Reply-To: <39aa30e4-2726-a0ba-3537-3be609dbc0b5@amd.com> From: Daniel Stone Date: Fri, 21 May 2021 14:23:38 +0100 Message-ID: Subject: Re: [Linaro-mm-sig] [PATCH 04/11] drm/panfrost: Fix implicit sync To: =?UTF-8?Q?Christian_K=C3=B6nig?= Cc: Daniel Vetter , Tomeu Vizoso , Intel Graphics Development , DRI Development , Steven Price , "moderated list:DMA BUFFER SHARING FRAMEWORK" , Alyssa Rosenzweig , Daniel Vetter , "open list:DMA BUFFER SHARING FRAMEWORK" Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org On Fri, 21 May 2021 at 14:09, Christian K=C3=B6nig wrote: > Am 21.05.21 um 14:54 schrieb Daniel Stone: > > If you're curious, the interface definitions are in the csf/ directory > > in the 'Bifrost kernel driver' r30p0 download you can get from the Arm > > developer site. Unfortunately the exact semantics aren't completely > > clear. > > Well it is actually relatively simple. Take a look at the timeline > semaphores from Vulkan, everybody is basically implementing the same > semantics now. > > When you queued up a bunch of commands on your hardware, the first one > will write value 1 to a 64bit memory location, the second one will write > value 2, the third value 3 and so on. After writing the value the > hardware raises and interrupt signal to everybody interested. > > In other words pretty standard memory fence behavior. > > When you now have a second queue which depends on work of the first one > you look at the memory location and do a compare. If you depend on the > third submission you just wait for the value to be >3 and are done. Right, it is clearly defined to the timeline semaphore semantics, I just meant that it's not clear how it works at a lower level wrt the synchronisation and signaling. The simplest possible interpretation is that wait_addrval blocks infinitely before kick-cmdbuf, but that seems painful with only 32 queues. And the same for fences, which are a binary signal. I guess we'll find out. My tooth hurts. Cheers, Daniel