RISC-V PMU driver issue

From: 雷博涵 <garthlei@pku.edu.cn>
To: Atish Patra <atishp@atishpatra.org>
Cc: linux-riscv@lists.infradead.org
Subject: RISC-V PMU driver issue
Date: Wed, 28 Feb 2024 11:49:20 +0800	[thread overview]
Message-ID: <CC51D53B-846C-4D81-86FC-FBF969D0A0D6@pku.edu.cn> (raw)

Hi all,

I am having problems with the RISC-V PMU driver. The overflow handler of my custom perf event kernel counter seems to read an incorrect value from the event.
It seems that the issue lies in the function `riscv_pmu_event_set_period`, which sets `prev_count` to a new value but does not modify the underlying hardware counter. When `perf_event_read_value` gets called later in the user-defined overflow handler, `riscv_pmu_event_update` will update the `count` field again based on the unmodified hardware counter value and the modified `prev_count` field, which causes an incorrect reading.
I noticed that other PMU drivers, such as the ARM one, write to the underlying counter in their set_period functions, which prevents the problem. However, the RISC-V SBI specification does not have such an API to write to a counter without starting it. Using `local64_read(&hw_evt->period_left) <= 0` directly as the guard condition to place `riscv_pmu_event_set_period(event)` after it seems to work, but I am not sure whether it can cause other issues.

Thank you,
Bohan Lei

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