* [PATCH] drm/amdgpu: simplify the sdma 4_x MGCG/MGLS logic.
@ 2021-03-04 3:58 Feifei Xu
2021-03-04 4:11 ` Alex Deucher
0 siblings, 1 reply; 12+ messages in thread
From: Feifei Xu @ 2021-03-04 3:58 UTC (permalink / raw
To: amd-gfx; +Cc: Feifei Xu
SDMA 4_x asics share the same MGCG/MGLS setting.
Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
---
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 12 +-----------
1 file changed, 1 insertion(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index 3bede8a70d7e..f46169c048fd 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -2271,21 +2271,11 @@ static int sdma_v4_0_set_clockgating_state(void *handle,
if (amdgpu_sriov_vf(adev))
return 0;
- switch (adev->asic_type) {
- case CHIP_VEGA10:
- case CHIP_VEGA12:
- case CHIP_VEGA20:
- case CHIP_RAVEN:
- case CHIP_ARCTURUS:
- case CHIP_RENOIR:
- case CHIP_ALDEBARAN:
+ if (adev->asic_type >= CHIP_VEGA10){
sdma_v4_0_update_medium_grain_clock_gating(adev,
state == AMD_CG_STATE_GATE);
sdma_v4_0_update_medium_grain_light_sleep(adev,
state == AMD_CG_STATE_GATE);
- break;
- default:
- break;
}
return 0;
}
--
2.25.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH] drm/amdgpu: simplify the sdma 4_x MGCG/MGLS logic.
2021-03-04 3:58 [PATCH] drm/amdgpu: simplify the sdma 4_x MGCG/MGLS logic Feifei Xu
@ 2021-03-04 4:11 ` Alex Deucher
2021-03-04 4:44 ` Xu, Feifei
0 siblings, 1 reply; 12+ messages in thread
From: Alex Deucher @ 2021-03-04 4:11 UTC (permalink / raw
To: Feifei Xu; +Cc: amd-gfx list
On Wed, Mar 3, 2021 at 10:58 PM Feifei Xu <Feifei.Xu@amd.com> wrote:
>
> SDMA 4_x asics share the same MGCG/MGLS setting.
>
> Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 12 +-----------
> 1 file changed, 1 insertion(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> index 3bede8a70d7e..f46169c048fd 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> @@ -2271,21 +2271,11 @@ static int sdma_v4_0_set_clockgating_state(void *handle,
> if (amdgpu_sriov_vf(adev))
> return 0;
>
> - switch (adev->asic_type) {
> - case CHIP_VEGA10:
> - case CHIP_VEGA12:
> - case CHIP_VEGA20:
> - case CHIP_RAVEN:
> - case CHIP_ARCTURUS:
> - case CHIP_RENOIR:
> - case CHIP_ALDEBARAN:
> + if (adev->asic_type >= CHIP_VEGA10){
Need a space between ) and {. That said, do we even need to check the
asic type here at all? I think this applies to all chips that have
sdma4.
Alex
> sdma_v4_0_update_medium_grain_clock_gating(adev,
> state == AMD_CG_STATE_GATE);
> sdma_v4_0_update_medium_grain_light_sleep(adev,
> state == AMD_CG_STATE_GATE);
> - break;
> - default:
> - break;
> }
> return 0;
> }
> --
> 2.25.1
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread
* RE: [PATCH] drm/amdgpu: simplify the sdma 4_x MGCG/MGLS logic.
2021-03-04 4:11 ` Alex Deucher
@ 2021-03-04 4:44 ` Xu, Feifei
2021-03-04 5:20 ` Alex Deucher
0 siblings, 1 reply; 12+ messages in thread
From: Xu, Feifei @ 2021-03-04 4:44 UTC (permalink / raw
To: Alex Deucher; +Cc: amd-gfx list
[AMD Official Use Only - Internal Distribution Only]
Thanks. The VegaM still need to be rule out.
Thanks,
Feifei
-----Original Message-----
From: Alex Deucher <alexdeucher@gmail.com>
Sent: Thursday, March 4, 2021 12:12 PM
To: Xu, Feifei <Feifei.Xu@amd.com>
Cc: amd-gfx list <amd-gfx@lists.freedesktop.org>
Subject: Re: [PATCH] drm/amdgpu: simplify the sdma 4_x MGCG/MGLS logic.
On Wed, Mar 3, 2021 at 10:58 PM Feifei Xu <Feifei.Xu@amd.com> wrote:
>
> SDMA 4_x asics share the same MGCG/MGLS setting.
>
> Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 12 +-----------
> 1 file changed, 1 insertion(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> index 3bede8a70d7e..f46169c048fd 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> @@ -2271,21 +2271,11 @@ static int sdma_v4_0_set_clockgating_state(void *handle,
> if (amdgpu_sriov_vf(adev))
> return 0;
>
> - switch (adev->asic_type) {
> - case CHIP_VEGA10:
> - case CHIP_VEGA12:
> - case CHIP_VEGA20:
> - case CHIP_RAVEN:
> - case CHIP_ARCTURUS:
> - case CHIP_RENOIR:
> - case CHIP_ALDEBARAN:
> + if (adev->asic_type >= CHIP_VEGA10){
Need a space between ) and {. That said, do we even need to check the asic type here at all? I think this applies to all chips that have sdma4.
Alex
> sdma_v4_0_update_medium_grain_clock_gating(adev,
> state == AMD_CG_STATE_GATE);
> sdma_v4_0_update_medium_grain_light_sleep(adev,
> state == AMD_CG_STATE_GATE);
> - break;
> - default:
> - break;
> }
> return 0;
> }
> --
> 2.25.1
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flist
> s.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=04%7C01%7CFe
> ifei.Xu%40amd.com%7C67eba26e9d7a4ea88e9b08d8dec3af22%7C3dd8961fe4884e6
> 08e11a82d994e183d%7C0%7C0%7C637504279325196042%7CUnknown%7CTWFpbGZsb3d
> 8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C
> 1000&sdata=jUa2v%2BB6NICmTSr9Zdt0MQdjd1oIXYOzDYloTzUstz0%3D&re
> served=0
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH] drm/amdgpu: simplify the sdma 4_x MGCG/MGLS logic.
@ 2021-03-04 4:54 Feifei Xu
2021-03-04 4:55 ` Xu, Feifei
0 siblings, 1 reply; 12+ messages in thread
From: Feifei Xu @ 2021-03-04 4:54 UTC (permalink / raw
To: amd-gfx, alexdeucher; +Cc: Alexander.Deucher, Feifei Xu
SDMA 4_x asics share the same MGCG/MGLS setting.
Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
---
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 12 +-----------
1 file changed, 1 insertion(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index 3bede8a70d7e..0280e8f589d1 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -2271,21 +2271,11 @@ static int sdma_v4_0_set_clockgating_state(void *handle,
if (amdgpu_sriov_vf(adev))
return 0;
- switch (adev->asic_type) {
- case CHIP_VEGA10:
- case CHIP_VEGA12:
- case CHIP_VEGA20:
- case CHIP_RAVEN:
- case CHIP_ARCTURUS:
- case CHIP_RENOIR:
- case CHIP_ALDEBARAN:
+ if (adev->asic_type >= CHIP_VEGA10) {
sdma_v4_0_update_medium_grain_clock_gating(adev,
state == AMD_CG_STATE_GATE);
sdma_v4_0_update_medium_grain_light_sleep(adev,
state == AMD_CG_STATE_GATE);
- break;
- default:
- break;
}
return 0;
}
--
2.25.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 12+ messages in thread
* RE: [PATCH] drm/amdgpu: simplify the sdma 4_x MGCG/MGLS logic.
2021-03-04 4:54 Feifei Xu
@ 2021-03-04 4:55 ` Xu, Feifei
0 siblings, 0 replies; 12+ messages in thread
From: Xu, Feifei @ 2021-03-04 4:55 UTC (permalink / raw
To: Xu, Feifei, amd-gfx@lists.freedesktop.org, alexdeucher@gmail.com
Cc: Deucher, Alexander
[AMD Official Use Only - Internal Distribution Only]
Modified the coding style error. And resend. Thanks.
Thanks,
Feifei
-----Original Message-----
From: Feifei Xu <Feifei.Xu@amd.com>
Sent: Thursday, March 4, 2021 12:54 PM
To: amd-gfx@lists.freedesktop.org; alexdeucher@gmail.com
Cc: Deucher, Alexander <Alexander.Deucher@amd.com>; Xu, Feifei <Feifei.Xu@amd.com>
Subject: [PATCH] drm/amdgpu: simplify the sdma 4_x MGCG/MGLS logic.
SDMA 4_x asics share the same MGCG/MGLS setting.
Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
---
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 12 +-----------
1 file changed, 1 insertion(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index 3bede8a70d7e..0280e8f589d1 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -2271,21 +2271,11 @@ static int sdma_v4_0_set_clockgating_state(void *handle,
if (amdgpu_sriov_vf(adev))
return 0;
-switch (adev->asic_type) {
-case CHIP_VEGA10:
-case CHIP_VEGA12:
-case CHIP_VEGA20:
-case CHIP_RAVEN:
-case CHIP_ARCTURUS:
-case CHIP_RENOIR:
-case CHIP_ALDEBARAN:
+if (adev->asic_type >= CHIP_VEGA10) {
sdma_v4_0_update_medium_grain_clock_gating(adev,
state == AMD_CG_STATE_GATE);
sdma_v4_0_update_medium_grain_light_sleep(adev,
state == AMD_CG_STATE_GATE);
-break;
-default:
-break;
}
return 0;
}
--
2.25.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH] drm/amdgpu: simplify the sdma 4_x MGCG/MGLS logic.
2021-03-04 4:44 ` Xu, Feifei
@ 2021-03-04 5:20 ` Alex Deucher
2021-03-04 5:36 ` Lazar, Lijo
2021-03-04 5:47 ` Xu, Feifei
0 siblings, 2 replies; 12+ messages in thread
From: Alex Deucher @ 2021-03-04 5:20 UTC (permalink / raw
To: Xu, Feifei; +Cc: amd-gfx list
On Wed, Mar 3, 2021 at 11:44 PM Xu, Feifei <Feifei.Xu@amd.com> wrote:
>
> [AMD Official Use Only - Internal Distribution Only]
>
> Thanks. The VegaM still need to be rule out.
VegaM is SDMA 3.x.
Alex
>
> Thanks,
> Feifei
>
> -----Original Message-----
> From: Alex Deucher <alexdeucher@gmail.com>
> Sent: Thursday, March 4, 2021 12:12 PM
> To: Xu, Feifei <Feifei.Xu@amd.com>
> Cc: amd-gfx list <amd-gfx@lists.freedesktop.org>
> Subject: Re: [PATCH] drm/amdgpu: simplify the sdma 4_x MGCG/MGLS logic.
>
> On Wed, Mar 3, 2021 at 10:58 PM Feifei Xu <Feifei.Xu@amd.com> wrote:
> >
> > SDMA 4_x asics share the same MGCG/MGLS setting.
> >
> > Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
> > ---
> > drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 12 +-----------
> > 1 file changed, 1 insertion(+), 11 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> > b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> > index 3bede8a70d7e..f46169c048fd 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> > @@ -2271,21 +2271,11 @@ static int sdma_v4_0_set_clockgating_state(void *handle,
> > if (amdgpu_sriov_vf(adev))
> > return 0;
> >
> > - switch (adev->asic_type) {
> > - case CHIP_VEGA10:
> > - case CHIP_VEGA12:
> > - case CHIP_VEGA20:
> > - case CHIP_RAVEN:
> > - case CHIP_ARCTURUS:
> > - case CHIP_RENOIR:
> > - case CHIP_ALDEBARAN:
> > + if (adev->asic_type >= CHIP_VEGA10){
>
> Need a space between ) and {. That said, do we even need to check the asic type here at all? I think this applies to all chips that have sdma4.
>
> Alex
>
> > sdma_v4_0_update_medium_grain_clock_gating(adev,
> > state == AMD_CG_STATE_GATE);
> > sdma_v4_0_update_medium_grain_light_sleep(adev,
> > state == AMD_CG_STATE_GATE);
> > - break;
> > - default:
> > - break;
> > }
> > return 0;
> > }
> > --
> > 2.25.1
> >
> > _______________________________________________
> > amd-gfx mailing list
> > amd-gfx@lists.freedesktop.org
> > https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flist
> > s.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=04%7C01%7CFe
> > ifei.Xu%40amd.com%7C67eba26e9d7a4ea88e9b08d8dec3af22%7C3dd8961fe4884e6
> > 08e11a82d994e183d%7C0%7C0%7C637504279325196042%7CUnknown%7CTWFpbGZsb3d
> > 8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C
> > 1000&sdata=jUa2v%2BB6NICmTSr9Zdt0MQdjd1oIXYOzDYloTzUstz0%3D&re
> > served=0
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread
* RE: [PATCH] drm/amdgpu: simplify the sdma 4_x MGCG/MGLS logic.
2021-03-04 5:20 ` Alex Deucher
@ 2021-03-04 5:36 ` Lazar, Lijo
2021-03-04 5:48 ` Xu, Feifei
2021-03-04 5:47 ` Xu, Feifei
1 sibling, 1 reply; 12+ messages in thread
From: Lazar, Lijo @ 2021-03-04 5:36 UTC (permalink / raw
To: Alex Deucher, Xu, Feifei; +Cc: amd-gfx list
[AMD Public Use]
There shouldn't be any check based on ASIC type. If a check is required, it should be based on AMD_CG_SUPPORT_SDMA_MGCG and AMD_CG_SUPPORT_SDMA_LS. We set the flags appropriately for each ASIC in soc15.
Thanks,
Lijo
-----Original Message-----
From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Alex Deucher
Sent: Thursday, March 4, 2021 10:50 AM
To: Xu, Feifei <Feifei.Xu@amd.com>
Cc: amd-gfx list <amd-gfx@lists.freedesktop.org>
Subject: Re: [PATCH] drm/amdgpu: simplify the sdma 4_x MGCG/MGLS logic.
On Wed, Mar 3, 2021 at 11:44 PM Xu, Feifei <Feifei.Xu@amd.com> wrote:
>
> [AMD Official Use Only - Internal Distribution Only]
>
> Thanks. The VegaM still need to be rule out.
VegaM is SDMA 3.x.
Alex
>
> Thanks,
> Feifei
>
> -----Original Message-----
> From: Alex Deucher <alexdeucher@gmail.com>
> Sent: Thursday, March 4, 2021 12:12 PM
> To: Xu, Feifei <Feifei.Xu@amd.com>
> Cc: amd-gfx list <amd-gfx@lists.freedesktop.org>
> Subject: Re: [PATCH] drm/amdgpu: simplify the sdma 4_x MGCG/MGLS logic.
>
> On Wed, Mar 3, 2021 at 10:58 PM Feifei Xu <Feifei.Xu@amd.com> wrote:
> >
> > SDMA 4_x asics share the same MGCG/MGLS setting.
> >
> > Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
> > ---
> > drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 12 +-----------
> > 1 file changed, 1 insertion(+), 11 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> > b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> > index 3bede8a70d7e..f46169c048fd 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> > @@ -2271,21 +2271,11 @@ static int sdma_v4_0_set_clockgating_state(void *handle,
> > if (amdgpu_sriov_vf(adev))
> > return 0;
> >
> > - switch (adev->asic_type) {
> > - case CHIP_VEGA10:
> > - case CHIP_VEGA12:
> > - case CHIP_VEGA20:
> > - case CHIP_RAVEN:
> > - case CHIP_ARCTURUS:
> > - case CHIP_RENOIR:
> > - case CHIP_ALDEBARAN:
> > + if (adev->asic_type >= CHIP_VEGA10){
>
> Need a space between ) and {. That said, do we even need to check the asic type here at all? I think this applies to all chips that have sdma4.
>
> Alex
>
> > sdma_v4_0_update_medium_grain_clock_gating(adev,
> > state == AMD_CG_STATE_GATE);
> > sdma_v4_0_update_medium_grain_light_sleep(adev,
> > state == AMD_CG_STATE_GATE);
> > - break;
> > - default:
> > - break;
> > }
> > return 0;
> > }
> > --
> > 2.25.1
> >
> > _______________________________________________
> > amd-gfx mailing list
> > amd-gfx@lists.freedesktop.org
> > https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fli
> > st
> > s.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=04%7C01%7C
> > Fe
> > ifei.Xu%40amd.com%7C67eba26e9d7a4ea88e9b08d8dec3af22%7C3dd8961fe4884
> > e6
> > 08e11a82d994e183d%7C0%7C0%7C637504279325196042%7CUnknown%7CTWFpbGZsb
> > 3d
> > 8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%
> > 7C
> > 1000&sdata=jUa2v%2BB6NICmTSr9Zdt0MQdjd1oIXYOzDYloTzUstz0%3D&
> > re
> > served=0
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=04%7C01%7Clijo.lazar%40amd.com%7Cbfbac27bc87349944bb208d8decd3447%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637504320239632738%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&sdata=LJ5n33cyVrDmUCl%2FrJYUUtYP4RKP3tIiS1FKOSqdwyM%3D&reserved=0
_______________________________________________
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^ permalink raw reply [flat|nested] 12+ messages in thread
* RE: [PATCH] drm/amdgpu: simplify the sdma 4_x MGCG/MGLS logic.
2021-03-04 5:20 ` Alex Deucher
2021-03-04 5:36 ` Lazar, Lijo
@ 2021-03-04 5:47 ` Xu, Feifei
1 sibling, 0 replies; 12+ messages in thread
From: Xu, Feifei @ 2021-03-04 5:47 UTC (permalink / raw
To: Alex Deucher; +Cc: amd-gfx list
[AMD Official Use Only - Internal Distribution Only]
OK. Thanks for pointing it out. I will modify to remove the check.
Thanks,
Feifei
-----Original Message-----
From: Alex Deucher <alexdeucher@gmail.com>
Sent: Thursday, March 4, 2021 1:20 PM
To: Xu, Feifei <Feifei.Xu@amd.com>
Cc: amd-gfx list <amd-gfx@lists.freedesktop.org>
Subject: Re: [PATCH] drm/amdgpu: simplify the sdma 4_x MGCG/MGLS logic.
On Wed, Mar 3, 2021 at 11:44 PM Xu, Feifei <Feifei.Xu@amd.com> wrote:
>
> [AMD Official Use Only - Internal Distribution Only]
>
> Thanks. The VegaM still need to be rule out.
VegaM is SDMA 3.x.
Alex
>
> Thanks,
> Feifei
>
> -----Original Message-----
> From: Alex Deucher <alexdeucher@gmail.com>
> Sent: Thursday, March 4, 2021 12:12 PM
> To: Xu, Feifei <Feifei.Xu@amd.com>
> Cc: amd-gfx list <amd-gfx@lists.freedesktop.org>
> Subject: Re: [PATCH] drm/amdgpu: simplify the sdma 4_x MGCG/MGLS logic.
>
> On Wed, Mar 3, 2021 at 10:58 PM Feifei Xu <Feifei.Xu@amd.com> wrote:
> >
> > SDMA 4_x asics share the same MGCG/MGLS setting.
> >
> > Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
> > ---
> > drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 12 +-----------
> > 1 file changed, 1 insertion(+), 11 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> > b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> > index 3bede8a70d7e..f46169c048fd 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> > @@ -2271,21 +2271,11 @@ static int sdma_v4_0_set_clockgating_state(void *handle,
> > if (amdgpu_sriov_vf(adev))
> > return 0;
> >
> > - switch (adev->asic_type) {
> > - case CHIP_VEGA10:
> > - case CHIP_VEGA12:
> > - case CHIP_VEGA20:
> > - case CHIP_RAVEN:
> > - case CHIP_ARCTURUS:
> > - case CHIP_RENOIR:
> > - case CHIP_ALDEBARAN:
> > + if (adev->asic_type >= CHIP_VEGA10){
>
> Need a space between ) and {. That said, do we even need to check the asic type here at all? I think this applies to all chips that have sdma4.
>
> Alex
>
> > sdma_v4_0_update_medium_grain_clock_gating(adev,
> > state == AMD_CG_STATE_GATE);
> > sdma_v4_0_update_medium_grain_light_sleep(adev,
> > state == AMD_CG_STATE_GATE);
> > - break;
> > - default:
> > - break;
> > }
> > return 0;
> > }
> > --
> > 2.25.1
> >
> > _______________________________________________
> > amd-gfx mailing list
> > amd-gfx@lists.freedesktop.org
> > https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fli
> > st
> > s.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=04%7C01%7C
> > Fe
> > ifei.Xu%40amd.com%7C67eba26e9d7a4ea88e9b08d8dec3af22%7C3dd8961fe4884
> > e6
> > 08e11a82d994e183d%7C0%7C0%7C637504279325196042%7CUnknown%7CTWFpbGZsb
> > 3d
> > 8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%
> > 7C
> > 1000&sdata=jUa2v%2BB6NICmTSr9Zdt0MQdjd1oIXYOzDYloTzUstz0%3D&
> > re
> > served=0
_______________________________________________
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^ permalink raw reply [flat|nested] 12+ messages in thread
* RE: [PATCH] drm/amdgpu: simplify the sdma 4_x MGCG/MGLS logic.
2021-03-04 5:36 ` Lazar, Lijo
@ 2021-03-04 5:48 ` Xu, Feifei
0 siblings, 0 replies; 12+ messages in thread
From: Xu, Feifei @ 2021-03-04 5:48 UTC (permalink / raw
To: Lazar, Lijo, Alex Deucher; +Cc: amd-gfx list
Thanks. Will modify to remove the check since all SDMA 4_x share the same setting logic.
Thanks,
Feifei
-----Original Message-----
From: Lazar, Lijo <Lijo.Lazar@amd.com>
Sent: Thursday, March 4, 2021 1:37 PM
To: Alex Deucher <alexdeucher@gmail.com>; Xu, Feifei <Feifei.Xu@amd.com>
Cc: amd-gfx list <amd-gfx@lists.freedesktop.org>
Subject: RE: [PATCH] drm/amdgpu: simplify the sdma 4_x MGCG/MGLS logic.
[AMD Public Use]
There shouldn't be any check based on ASIC type. If a check is required, it should be based on AMD_CG_SUPPORT_SDMA_MGCG and AMD_CG_SUPPORT_SDMA_LS. We set the flags appropriately for each ASIC in soc15.
Thanks,
Lijo
-----Original Message-----
From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Alex Deucher
Sent: Thursday, March 4, 2021 10:50 AM
To: Xu, Feifei <Feifei.Xu@amd.com>
Cc: amd-gfx list <amd-gfx@lists.freedesktop.org>
Subject: Re: [PATCH] drm/amdgpu: simplify the sdma 4_x MGCG/MGLS logic.
On Wed, Mar 3, 2021 at 11:44 PM Xu, Feifei <Feifei.Xu@amd.com> wrote:
>
> [AMD Official Use Only - Internal Distribution Only]
>
> Thanks. The VegaM still need to be rule out.
VegaM is SDMA 3.x.
Alex
>
> Thanks,
> Feifei
>
> -----Original Message-----
> From: Alex Deucher <alexdeucher@gmail.com>
> Sent: Thursday, March 4, 2021 12:12 PM
> To: Xu, Feifei <Feifei.Xu@amd.com>
> Cc: amd-gfx list <amd-gfx@lists.freedesktop.org>
> Subject: Re: [PATCH] drm/amdgpu: simplify the sdma 4_x MGCG/MGLS logic.
>
> On Wed, Mar 3, 2021 at 10:58 PM Feifei Xu <Feifei.Xu@amd.com> wrote:
> >
> > SDMA 4_x asics share the same MGCG/MGLS setting.
> >
> > Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
> > ---
> > drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 12 +-----------
> > 1 file changed, 1 insertion(+), 11 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> > b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> > index 3bede8a70d7e..f46169c048fd 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> > @@ -2271,21 +2271,11 @@ static int sdma_v4_0_set_clockgating_state(void *handle,
> > if (amdgpu_sriov_vf(adev))
> > return 0;
> >
> > - switch (adev->asic_type) {
> > - case CHIP_VEGA10:
> > - case CHIP_VEGA12:
> > - case CHIP_VEGA20:
> > - case CHIP_RAVEN:
> > - case CHIP_ARCTURUS:
> > - case CHIP_RENOIR:
> > - case CHIP_ALDEBARAN:
> > + if (adev->asic_type >= CHIP_VEGA10){
>
> Need a space between ) and {. That said, do we even need to check the asic type here at all? I think this applies to all chips that have sdma4.
>
> Alex
>
> > sdma_v4_0_update_medium_grain_clock_gating(adev,
> > state == AMD_CG_STATE_GATE);
> > sdma_v4_0_update_medium_grain_light_sleep(adev,
> > state == AMD_CG_STATE_GATE);
> > - break;
> > - default:
> > - break;
> > }
> > return 0;
> > }
> > --
> > 2.25.1
> >
> > _______________________________________________
> > amd-gfx mailing list
> > amd-gfx@lists.freedesktop.org
> > https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fli
> > st
> > s.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=04%7C01%7C
> > Fe
> > ifei.Xu%40amd.com%7C67eba26e9d7a4ea88e9b08d8dec3af22%7C3dd8961fe4884
> > e6
> > 08e11a82d994e183d%7C0%7C0%7C637504279325196042%7CUnknown%7CTWFpbGZsb
> > 3d
> > 8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%
> > 7C
> > 1000&sdata=jUa2v%2BB6NICmTSr9Zdt0MQdjd1oIXYOzDYloTzUstz0%3D&
> > re
> > served=0
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=04%7C01%7Clijo.lazar%40amd.com%7Cbfbac27bc87349944bb208d8decd3447%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637504320239632738%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&sdata=LJ5n33cyVrDmUCl%2FrJYUUtYP4RKP3tIiS1FKOSqdwyM%3D&reserved=0
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^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH] drm/amdgpu: simplify the sdma 4_x MGCG/MGLS logic.
@ 2021-03-04 6:48 Feifei Xu
2021-03-04 7:31 ` Zhang, Hawking
2021-03-04 12:02 ` Lazar, Lijo
0 siblings, 2 replies; 12+ messages in thread
From: Feifei Xu @ 2021-03-04 6:48 UTC (permalink / raw
To: amd-gfx; +Cc: alexdeucher, Feifei Xu, Lijo.Lazar
SDMA 4_x asics share the same MGCG/MGLS setting.
Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
---
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 20 ++++----------------
1 file changed, 4 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index 3bede8a70d7e..70d247841d14 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -2271,22 +2271,10 @@ static int sdma_v4_0_set_clockgating_state(void *handle,
if (amdgpu_sriov_vf(adev))
return 0;
- switch (adev->asic_type) {
- case CHIP_VEGA10:
- case CHIP_VEGA12:
- case CHIP_VEGA20:
- case CHIP_RAVEN:
- case CHIP_ARCTURUS:
- case CHIP_RENOIR:
- case CHIP_ALDEBARAN:
- sdma_v4_0_update_medium_grain_clock_gating(adev,
- state == AMD_CG_STATE_GATE);
- sdma_v4_0_update_medium_grain_light_sleep(adev,
- state == AMD_CG_STATE_GATE);
- break;
- default:
- break;
- }
+ sdma_v4_0_update_medium_grain_clock_gating(adev,
+ state == AMD_CG_STATE_GATE);
+ sdma_v4_0_update_medium_grain_light_sleep(adev,
+ state == AMD_CG_STATE_GATE);
return 0;
}
--
2.25.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 12+ messages in thread
* RE: [PATCH] drm/amdgpu: simplify the sdma 4_x MGCG/MGLS logic.
2021-03-04 6:48 Feifei Xu
@ 2021-03-04 7:31 ` Zhang, Hawking
2021-03-04 12:02 ` Lazar, Lijo
1 sibling, 0 replies; 12+ messages in thread
From: Zhang, Hawking @ 2021-03-04 7:31 UTC (permalink / raw
To: Xu, Feifei, amd-gfx@lists.freedesktop.org
Cc: alexdeucher@gmail.com, Xu, Feifei, Lazar, Lijo
[AMD Public Use]
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Regards,
Hawking
-----Original Message-----
From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Feifei Xu
Sent: Thursday, March 4, 2021 14:49
To: amd-gfx@lists.freedesktop.org
Cc: alexdeucher@gmail.com; Xu, Feifei <Feifei.Xu@amd.com>; Lazar, Lijo <Lijo.Lazar@amd.com>
Subject: [PATCH] drm/amdgpu: simplify the sdma 4_x MGCG/MGLS logic.
SDMA 4_x asics share the same MGCG/MGLS setting.
Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
---
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 20 ++++----------------
1 file changed, 4 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index 3bede8a70d7e..70d247841d14 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -2271,22 +2271,10 @@ static int sdma_v4_0_set_clockgating_state(void *handle,
if (amdgpu_sriov_vf(adev))
return 0;
- switch (adev->asic_type) {
- case CHIP_VEGA10:
- case CHIP_VEGA12:
- case CHIP_VEGA20:
- case CHIP_RAVEN:
- case CHIP_ARCTURUS:
- case CHIP_RENOIR:
- case CHIP_ALDEBARAN:
- sdma_v4_0_update_medium_grain_clock_gating(adev,
- state == AMD_CG_STATE_GATE);
- sdma_v4_0_update_medium_grain_light_sleep(adev,
- state == AMD_CG_STATE_GATE);
- break;
- default:
- break;
- }
+ sdma_v4_0_update_medium_grain_clock_gating(adev,
+ state == AMD_CG_STATE_GATE);
+ sdma_v4_0_update_medium_grain_light_sleep(adev,
+ state == AMD_CG_STATE_GATE);
return 0;
}
--
2.25.1
_______________________________________________
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^ permalink raw reply related [flat|nested] 12+ messages in thread
* RE: [PATCH] drm/amdgpu: simplify the sdma 4_x MGCG/MGLS logic.
2021-03-04 6:48 Feifei Xu
2021-03-04 7:31 ` Zhang, Hawking
@ 2021-03-04 12:02 ` Lazar, Lijo
1 sibling, 0 replies; 12+ messages in thread
From: Lazar, Lijo @ 2021-03-04 12:02 UTC (permalink / raw
To: Xu, Feifei, amd-gfx@lists.freedesktop.org
Cc: alexdeucher@gmail.com, Xu, Feifei
[AMD Public Use]
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
-----Original Message-----
From: Feifei Xu <Feifei.Xu@amd.com>
Sent: Thursday, March 4, 2021 12:19 PM
To: amd-gfx@lists.freedesktop.org
Cc: alexdeucher@gmail.com; Lazar, Lijo <Lijo.Lazar@amd.com>; Xu, Feifei <Feifei.Xu@amd.com>
Subject: [PATCH] drm/amdgpu: simplify the sdma 4_x MGCG/MGLS logic.
SDMA 4_x asics share the same MGCG/MGLS setting.
Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
---
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 20 ++++----------------
1 file changed, 4 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index 3bede8a70d7e..70d247841d14 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -2271,22 +2271,10 @@ static int sdma_v4_0_set_clockgating_state(void *handle,
if (amdgpu_sriov_vf(adev))
return 0;
- switch (adev->asic_type) {
- case CHIP_VEGA10:
- case CHIP_VEGA12:
- case CHIP_VEGA20:
- case CHIP_RAVEN:
- case CHIP_ARCTURUS:
- case CHIP_RENOIR:
- case CHIP_ALDEBARAN:
- sdma_v4_0_update_medium_grain_clock_gating(adev,
- state == AMD_CG_STATE_GATE);
- sdma_v4_0_update_medium_grain_light_sleep(adev,
- state == AMD_CG_STATE_GATE);
- break;
- default:
- break;
- }
+ sdma_v4_0_update_medium_grain_clock_gating(adev,
+ state == AMD_CG_STATE_GATE);
+ sdma_v4_0_update_medium_grain_light_sleep(adev,
+ state == AMD_CG_STATE_GATE);
return 0;
}
--
2.25.1
_______________________________________________
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^ permalink raw reply related [flat|nested] 12+ messages in thread
end of thread, other threads:[~2021-03-04 12:02 UTC | newest]
Thread overview: 12+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2021-03-04 3:58 [PATCH] drm/amdgpu: simplify the sdma 4_x MGCG/MGLS logic Feifei Xu
2021-03-04 4:11 ` Alex Deucher
2021-03-04 4:44 ` Xu, Feifei
2021-03-04 5:20 ` Alex Deucher
2021-03-04 5:36 ` Lazar, Lijo
2021-03-04 5:48 ` Xu, Feifei
2021-03-04 5:47 ` Xu, Feifei
-- strict thread matches above, loose matches on Subject: below --
2021-03-04 4:54 Feifei Xu
2021-03-04 4:55 ` Xu, Feifei
2021-03-04 6:48 Feifei Xu
2021-03-04 7:31 ` Zhang, Hawking
2021-03-04 12:02 ` Lazar, Lijo
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