diff for duplicates of <EE11001F9E5DDD47B7634E2F8A612F2E01D664BC@lhreml503-mbx> diff --git a/a/1.txt b/N1/1.txt index be39508..f3dcb5b 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -9,11 +9,11 @@ Gab > -----Original Message----- > From: Gabriele Paoloni > Sent: Tuesday, July 14, 2015 11:47 AM -> To: Gabriele Paoloni; arnd@arndb.de; lorenzo.pieralisi@arm.com; -> Wangzhou (B); bhelgaas@google.com; robh+dt@kernel.org; -> james.morse@arm.com; Liviu.Dudau@arm.com -> Cc: linux-pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org; -> devicetree@vger.kernel.org; Yuanzhichang; Zhudacai; zhangjukuo; +> To: Gabriele Paoloni; arnd at arndb.de; lorenzo.pieralisi at arm.com; +> Wangzhou (B); bhelgaas at google.com; robh+dt at kernel.org; +> james.morse at arm.com; Liviu.Dudau at arm.com +> Cc: linux-pci at vger.kernel.org; linux-arm-kernel at lists.infradead.org; +> devicetree at vger.kernel.org; Yuanzhichang; Zhudacai; zhangjukuo; > qiuzhenfa; Liguozhu (Kenneth) > Subject: [PATCH v2] PCI: Store PCIe bus address in struct of_pci_range > diff --git a/a/content_digest b/N1/content_digest index 3859558..ad2c41d 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -2,33 +2,16 @@ "ref\0001436870799-207766-1-git-send-email-gabriele.paoloni\@huawei.com\0" ] [ - "From\0Gabriele Paoloni <gabriele.paoloni\@huawei.com>\0" + "From\0gabriele.paoloni\@huawei.com (Gabriele Paoloni)\0" ] [ - "Subject\0RE: [PATCH v2] PCI: Store PCIe bus address in struct of_pci_range\0" + "Subject\0[PATCH v2] PCI: Store PCIe bus address in struct of_pci_range\0" ] [ "Date\0Wed, 22 Jul 2015 09:45:22 +0000\0" ] [ - "To\0Gabriele Paoloni <gabriele.paoloni\@huawei.com>", - " arnd\@arndb.de <arnd\@arndb.de>", - " lorenzo.pieralisi\@arm.com <lorenzo.pieralisi\@arm.com>", - " Wangzhou (B) <wangzhou1\@hisilicon.com>", - " bhelgaas\@google.com <bhelgaas\@google.com>", - " robh+dt\@kernel.org <robh+dt\@kernel.org>", - " james.morse\@arm.com <james.morse\@arm.com>", - " Liviu.Dudau\@arm.com <Liviu.Dudau\@arm.com>\0" -] -[ - "Cc\0linux-pci\@vger.kernel.org <linux-pci\@vger.kernel.org>", - " linux-arm-kernel\@lists.infradead.org <linux-arm-kernel\@lists.infradead.org>", - " devicetree\@vger.kernel.org <devicetree\@vger.kernel.org>", - " Yuanzhichang <yuanzhichang\@hisilicon.com>", - " Zhudacai <zhudacai\@hisilicon.com>", - " zhangjukuo <zhangjukuo\@huawei.com>", - " qiuzhenfa <qiuzhenfa\@hisilicon.com>", - " Liguozhu (Kenneth) <liguozhu\@hisilicon.com>\0" + "To\0linux-arm-kernel\@lists.infradead.org\0" ] [ "\0000:1\0" @@ -48,11 +31,11 @@ "> -----Original Message-----\n", "> From: Gabriele Paoloni\n", "> Sent: Tuesday, July 14, 2015 11:47 AM\n", - "> To: Gabriele Paoloni; arnd\@arndb.de; lorenzo.pieralisi\@arm.com;\n", - "> Wangzhou (B); bhelgaas\@google.com; robh+dt\@kernel.org;\n", - "> james.morse\@arm.com; Liviu.Dudau\@arm.com\n", - "> Cc: linux-pci\@vger.kernel.org; linux-arm-kernel\@lists.infradead.org;\n", - "> devicetree\@vger.kernel.org; Yuanzhichang; Zhudacai; zhangjukuo;\n", + "> To: Gabriele Paoloni; arnd at arndb.de; lorenzo.pieralisi at arm.com;\n", + "> Wangzhou (B); bhelgaas at google.com; robh+dt at kernel.org;\n", + "> james.morse at arm.com; Liviu.Dudau at arm.com\n", + "> Cc: linux-pci at vger.kernel.org; linux-arm-kernel at lists.infradead.org;\n", + "> devicetree at vger.kernel.org; Yuanzhichang; Zhudacai; zhangjukuo;\n", "> qiuzhenfa; Liguozhu (Kenneth)\n", "> Subject: [PATCH v2] PCI: Store PCIe bus address in struct of_pci_range\n", "> \n", @@ -168,4 +151,4 @@ "> 1.9.1" ] -26dbd478b95fe4740d9f1950d4e8df4f0ae3a4e831cff5c8dff2893e912f7409 +1bc90dd31b385037a61d333e64f1466abdf20e199a0205a6584c99788597c7d7
diff --git a/a/1.txt b/N2/1.txt index be39508..63a22fe 100644 --- a/a/1.txt +++ b/N2/1.txt @@ -1,129 +1,80 @@ -Any comment on this patch? - -This is needed by "[PATCH v4 2/5] PCI: designware: Add ARM64 support" - -Thanks - -Gab - -> -----Original Message----- -> From: Gabriele Paoloni -> Sent: Tuesday, July 14, 2015 11:47 AM -> To: Gabriele Paoloni; arnd@arndb.de; lorenzo.pieralisi@arm.com; -> Wangzhou (B); bhelgaas@google.com; robh+dt@kernel.org; -> james.morse@arm.com; Liviu.Dudau@arm.com -> Cc: linux-pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org; -> devicetree@vger.kernel.org; Yuanzhichang; Zhudacai; zhangjukuo; -> qiuzhenfa; Liguozhu (Kenneth) -> Subject: [PATCH v2] PCI: Store PCIe bus address in struct of_pci_range -> -> From: gabriele paoloni <gabriele.paoloni@huawei.com> -> -> This patch is needed port PCIe designware to new DT parsing API -> As discussed in -> http://lists.infradead.org/pipermail/linux-arm-kernel/2015- -> January/317743.html -> in designware we have a problem as the PCI addresses in the PCIe -> controller -> address space are required in order to perform correct HW operation. -> -> In order to solve this problem commit -> f4c55c5a3 "PCI: designware: Program ATU with untranslated address" -> added code to read the PCIe controller start address directly from -> the -> DT ranges. -> -> In the new DT parsing API of_pci_get_host_bridge_resources() hides -> the -> DT parser from the host controller drivers, so it is not possible -> for drivers to parse values directly from the DT. -> -> In http://www.spinics.net/lists/linux-pci/msg42540.html we already -> tried -> to use the new DT parsing API but there is a bug (obviously) in -> setting -> the <*>_mod_base addresses -> Applying this patch we can easily set "<*>_mod_base = win- -> >__res.start" -> -> This patch adds a new field in "struct of_pci_range" to store the -> pci bus start address; it fills the field in -> of_pci_range_parser_one(); -> in of_pci_get_host_bridge_resources() it retrieves the resource -> entry -> after it is created and added to the resource list and uses -> entry->__res.start to store the pci controller address -> -> the patch is based on 4.2-rc1 -> -> Signed-off-by: Gabriele Paoloni <gabriele.paoloni@huawei.com> -> --- -> drivers/of/address.c | 2 ++ -> drivers/of/of_pci.c | 4 ++++ -> include/linux/of_address.h | 1 + -> 3 files changed, 7 insertions(+) -> -> diff --git a/drivers/of/address.c b/drivers/of/address.c -> index 8bfda6a..23a5793 100644 -> --- a/drivers/of/address.c -> +++ b/drivers/of/address.c -> @@ -253,6 +253,7 @@ struct of_pci_range *of_pci_range_parser_one(struct -> of_pci_range_parser *parser, -> struct of_pci_range *range) -> { -> const int na = 3, ns = 2; -> + const int p_ns = of_n_size_cells(parser->node); -> -> if (!range) -> return NULL; -> @@ -265,6 +266,7 @@ struct of_pci_range *of_pci_range_parser_one(struct -> of_pci_range_parser *parser, -> range->pci_addr = of_read_number(parser->range + 1, ns); -> range->cpu_addr = of_translate_address(parser->node, -> parser->range + na); -> + range->bus_addr = of_read_number(parser->range + na, p_ns); -> range->size = of_read_number(parser->range + parser->pna + na, -> ns); -> -> parser->range += parser->np; -> diff --git a/drivers/of/of_pci.c b/drivers/of/of_pci.c -> index 5751dc5..b171d02 100644 -> --- a/drivers/of/of_pci.c -> +++ b/drivers/of/of_pci.c -> @@ -198,6 +198,7 @@ int of_pci_get_host_bridge_resources(struct -> device_node *dev, -> -> pr_debug("Parsing ranges property...\n"); -> for_each_of_pci_range(&parser, &range) { -> + struct resource_entry *entry; -> /* Read next ranges element */ -> if ((range.flags & IORESOURCE_TYPE_BITS) == IORESOURCE_IO) -> snprintf(range_type, 4, " IO"); -> @@ -240,6 +241,9 @@ int of_pci_get_host_bridge_resources(struct -> device_node *dev, -> } -> -> pci_add_resource_offset(resources, res, res->start - -> range.pci_addr); -> + entry = list_last_entry(resources, struct resource_entry, -> node); -> + /*we are using __res for storing the PCI controller -> address*/ -> + entry->__res.start = range.bus_addr; -> } -> -> return 0; -> diff --git a/include/linux/of_address.h b/include/linux/of_address.h -> index d88e81b..865f96e 100644 -> --- a/include/linux/of_address.h -> +++ b/include/linux/of_address.h -> @@ -16,6 +16,7 @@ struct of_pci_range { -> u32 pci_space; -> u64 pci_addr; -> u64 cpu_addr; -> + u64 bus_addr; -> u64 size; -> u32 flags; -> }; -> -- -> 1.9.1 +QW55IGNvbW1lbnQgb24gdGhpcyBwYXRjaD8NCg0KVGhpcyBpcyBuZWVkZWQgYnkgIltQQVRDSCB2 +NCAyLzVdIFBDSTogZGVzaWdud2FyZTogQWRkIEFSTTY0IHN1cHBvcnQiDQoNClRoYW5rcw0KDQpH +YWINCg0KPiAtLS0tLU9yaWdpbmFsIE1lc3NhZ2UtLS0tLQ0KPiBGcm9tOiBHYWJyaWVsZSBQYW9s +b25pDQo+IFNlbnQ6IFR1ZXNkYXksIEp1bHkgMTQsIDIwMTUgMTE6NDcgQU0NCj4gVG86IEdhYnJp +ZWxlIFBhb2xvbmk7IGFybmRAYXJuZGIuZGU7IGxvcmVuem8ucGllcmFsaXNpQGFybS5jb207DQo+ +IFdhbmd6aG91IChCKTsgYmhlbGdhYXNAZ29vZ2xlLmNvbTsgcm9iaCtkdEBrZXJuZWwub3JnOw0K +PiBqYW1lcy5tb3JzZUBhcm0uY29tOyBMaXZpdS5EdWRhdUBhcm0uY29tDQo+IENjOiBsaW51eC1w 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a/a/content_digest b/N2/content_digest index 3859558..2be9839 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -37,135 +37,86 @@ "b\0" ] [ - "Any comment on this patch?\n", - "\n", - "This is needed by \"[PATCH v4 2/5] PCI: designware: Add ARM64 support\"\n", - "\n", - "Thanks\n", - "\n", - "Gab\n", - "\n", - "> -----Original Message-----\n", - "> From: Gabriele Paoloni\n", - "> Sent: Tuesday, July 14, 2015 11:47 AM\n", - "> To: Gabriele Paoloni; arnd\@arndb.de; lorenzo.pieralisi\@arm.com;\n", - "> Wangzhou (B); bhelgaas\@google.com; robh+dt\@kernel.org;\n", - "> james.morse\@arm.com; Liviu.Dudau\@arm.com\n", - "> Cc: linux-pci\@vger.kernel.org; linux-arm-kernel\@lists.infradead.org;\n", - "> devicetree\@vger.kernel.org; Yuanzhichang; Zhudacai; zhangjukuo;\n", - "> qiuzhenfa; Liguozhu (Kenneth)\n", - "> Subject: [PATCH v2] PCI: Store PCIe bus address in struct of_pci_range\n", - "> \n", - "> From: gabriele paoloni <gabriele.paoloni\@huawei.com>\n", - "> \n", - "> This patch is needed port PCIe designware to new DT parsing API\n", - "> As discussed in\n", - "> http://lists.infradead.org/pipermail/linux-arm-kernel/2015-\n", - "> January/317743.html\n", - "> in designware we have a problem as the PCI addresses in the PCIe\n", - "> controller\n", - "> address space are required in order to perform correct HW operation.\n", - "> \n", - "> In order to solve this problem commit\n", - "> f4c55c5a3 \"PCI: designware: Program ATU with untranslated address\"\n", - "> added code to read the PCIe controller start address directly from\n", - "> the\n", - "> DT ranges.\n", - "> \n", - "> In the new DT parsing API of_pci_get_host_bridge_resources() hides\n", - "> the\n", - "> DT parser from the host controller drivers, so it is not possible\n", - "> for drivers to parse values directly from the DT.\n", - "> \n", - "> In http://www.spinics.net/lists/linux-pci/msg42540.html we already\n", - "> tried\n", - "> to use the new DT parsing API but there is a bug (obviously) in\n", - "> setting\n", - "> the <*>_mod_base addresses\n", - "> Applying this patch we can easily set \"<*>_mod_base = win-\n", - "> >__res.start\"\n", - "> \n", - "> This patch adds a new field in \"struct of_pci_range\" to store the\n", - "> pci bus start address; it fills the field in\n", - "> of_pci_range_parser_one();\n", - "> in of_pci_get_host_bridge_resources() it retrieves the resource\n", - "> entry\n", - "> after it is created and added to the resource list and uses\n", - "> entry->__res.start to store the pci controller address\n", - "> \n", - "> the patch is based on 4.2-rc1\n", - "> \n", - "> Signed-off-by: Gabriele Paoloni <gabriele.paoloni\@huawei.com>\n", - "> ---\n", - "> drivers/of/address.c | 2 ++\n", - "> drivers/of/of_pci.c | 4 ++++\n", - "> include/linux/of_address.h | 1 +\n", - "> 3 files changed, 7 insertions(+)\n", - "> \n", - "> diff --git a/drivers/of/address.c b/drivers/of/address.c\n", - "> index 8bfda6a..23a5793 100644\n", - "> --- a/drivers/of/address.c\n", - "> +++ b/drivers/of/address.c\n", - "> \@\@ -253,6 +253,7 \@\@ struct of_pci_range *of_pci_range_parser_one(struct\n", - "> of_pci_range_parser *parser,\n", - "> \t\t\t\t\t\tstruct of_pci_range *range)\n", - "> {\n", - "> \tconst int na = 3, ns = 2;\n", - "> +\tconst int p_ns = of_n_size_cells(parser->node);\n", - "> \n", - "> \tif (!range)\n", - "> \t\treturn NULL;\n", - "> \@\@ -265,6 +266,7 \@\@ struct of_pci_range *of_pci_range_parser_one(struct\n", - "> of_pci_range_parser *parser,\n", - "> \trange->pci_addr = of_read_number(parser->range + 1, ns);\n", - "> \trange->cpu_addr = of_translate_address(parser->node,\n", - "> \t\t\t\tparser->range + na);\n", - "> +\trange->bus_addr = of_read_number(parser->range + na, p_ns);\n", - "> \trange->size = of_read_number(parser->range + parser->pna + na,\n", - "> ns);\n", - "> \n", - "> \tparser->range += parser->np;\n", - "> diff --git a/drivers/of/of_pci.c b/drivers/of/of_pci.c\n", - "> index 5751dc5..b171d02 100644\n", - "> --- a/drivers/of/of_pci.c\n", - "> +++ b/drivers/of/of_pci.c\n", - "> \@\@ -198,6 +198,7 \@\@ int of_pci_get_host_bridge_resources(struct\n", - "> device_node *dev,\n", - "> \n", - "> \tpr_debug(\"Parsing ranges property...\\n\");\n", - "> \tfor_each_of_pci_range(&parser, &range) {\n", - "> +\t\tstruct resource_entry *entry;\n", - "> \t\t/* Read next ranges element */\n", - "> \t\tif ((range.flags & IORESOURCE_TYPE_BITS) == IORESOURCE_IO)\n", - "> \t\t\tsnprintf(range_type, 4, \" IO\");\n", - "> \@\@ -240,6 +241,9 \@\@ int of_pci_get_host_bridge_resources(struct\n", - "> device_node *dev,\n", - "> \t\t}\n", - "> \n", - "> \t\tpci_add_resource_offset(resources, res,\tres->start -\n", - "> range.pci_addr);\n", - "> +\t\tentry = list_last_entry(resources, struct resource_entry,\n", - "> node);\n", - "> +\t\t/*we are using __res for storing the PCI controller\n", - "> address*/\n", - "> +\t\tentry->__res.start = range.bus_addr;\n", - "> \t}\n", - "> \n", - "> \treturn 0;\n", - "> diff --git a/include/linux/of_address.h b/include/linux/of_address.h\n", - "> index d88e81b..865f96e 100644\n", - "> --- a/include/linux/of_address.h\n", - "> +++ b/include/linux/of_address.h\n", - "> \@\@ -16,6 +16,7 \@\@ struct of_pci_range {\n", - "> \tu32 pci_space;\n", - "> \tu64 pci_addr;\n", - "> \tu64 cpu_addr;\n", - "> +\tu64 bus_addr;\n", - "> \tu64 size;\n", - "> \tu32 flags;\n", - "> };\n", - "> --\n", - "> 1.9.1" + "QW55IGNvbW1lbnQgb24gdGhpcyBwYXRjaD8NCg0KVGhpcyBpcyBuZWVkZWQgYnkgIltQQVRDSCB2\n", + "NCAyLzVdIFBDSTogZGVzaWdud2FyZTogQWRkIEFSTTY0IHN1cHBvcnQiDQoNClRoYW5rcw0KDQpH\n", + "YWINCg0KPiAtLS0tLU9yaWdpbmFsIE1lc3NhZ2UtLS0tLQ0KPiBGcm9tOiBHYWJyaWVsZSBQYW9s\n", + "b25pDQo+IFNlbnQ6IFR1ZXNkYXksIEp1bHkgMTQsIDIwMTUgMTE6NDcgQU0NCj4gVG86IEdhYnJp\n", + "ZWxlIFBhb2xvbmk7IGFybmRAYXJuZGIuZGU7IGxvcmVuem8ucGllcmFsaXNpQGFybS5jb207DQo+\n", + "IFdhbmd6aG91IChCKTsgYmhlbGdhYXNAZ29vZ2xlLmNvbTsgcm9iaCtkdEBrZXJuZWwub3JnOw0K\n", + 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