* [U-Boot] [PATCH v2] Revert "spi: cadence_qspi_apb: Use 32 bit indirect read transaction when possible"
@ 2017-11-17 6:54 Goldschmidt Simon
2017-11-17 10:27 ` Vignesh R
0 siblings, 1 reply; 2+ messages in thread
From: Goldschmidt Simon @ 2017-11-17 6:54 UTC (permalink / raw
To: u-boot
This reverts commit b63b46313ed29e9b0c36b3d6b9407f6eade40c8f.
This commit changed cadence_qspi_apb to use bouncebuf.c, which invalidates
the data cache after reading. This is meant for dma transfers only and
breaks the cadence_qspi driver which copies via cpu only: data that is
copied by the cpu is in cache only and the cache invalidation at the end
throws away this data.
Signed-off-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com>
---
Changes for v2:
- Rebased on top of Jason's patchset v4 "Sync DT bindings with Linux"
drivers/spi/cadence_qspi_apb.c | 22 ++++++----------------
1 file changed, 6 insertions(+), 16 deletions(-)
diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c
index 8309ab8794..c7cb33aa8f 100644
--- a/drivers/spi/cadence_qspi_apb.c
+++ b/drivers/spi/cadence_qspi_apb.c
@@ -627,8 +627,6 @@ int cadence_qspi_apb_indirect_read_execute(struct cadence_spi_platdata *plat,
{
unsigned int remaining = n_rx;
unsigned int bytes_to_read = 0;
- struct bounce_buffer bb;
- u8 *bb_rxbuf;
int ret;
writel(n_rx, plat->regbase + CQSPI_REG_INDIRECTRDBYTES);
@@ -637,11 +635,6 @@ int cadence_qspi_apb_indirect_read_execute(struct cadence_spi_platdata *plat,
writel(CQSPI_REG_INDIRECTRD_START,
plat->regbase + CQSPI_REG_INDIRECTRD);
- ret = bounce_buffer_start(&bb, (void *)rxbuf, n_rx, GEN_BB_WRITE);
- if (ret)
- return ret;
- bb_rxbuf = bb.bounce_buffer;
-
while (remaining > 0) {
ret = cadence_qspi_wait_for_data(plat);
if (ret < 0) {
@@ -655,13 +648,12 @@ int cadence_qspi_apb_indirect_read_execute(struct cadence_spi_platdata *plat,
bytes_to_read *= plat->fifo_width;
bytes_to_read = bytes_to_read > remaining ?
remaining : bytes_to_read;
- readsl(plat->ahbbase, bb_rxbuf, bytes_to_read >> 2);
- if (bytes_to_read % 4)
- readsb(plat->ahbbase,
- bb_rxbuf + rounddown(bytes_to_read, 4),
- bytes_to_read % 4);
-
- bb_rxbuf += bytes_to_read;
+ /* Handle non-4-byte aligned access to avoid data abort. */
+ if (((uintptr_t)rxbuf % 4) || (bytes_to_read % 4))
+ readsb(plat->ahbbase, rxbuf, bytes_to_read);
+ else
+ readsl(plat->ahbbase, rxbuf, bytes_to_read >> 2);
+ rxbuf += bytes_to_read;
remaining -= bytes_to_read;
bytes_to_read = cadence_qspi_get_rd_sram_level(plat);
}
@@ -678,7 +670,6 @@ int cadence_qspi_apb_indirect_read_execute(struct cadence_spi_platdata *plat,
/* Clear indirect completion status */
writel(CQSPI_REG_INDIRECTRD_DONE,
plat->regbase + CQSPI_REG_INDIRECTRD);
- bounce_buffer_stop(&bb);
return 0;
@@ -686,7 +677,6 @@ failrd:
/* Cancel the indirect read */
writel(CQSPI_REG_INDIRECTRD_CANCEL,
plat->regbase + CQSPI_REG_INDIRECTRD);
- bounce_buffer_stop(&bb);
return ret;
}
--
2.12.2.windows.2
^ permalink raw reply related [flat|nested] 2+ messages in thread
* [U-Boot] [PATCH v2] Revert "spi: cadence_qspi_apb: Use 32 bit indirect read transaction when possible"
2017-11-17 6:54 [U-Boot] [PATCH v2] Revert "spi: cadence_qspi_apb: Use 32 bit indirect read transaction when possible" Goldschmidt Simon
@ 2017-11-17 10:27 ` Vignesh R
0 siblings, 0 replies; 2+ messages in thread
From: Vignesh R @ 2017-11-17 10:27 UTC (permalink / raw
To: u-boot
On Friday 17 November 2017 12:24 PM, Goldschmidt Simon wrote:
> This reverts commit b63b46313ed29e9b0c36b3d6b9407f6eade40c8f.
>
> This commit changed cadence_qspi_apb to use bouncebuf.c, which invalidates
> the data cache after reading. This is meant for dma transfers only and
> breaks the cadence_qspi driver which copies via cpu only: data that is
> copied by the cpu is in cache only and the cache invalidation at the end
> throws away this data.
>
> Signed-off-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com>
> ---
>
Acked-by: Vignesh R <vigneshr@ti.com>
Thanks
Vignesh
> Changes for v2:
> - Rebased on top of Jason's patchset v4 "Sync DT bindings with Linux"
>
> drivers/spi/cadence_qspi_apb.c | 22 ++++++----------------
> 1 file changed, 6 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c
> index 8309ab8794..c7cb33aa8f 100644
> --- a/drivers/spi/cadence_qspi_apb.c
> +++ b/drivers/spi/cadence_qspi_apb.c
> @@ -627,8 +627,6 @@ int cadence_qspi_apb_indirect_read_execute(struct cadence_spi_platdata *plat,
> {
> unsigned int remaining = n_rx;
> unsigned int bytes_to_read = 0;
> - struct bounce_buffer bb;
> - u8 *bb_rxbuf;
> int ret;
>
> writel(n_rx, plat->regbase + CQSPI_REG_INDIRECTRDBYTES);
> @@ -637,11 +635,6 @@ int cadence_qspi_apb_indirect_read_execute(struct cadence_spi_platdata *plat,
> writel(CQSPI_REG_INDIRECTRD_START,
> plat->regbase + CQSPI_REG_INDIRECTRD);
>
> - ret = bounce_buffer_start(&bb, (void *)rxbuf, n_rx, GEN_BB_WRITE);
> - if (ret)
> - return ret;
> - bb_rxbuf = bb.bounce_buffer;
> -
> while (remaining > 0) {
> ret = cadence_qspi_wait_for_data(plat);
> if (ret < 0) {
> @@ -655,13 +648,12 @@ int cadence_qspi_apb_indirect_read_execute(struct cadence_spi_platdata *plat,
> bytes_to_read *= plat->fifo_width;
> bytes_to_read = bytes_to_read > remaining ?
> remaining : bytes_to_read;
> - readsl(plat->ahbbase, bb_rxbuf, bytes_to_read >> 2);
> - if (bytes_to_read % 4)
> - readsb(plat->ahbbase,
> - bb_rxbuf + rounddown(bytes_to_read, 4),
> - bytes_to_read % 4);
> -
> - bb_rxbuf += bytes_to_read;
> + /* Handle non-4-byte aligned access to avoid data abort. */
> + if (((uintptr_t)rxbuf % 4) || (bytes_to_read % 4))
> + readsb(plat->ahbbase, rxbuf, bytes_to_read);
> + else
> + readsl(plat->ahbbase, rxbuf, bytes_to_read >> 2);
> + rxbuf += bytes_to_read;
> remaining -= bytes_to_read;
> bytes_to_read = cadence_qspi_get_rd_sram_level(plat);
> }
> @@ -678,7 +670,6 @@ int cadence_qspi_apb_indirect_read_execute(struct cadence_spi_platdata *plat,
> /* Clear indirect completion status */
> writel(CQSPI_REG_INDIRECTRD_DONE,
> plat->regbase + CQSPI_REG_INDIRECTRD);
> - bounce_buffer_stop(&bb);
>
> return 0;
>
> @@ -686,7 +677,6 @@ failrd:
> /* Cancel the indirect read */
> writel(CQSPI_REG_INDIRECTRD_CANCEL,
> plat->regbase + CQSPI_REG_INDIRECTRD);
> - bounce_buffer_stop(&bb);
> return ret;
> }
>
>
--
Regards
Vignesh
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2017-11-17 6:54 [U-Boot] [PATCH v2] Revert "spi: cadence_qspi_apb: Use 32 bit indirect read transaction when possible" Goldschmidt Simon
2017-11-17 10:27 ` Vignesh R
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