From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751701AbbGMKUN (ORCPT ); Mon, 13 Jul 2015 06:20:13 -0400 Received: from mail02.rohde-schwarz.com ([80.246.32.97]:61507 "EHLO mail02.rohde-schwarz.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751239AbbGMKUJ (ORCPT ); Mon, 13 Jul 2015 06:20:09 -0400 X-Greylist: delayed 906 seconds by postgrey-1.27 at vger.kernel.org; Mon, 13 Jul 2015 06:20:08 EDT In-Reply-To: <1436445895-25504-1-git-send-email-ranjit.waghmode@xilinx.com> References: <1436445895-25504-1-git-send-email-ranjit.waghmode@xilinx.com> To: Ranjit Waghmode Cc: ben@decadent.org.uk, broonie@kernel.org, computersforpeace@gmail.com, dwmw2@infradead.org, harinik@xilinx.com, juhosg@openwrt.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, "linux-mtd" , linux-spi@vger.kernel.org, marex@denx.de, michal.simek@xilinx.com, punnaia@xilinx.com, ran27jit@gmail.com, shijie.huang@intel.com, soren.brinkmann@xilinx.com, zajec5@gmail.com MIME-Version: 1.0 Subject: Re: [RFC PATCH 0/2] spi: add dual parallel & stacked mode support in Zynq MPSoC GQSPI controller X-KeepSent: DDDA0AA7:A583461A-C1257E81:0030FCED; type=4; flags=0; name=$KeepSent X-Mailer: Lotus Notes Release 8.5.3FP6 SHF416 February 28, 2015 From: Thomas.Betker@rohde-schwarz.com Message-ID: Date: Mon, 13 Jul 2015 12:04:54 +0200 X-RUS_SENSITIVITY: 10 X-MIMETrack: Itemize by SMTP Server on RSSMTP02/RSSMTP at 13.07.2015 12:04:57, Serialize by Router on RSSMTP02/RSSMTP at 13.07.2015 12:20:08, Serialize complete at 13.07.2015 12:20:08 X-TNEFEvaluated: 1 Content-Type: text/plain; charset="US-ASCII" Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hello Ranjit: > What is dual parallel mode? > --------------------------- > ZynqMP GQSPI controller supports Dual Parallel mode with following > functionalities: > 1) Supporting two SPI flash memories operating in parallel. 8 I/O lines. > 2) Chip selects and clock are shared to both the flash devices > 3) This mode is targeted for faster read/write speed and also doubles the size > 4) Commands/data can be transmitted/received from both the devices(mirror), > or only upper or only lower flash memory devices. > 5) Data arrangement: > With stripe enabled, > Even bytes i.e. 0, 2, 4,... are transmitted on Lower Data Bus > Odd bytes i.e. 1, 3, 5,.. are transmitted on Upper Data Bus. In the dual-parallel configuration, odd and even _bits_ of each byte are distributed over the flash chips; I am assuming this works just as in Zynq QSPI (apparently, the TRM for ZynqMP isn't out yet). Striping seems to be a different mechanism, though. Can you explain it a bit more? Also, the wording seems to indicate that it belongs to dual-stacked rather than dual-parallel. > Suggestions on MTD layer support > -------------------------------- > In order to add above two specified modes, we may required to get some > support from MTD layer. > > I'm trying to list the dependencies as follows: > 1) Support for two flashes > 2) Enable/Disable data stripe as and when required. > 3) May need to update read_sr() to get status of both flashes > 4) May also need to update read_fsr() to get status of both flashes > 5) Adjustment of offset value based on the parallel/stacked mode configuration > 6) Setting either parallel or stacked mode during the scan process. > 7) In case of stacked mode, is there a MTD concatenation support? In addition to 5), the MTD driver using a dual-parallel QSPI flash has to 5a) add padding at the start of data for unaligned addresses, 5b) add padding at the end of data for unaligned lengths. Best regards, Thomas Betker From mboxrd@z Thu Jan 1 00:00:00 1970 From: Thomas.Betker@rohde-schwarz.com (Thomas.Betker at rohde-schwarz.com) Date: Mon, 13 Jul 2015 12:04:54 +0200 Subject: [RFC PATCH 0/2] spi: add dual parallel & stacked mode support in Zynq MPSoC GQSPI controller In-Reply-To: <1436445895-25504-1-git-send-email-ranjit.waghmode@xilinx.com> References: <1436445895-25504-1-git-send-email-ranjit.waghmode@xilinx.com> Message-ID: To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Hello Ranjit: > What is dual parallel mode? > --------------------------- > ZynqMP GQSPI controller supports Dual Parallel mode with following > functionalities: > 1) Supporting two SPI flash memories operating in parallel. 8 I/O lines. > 2) Chip selects and clock are shared to both the flash devices > 3) This mode is targeted for faster read/write speed and also doubles the size > 4) Commands/data can be transmitted/received from both the devices(mirror), > or only upper or only lower flash memory devices. > 5) Data arrangement: > With stripe enabled, > Even bytes i.e. 0, 2, 4,... are transmitted on Lower Data Bus > Odd bytes i.e. 1, 3, 5,.. are transmitted on Upper Data Bus. In the dual-parallel configuration, odd and even _bits_ of each byte are distributed over the flash chips; I am assuming this works just as in Zynq QSPI (apparently, the TRM for ZynqMP isn't out yet). Striping seems to be a different mechanism, though. Can you explain it a bit more? Also, the wording seems to indicate that it belongs to dual-stacked rather than dual-parallel. > Suggestions on MTD layer support > -------------------------------- > In order to add above two specified modes, we may required to get some > support from MTD layer. > > I'm trying to list the dependencies as follows: > 1) Support for two flashes > 2) Enable/Disable data stripe as and when required. > 3) May need to update read_sr() to get status of both flashes > 4) May also need to update read_fsr() to get status of both flashes > 5) Adjustment of offset value based on the parallel/stacked mode configuration > 6) Setting either parallel or stacked mode during the scan process. > 7) In case of stacked mode, is there a MTD concatenation support? In addition to 5), the MTD driver using a dual-parallel QSPI flash has to 5a) add padding at the start of data for unaligned addresses, 5b) add padding at the end of data for unaligned lengths. Best regards, Thomas Betker From mboxrd@z Thu Jan 1 00:00:00 1970 From: Thomas.Betker@rohde-schwarz.com Subject: Re: [RFC PATCH 0/2] spi: add dual parallel & stacked mode support in Zynq MPSoC GQSPI controller Date: Mon, 13 Jul 2015 12:04:54 +0200 Message-ID: References: <1436445895-25504-1-git-send-email-ranjit.waghmode@xilinx.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Cc: linux-mtd , harinik@xilinx.com, marex@denx.de, ben@decadent.org.uk, zajec5@gmail.com, linux-kernel@vger.kernel.org, linux-spi@vger.kernel.org, juhosg@openwrt.org, broonie@kernel.org, linux-mtd@lists.infradead.org, soren.brinkmann@xilinx.com, shijie.huang@intel.com, punnaia@xilinx.com, ran27jit@gmail.com, computersforpeace@gmail.com, dwmw2@infradead.org, michal.simek@xilinx.com, linux-arm-kernel@lists.infradead.org To: Ranjit Waghmode Return-path: In-Reply-To: <1436445895-25504-1-git-send-email-ranjit.waghmode@xilinx.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=m.gmane.org@lists.infradead.org List-Id: linux-spi.vger.kernel.org Hello Ranjit: > What is dual parallel mode? > --------------------------- > ZynqMP GQSPI controller supports Dual Parallel mode with following > functionalities: > 1) Supporting two SPI flash memories operating in parallel. 8 I/O lines. > 2) Chip selects and clock are shared to both the flash devices > 3) This mode is targeted for faster read/write speed and also doubles the size > 4) Commands/data can be transmitted/received from both the devices(mirror), > or only upper or only lower flash memory devices. > 5) Data arrangement: > With stripe enabled, > Even bytes i.e. 0, 2, 4,... are transmitted on Lower Data Bus > Odd bytes i.e. 1, 3, 5,.. are transmitted on Upper Data Bus. In the dual-parallel configuration, odd and even _bits_ of each byte are distributed over the flash chips; I am assuming this works just as in Zynq QSPI (apparently, the TRM for ZynqMP isn't out yet). Striping seems to be a different mechanism, though. Can you explain it a bit more? Also, the wording seems to indicate that it belongs to dual-stacked rather than dual-parallel. > Suggestions on MTD layer support > -------------------------------- > In order to add above two specified modes, we may required to get some > support from MTD layer. > > I'm trying to list the dependencies as follows: > 1) Support for two flashes > 2) Enable/Disable data stripe as and when required. > 3) May need to update read_sr() to get status of both flashes > 4) May also need to update read_fsr() to get status of both flashes > 5) Adjustment of offset value based on the parallel/stacked mode configuration > 6) Setting either parallel or stacked mode during the scan process. > 7) In case of stacked mode, is there a MTD concatenation support? In addition to 5), the MTD driver using a dual-parallel QSPI flash has to 5a) add padding at the start of data for unaligned addresses, 5b) add padding at the end of data for unaligned lengths. Best regards, Thomas Betker