* [PATCH] drm/amd/amdgpu: add pipe1 hardware support
@ 2024-03-15 6:12 ZhenGuo Yin
2024-03-26 12:28 ` Yin, ZhenGuo (Chris)
0 siblings, 1 reply; 3+ messages in thread
From: ZhenGuo Yin @ 2024-03-15 6:12 UTC (permalink / raw
To: amd-gfx
Cc: mdaenzer, alexander.deucher, christian.koenig,
Arunpravin.PaneerSelvam, emily.deng, monk.liu, ZhenGuo Yin
Enable pipe1 support starting from SIENNA CICHLID asic.
Need to use correct ref/mask for pipe1 hdp flush.
Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/2117
Fixes: 085292c3d780 ("Revert "drm/amd/amdgpu: add pipe1 hardware support"")
Signed-off-by: ZhenGuo Yin <zhenguo.yin@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index f90905ef32c7..5eb6f189920b 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -4518,7 +4518,7 @@ static int gfx_v10_0_sw_init(void *handle)
case IP_VERSION(10, 3, 3):
case IP_VERSION(10, 3, 7):
adev->gfx.me.num_me = 1;
- adev->gfx.me.num_pipe_per_me = 1;
+ adev->gfx.me.num_pipe_per_me = 2;
adev->gfx.me.num_queue_per_pipe = 1;
adev->gfx.mec.num_mec = 2;
adev->gfx.mec.num_pipe_per_mec = 4;
@@ -8317,7 +8317,7 @@ static void gfx_v10_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
}
reg_mem_engine = 0;
} else {
- ref_and_mask = nbio_hf_reg->ref_and_mask_cp0;
+ ref_and_mask = nbio_hf_reg->ref_and_mask_cp0 << ring->pipe;
reg_mem_engine = 1; /* pfp */
}
--
2.35.1
^ permalink raw reply related [flat|nested] 3+ messages in thread
* RE: [PATCH] drm/amd/amdgpu: add pipe1 hardware support
2024-03-15 6:12 [PATCH] drm/amd/amdgpu: add pipe1 hardware support ZhenGuo Yin
@ 2024-03-26 12:28 ` Yin, ZhenGuo (Chris)
2024-03-26 13:17 ` Alex Deucher
0 siblings, 1 reply; 3+ messages in thread
From: Yin, ZhenGuo (Chris) @ 2024-03-26 12:28 UTC (permalink / raw
To: amd-gfx@lists.freedesktop.org
Cc: mdaenzer@redhat.com, Deucher, Alexander, Koenig, Christian,
Paneer Selvam, Arunpravin, Deng, Emily, Liu, Monk
[AMD Official Use Only - General]
Hi, Alex
Could you please help to review this patch?
This should fix the bug: https://gitlab.freedesktop.org/drm/amd/-/issues/2117.
Thx.
Best,
Zhenguo
Cloud-GPU Core team, SRDC
-----Original Message-----
From: Yin, ZhenGuo (Chris) <ZhenGuo.Yin@amd.com>
Sent: Friday, March 15, 2024 2:12 PM
To: amd-gfx@lists.freedesktop.org
Cc: mdaenzer@redhat.com; Deucher, Alexander <Alexander.Deucher@amd.com>; Koenig, Christian <Christian.Koenig@amd.com>; Paneer Selvam, Arunpravin <Arunpravin.PaneerSelvam@amd.com>; Deng, Emily <Emily.Deng@amd.com>; Liu, Monk <Monk.Liu@amd.com>; Yin, ZhenGuo (Chris) <ZhenGuo.Yin@amd.com>
Subject: [PATCH] drm/amd/amdgpu: add pipe1 hardware support
Enable pipe1 support starting from SIENNA CICHLID asic.
Need to use correct ref/mask for pipe1 hdp flush.
Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/2117
Fixes: 085292c3d780 ("Revert "drm/amd/amdgpu: add pipe1 hardware support"")
Signed-off-by: ZhenGuo Yin <zhenguo.yin@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index f90905ef32c7..5eb6f189920b 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -4518,7 +4518,7 @@ static int gfx_v10_0_sw_init(void *handle)
case IP_VERSION(10, 3, 3):
case IP_VERSION(10, 3, 7):
adev->gfx.me.num_me = 1;
- adev->gfx.me.num_pipe_per_me = 1;
+ adev->gfx.me.num_pipe_per_me = 2;
adev->gfx.me.num_queue_per_pipe = 1;
adev->gfx.mec.num_mec = 2;
adev->gfx.mec.num_pipe_per_mec = 4;
@@ -8317,7 +8317,7 @@ static void gfx_v10_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
}
reg_mem_engine = 0;
} else {
- ref_and_mask = nbio_hf_reg->ref_and_mask_cp0;
+ ref_and_mask = nbio_hf_reg->ref_and_mask_cp0 << ring->pipe;
reg_mem_engine = 1; /* pfp */
}
--
2.35.1
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH] drm/amd/amdgpu: add pipe1 hardware support
2024-03-26 12:28 ` Yin, ZhenGuo (Chris)
@ 2024-03-26 13:17 ` Alex Deucher
0 siblings, 0 replies; 3+ messages in thread
From: Alex Deucher @ 2024-03-26 13:17 UTC (permalink / raw
To: Yin, ZhenGuo (Chris)
Cc: amd-gfx@lists.freedesktop.org, mdaenzer@redhat.com,
Deucher, Alexander, Koenig, Christian, Paneer Selvam, Arunpravin,
Deng, Emily, Liu, Monk
On Tue, Mar 26, 2024 at 8:28 AM Yin, ZhenGuo (Chris)
<ZhenGuo.Yin@amd.com> wrote:
>
> [AMD Official Use Only - General]
>
> Hi, Alex
>
> Could you please help to review this patch?
> This should fix the bug: https://gitlab.freedesktop.org/drm/amd/-/issues/2117.
Please split this into two patches. The HDP fix is a standalone bug
fix. Please also add:
Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2117
With those changes, the patch is:
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
>
> Thx.
>
> Best,
> Zhenguo
> Cloud-GPU Core team, SRDC
>
> -----Original Message-----
> From: Yin, ZhenGuo (Chris) <ZhenGuo.Yin@amd.com>
> Sent: Friday, March 15, 2024 2:12 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: mdaenzer@redhat.com; Deucher, Alexander <Alexander.Deucher@amd.com>; Koenig, Christian <Christian.Koenig@amd.com>; Paneer Selvam, Arunpravin <Arunpravin.PaneerSelvam@amd.com>; Deng, Emily <Emily.Deng@amd.com>; Liu, Monk <Monk.Liu@amd.com>; Yin, ZhenGuo (Chris) <ZhenGuo.Yin@amd.com>
> Subject: [PATCH] drm/amd/amdgpu: add pipe1 hardware support
>
> Enable pipe1 support starting from SIENNA CICHLID asic.
> Need to use correct ref/mask for pipe1 hdp flush.
>
> Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/2117
> Fixes: 085292c3d780 ("Revert "drm/amd/amdgpu: add pipe1 hardware support"")
> Signed-off-by: ZhenGuo Yin <zhenguo.yin@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> index f90905ef32c7..5eb6f189920b 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> @@ -4518,7 +4518,7 @@ static int gfx_v10_0_sw_init(void *handle)
> case IP_VERSION(10, 3, 3):
> case IP_VERSION(10, 3, 7):
> adev->gfx.me.num_me = 1;
> - adev->gfx.me.num_pipe_per_me = 1;
> + adev->gfx.me.num_pipe_per_me = 2;
> adev->gfx.me.num_queue_per_pipe = 1;
> adev->gfx.mec.num_mec = 2;
> adev->gfx.mec.num_pipe_per_mec = 4;
> @@ -8317,7 +8317,7 @@ static void gfx_v10_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
> }
> reg_mem_engine = 0;
> } else {
> - ref_and_mask = nbio_hf_reg->ref_and_mask_cp0;
> + ref_and_mask = nbio_hf_reg->ref_and_mask_cp0 << ring->pipe;
> reg_mem_engine = 1; /* pfp */
> }
>
> --
> 2.35.1
>
^ permalink raw reply [flat|nested] 3+ messages in thread
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2024-03-15 6:12 [PATCH] drm/amd/amdgpu: add pipe1 hardware support ZhenGuo Yin
2024-03-26 12:28 ` Yin, ZhenGuo (Chris)
2024-03-26 13:17 ` Alex Deucher
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