* [PATCH 1/4] Define ePMP mseccfg
[not found] <20200808052031.19523-1-weiying_hou@outlook.com>
@ 2020-08-08 5:20 ` Hou Weiying
2020-08-08 5:20 ` Hou Weiying
` (2 subsequent siblings)
3 siblings, 0 replies; 12+ messages in thread
From: Hou Weiying @ 2020-08-08 5:20 UTC (permalink / raw
To: qemu-riscv, qemu-devel
Cc: sagark, kbastian, Hongzheng-Li, Alistair.Francis, Myriad-Dreamin,
palmer
Currently using 0x390 and 0x391 for x-epmp (experimental). This may change in the future spec.
Signed-off-by: Hongzheng-Li <Ethan.Lee.QNL@gmail.com>
Signed-off-by: Hou Weiying <weiying_hou@outlook.com>
Signed-off-by: Myriad-Dreamin <camiyoru@gmail.com>
---
target/riscv/cpu_bits.h | 3 +++
target/riscv/gdbstub.c | 2 ++
2 files changed, 5 insertions(+)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 7f64ee1174..9a8a6be534 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -214,6 +214,9 @@
#define CSR_MTINST 0x34a
#define CSR_MTVAL2 0x34b
+/* Enhanced PMP */
+#define CSR_MSECCFG 0x390
+#define CSR_MSECCFGH 0x391
/* Physical Memory Protection */
#define CSR_PMPCFG0 0x3a0
#define CSR_PMPCFG1 0x3a1
diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
index eba12a86f2..de5551604a 100644
--- a/target/riscv/gdbstub.c
+++ b/target/riscv/gdbstub.c
@@ -132,6 +132,8 @@ static int csr_register_map[] = {
CSR_MIP,
CSR_MTINST,
CSR_MTVAL2,
+ CSR_MSECCFG,
+ CSR_MSECCFGH,
CSR_PMPCFG0,
CSR_PMPCFG1,
CSR_PMPCFG2,
--
2.20.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 1/4] Define ePMP mseccfg
@ 2020-08-08 5:20 ` Hou Weiying
0 siblings, 0 replies; 12+ messages in thread
From: Hou Weiying @ 2020-08-08 5:20 UTC (permalink / raw
To: qemu-riscv, qemu-devel
Cc: palmer, Alistair.Francis, sagark, kbastian, Hongzheng-Li,
Myriad-Dreamin
Currently using 0x390 and 0x391 for x-epmp (experimental). This may change in the future spec.
Signed-off-by: Hongzheng-Li <Ethan.Lee.QNL@gmail.com>
Signed-off-by: Hou Weiying <weiying_hou@outlook.com>
Signed-off-by: Myriad-Dreamin <camiyoru@gmail.com>
---
target/riscv/cpu_bits.h | 3 +++
target/riscv/gdbstub.c | 2 ++
2 files changed, 5 insertions(+)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 7f64ee1174..9a8a6be534 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -214,6 +214,9 @@
#define CSR_MTINST 0x34a
#define CSR_MTVAL2 0x34b
+/* Enhanced PMP */
+#define CSR_MSECCFG 0x390
+#define CSR_MSECCFGH 0x391
/* Physical Memory Protection */
#define CSR_PMPCFG0 0x3a0
#define CSR_PMPCFG1 0x3a1
diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
index eba12a86f2..de5551604a 100644
--- a/target/riscv/gdbstub.c
+++ b/target/riscv/gdbstub.c
@@ -132,6 +132,8 @@ static int csr_register_map[] = {
CSR_MIP,
CSR_MTINST,
CSR_MTVAL2,
+ CSR_MSECCFG,
+ CSR_MSECCFGH,
CSR_PMPCFG0,
CSR_PMPCFG1,
CSR_PMPCFG2,
--
2.20.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 2/4] Implementation of enhanced PMP(ePMP) support
[not found] <20200808052031.19523-1-weiying_hou@outlook.com>
@ 2020-08-08 5:20 ` Hou Weiying
2020-08-08 5:20 ` Hou Weiying
` (2 subsequent siblings)
3 siblings, 0 replies; 12+ messages in thread
From: Hou Weiying @ 2020-08-08 5:20 UTC (permalink / raw
To: qemu-riscv, qemu-devel
Cc: sagark, kbastian, Hongzheng-Li, Alistair.Francis, Myriad-Dreamin,
palmer
The ePMP can be found in:
https://docs.google.com/document/d/1Mh_aiHYxemL0umN3GTTw8vsbmzHZ_nxZXgjgOUzbvc8/edit#heading=h.9wsr1lnxtwe2
Signed-off-by: Hongzheng-Li <Ethan.Lee.QNL@gmail.com>
Signed-off-by: Hou Weiying <weiying_hou@outlook.com>
Signed-off-by: Myriad-Dreamin <camiyoru@gmail.com>
---
target/riscv/pmp.c | 134 ++++++++++++++++++++++++++++++++++----
target/riscv/pmp.h | 12 ++++
target/riscv/trace-events | 4 ++
3 files changed, 138 insertions(+), 12 deletions(-)
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index 0e6b640fbd..8df389cecd 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -34,6 +34,26 @@ static void pmp_write_cfg(CPURISCVState *env, uint32_t addr_index,
static uint8_t pmp_read_cfg(CPURISCVState *env, uint32_t addr_index);
static void pmp_update_rule(CPURISCVState *env, uint32_t pmp_index);
+static char mode_to_char(int mode)
+{
+ char ret = 0;
+ switch (mode) {
+ case PRV_U:
+ ret = 'u';
+ break;
+ case PRV_S:
+ ret = 's';
+ break;
+ case PRV_H:
+ ret = 'h';
+ break;
+ case PRV_M:
+ ret = 'm';
+ break;
+ }
+ return ret;
+}
+
/*
* Accessor method to extract address matching type 'a field' from cfg reg
*/
@@ -99,7 +119,28 @@ static inline uint8_t pmp_read_cfg(CPURISCVState *env, uint32_t pmp_index)
static void pmp_write_cfg(CPURISCVState *env, uint32_t pmp_index, uint8_t val)
{
if (pmp_index < MAX_RISCV_PMPS) {
- if (!pmp_is_locked(env, pmp_index)) {
+ /*
+ * mseccfg.RLB is set
+ */
+ if (MSECCFG_RLB_ISSET(env) ||
+ /*
+ * mseccfg.MML is set
+ */
+ (MSECCFG_MML_ISSET(env) &&
+ /*
+ * m model and not adding X bit
+ */
+ (((val & PMP_LOCK) != 0 && (val & PMP_EXEC) != PMP_EXEC) ||
+ /*
+ * shared region and not adding X bit
+ */
+ ((val & PMP_LOCK) != PMP_LOCK &&
+ (val & 0x7) != (PMP_WRITE | PMP_EXEC)))) ||
+ /*
+ * mseccfg.MML is not set
+ */
+ (!MSECCFG_MML_ISSET(env) && !pmp_is_locked(env, pmp_index))
+ ){
env->pmp_state.pmp[pmp_index].cfg_reg = val;
pmp_update_rule(env, pmp_index);
} else {
@@ -230,6 +271,18 @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
/* Short cut if no rules */
if (0 == pmp_get_num_rules(env)) {
+ if (MSECCFG_MMWP_ISSET(env)) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "pmp violation - %c mode access denied\n",
+ mode_to_char(mode));
+ return false;
+ }
+ if (MSECCFG_MML_ISSET(env) && (mode != PRV_M || (privs & PMP_EXEC))) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "pmp violation - %c mode access denied\n",
+ mode_to_char(mode));
+ return false;
+ }
return true;
}
@@ -261,16 +314,65 @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
const uint8_t a_field =
pmp_get_a_field(env->pmp_state.pmp[i].cfg_reg);
- /*
- * If the PMP entry is not off and the address is in range, do the priv
- * check
- */
if (((s + e) == 2) && (PMP_AMATCH_OFF != a_field)) {
- allowed_privs = PMP_READ | PMP_WRITE | PMP_EXEC;
- if ((mode != PRV_M) || pmp_is_locked(env, i)) {
- allowed_privs &= env->pmp_state.pmp[i].cfg_reg;
+ /*
+ * If the PMP entry is not off and the address is in range,
+ * do the priv check
+ */
+ if (!MSECCFG_MML_ISSET(env)) {
+ /*
+ * If mseccfg.MML Bit is not set, do pmp priv check
+ */
+ allowed_privs = PMP_READ | PMP_WRITE | PMP_EXEC;
+ if ((mode != PRV_M) || pmp_is_locked(env, i)) {
+ allowed_privs &= env->pmp_state.pmp[i].cfg_reg;
+ }
+ } else {
+ /*
+ * If mseccfg.MML Bit set, do the enhanced pmp priv check
+ */
+ if (env->pmp_state.pmp[i].cfg_reg & PMP_LOCK) {
+ /*
+ * Shared Region
+ */
+ if ((env->pmp_state.pmp[i].cfg_reg &
+ (PMP_READ | PMP_WRITE)) == PMP_WRITE) {
+ allowed_privs = PMP_EXEC | ((mode == PRV_M &&
+ (env->pmp_state.pmp[i].cfg_reg & PMP_EXEC)) ?
+ PMP_READ : 0);
+ } else {
+ allowed_privs = env->pmp_state.pmp[i].cfg_reg &
+ (PMP_READ | PMP_WRITE | PMP_EXEC);
+
+ if (mode != PRV_M && allowed_privs) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "pmp violation - %c mode access denied\n",
+ mode_to_char(mode));
+ ret = 0;
+ break;
+ }
+ }
+ } else {
+ /*
+ * Shared Region
+ */
+ if ((env->pmp_state.pmp[i].cfg_reg &
+ (PMP_READ | PMP_WRITE)) == PMP_WRITE) {
+ allowed_privs = PMP_READ | ((mode == PRV_M ||
+ (env->pmp_state.pmp[i].cfg_reg & PMP_EXEC)) ?
+ PMP_WRITE : 0);
+ } else {
+ allowed_privs = env->pmp_state.pmp[i].cfg_reg &
+ (PMP_READ | PMP_WRITE | PMP_EXEC);
+ if (mode == PRV_M && allowed_privs) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "pmp violation - m mode access denied\n");
+ ret = 0;
+ break;
+ }
+ }
+ }
}
-
if ((privs & allowed_privs) == privs) {
ret = 1;
break;
@@ -284,15 +386,23 @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
/* No rule matched */
if (ret == -1) {
if (mode == PRV_M) {
- ret = 1; /* Privileged spec v1.10 states if no PMP entry matches an
- * M-Mode access, the access succeeds */
+ ret = !MSECCFG_MMWP_ISSET(env); /* PMP Enhancements */
+ if (MSECCFG_MML_ISSET(env) && (privs & PMP_EXEC)) {
+ ret = 0;
+ }
} else {
ret = 0; /* Other modes are not allowed to succeed if they don't
* match a rule, but there are rules. We've checked for
* no rule earlier in this function. */
}
}
-
+ if (ret) {
+ trace_pmp_hart_has_privs_pass_match(
+ env->mhartid, addr, size, privs, mode);
+ } else {
+ trace_pmp_hart_has_privs_violation(
+ env->mhartid, addr, size, privs, mode);
+ }
return ret == 1 ? true : false;
}
diff --git a/target/riscv/pmp.h b/target/riscv/pmp.h
index 8e19793132..7db2069204 100644
--- a/target/riscv/pmp.h
+++ b/target/riscv/pmp.h
@@ -36,6 +36,12 @@ typedef enum {
PMP_AMATCH_NAPOT /* Naturally aligned power-of-two region */
} pmp_am_t;
+typedef enum {
+ MSECCFG_MML = 1 << 0,
+ MSECCFG_MMWP = 1 << 1,
+ MSECCFG_RLB = 1 << 2
+} mseccfg_field_t;
+
typedef struct {
target_ulong addr_reg;
uint8_t cfg_reg;
@@ -58,7 +64,13 @@ target_ulong pmpcfg_csr_read(CPURISCVState *env, uint32_t reg_index);
void pmpaddr_csr_write(CPURISCVState *env, uint32_t addr_index,
target_ulong val);
target_ulong pmpaddr_csr_read(CPURISCVState *env, uint32_t addr_index);
+void mseccfg_csr_write(CPURISCVState *env, target_ulong val);
+target_ulong mseccfg_csr_read(CPURISCVState *env);
bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
target_ulong size, pmp_priv_t priv, target_ulong mode);
+#define MSECCFG_MML_ISSET(env) get_field(env->mseccfg, MSECCFG_MML)
+#define MSECCFG_MMWP_ISSET(env) get_field(env->mseccfg, MSECCFG_MMWP)
+#define MSECCFG_RLB_ISSET(env) get_field(env->mseccfg, MSECCFG_RLB)
+
#endif
diff --git a/target/riscv/trace-events b/target/riscv/trace-events
index 4b6c652ae9..4f877f90f7 100644
--- a/target/riscv/trace-events
+++ b/target/riscv/trace-events
@@ -6,3 +6,7 @@ pmpcfg_csr_read(uint64_t mhartid, uint32_t reg_index, uint64_t val) "hart %" PRI
pmpcfg_csr_write(uint64_t mhartid, uint32_t reg_index, uint64_t val) "hart %" PRIu64 ": write reg%" PRIu32", val: 0x%" PRIx64
pmpaddr_csr_read(uint64_t mhartid, uint32_t addr_index, uint64_t val) "hart %" PRIu64 ": read addr%" PRIu32", val: 0x%" PRIx64
pmpaddr_csr_write(uint64_t mhartid, uint32_t addr_index, uint64_t val) "hart %" PRIu64 ": write addr%" PRIu32", val: 0x%" PRIx64
+mseccfg_csr_read(uint64_t mhartid, uint64_t val) "hart %" PRIu64 ": read mseccfg, val: 0x%" PRIx64
+mseccfg_csr_write(uint64_t mhartid, uint64_t val) "hart %" PRIu64 ": write mseccfg, val: 0x%" PRIx64
+pmp_hart_has_privs_pass_match(uint64_t mhartid, uint64_t addr, uint64_t size, uint64_t privs, uint64_t mode) "hart %"PRId64 "pass PMP 0 match addr:%"PRIu64" size:%"PRIu64 "privs: %"PRIu64 "mode: %"PRIu64
+pmp_hart_has_privs_violation(uint64_t mhartid, uint64_t addr, uint64_t size, uint64_t privs, uint64_t mode) "hart %"PRId64 "pass PMP 0 match addr:%"PRIu64" size:%"PRIu64 "privs: %"PRIu64 "mode: %"PRIu64
--
2.20.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 2/4] Implementation of enhanced PMP(ePMP) support
@ 2020-08-08 5:20 ` Hou Weiying
0 siblings, 0 replies; 12+ messages in thread
From: Hou Weiying @ 2020-08-08 5:20 UTC (permalink / raw
To: qemu-riscv, qemu-devel
Cc: palmer, Alistair.Francis, sagark, kbastian, Hongzheng-Li,
Myriad-Dreamin
The ePMP can be found in:
https://docs.google.com/document/d/1Mh_aiHYxemL0umN3GTTw8vsbmzHZ_nxZXgjgOUzbvc8/edit#heading=h.9wsr1lnxtwe2
Signed-off-by: Hongzheng-Li <Ethan.Lee.QNL@gmail.com>
Signed-off-by: Hou Weiying <weiying_hou@outlook.com>
Signed-off-by: Myriad-Dreamin <camiyoru@gmail.com>
---
target/riscv/pmp.c | 134 ++++++++++++++++++++++++++++++++++----
target/riscv/pmp.h | 12 ++++
target/riscv/trace-events | 4 ++
3 files changed, 138 insertions(+), 12 deletions(-)
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index 0e6b640fbd..8df389cecd 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -34,6 +34,26 @@ static void pmp_write_cfg(CPURISCVState *env, uint32_t addr_index,
static uint8_t pmp_read_cfg(CPURISCVState *env, uint32_t addr_index);
static void pmp_update_rule(CPURISCVState *env, uint32_t pmp_index);
+static char mode_to_char(int mode)
+{
+ char ret = 0;
+ switch (mode) {
+ case PRV_U:
+ ret = 'u';
+ break;
+ case PRV_S:
+ ret = 's';
+ break;
+ case PRV_H:
+ ret = 'h';
+ break;
+ case PRV_M:
+ ret = 'm';
+ break;
+ }
+ return ret;
+}
+
/*
* Accessor method to extract address matching type 'a field' from cfg reg
*/
@@ -99,7 +119,28 @@ static inline uint8_t pmp_read_cfg(CPURISCVState *env, uint32_t pmp_index)
static void pmp_write_cfg(CPURISCVState *env, uint32_t pmp_index, uint8_t val)
{
if (pmp_index < MAX_RISCV_PMPS) {
- if (!pmp_is_locked(env, pmp_index)) {
+ /*
+ * mseccfg.RLB is set
+ */
+ if (MSECCFG_RLB_ISSET(env) ||
+ /*
+ * mseccfg.MML is set
+ */
+ (MSECCFG_MML_ISSET(env) &&
+ /*
+ * m model and not adding X bit
+ */
+ (((val & PMP_LOCK) != 0 && (val & PMP_EXEC) != PMP_EXEC) ||
+ /*
+ * shared region and not adding X bit
+ */
+ ((val & PMP_LOCK) != PMP_LOCK &&
+ (val & 0x7) != (PMP_WRITE | PMP_EXEC)))) ||
+ /*
+ * mseccfg.MML is not set
+ */
+ (!MSECCFG_MML_ISSET(env) && !pmp_is_locked(env, pmp_index))
+ ){
env->pmp_state.pmp[pmp_index].cfg_reg = val;
pmp_update_rule(env, pmp_index);
} else {
@@ -230,6 +271,18 @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
/* Short cut if no rules */
if (0 == pmp_get_num_rules(env)) {
+ if (MSECCFG_MMWP_ISSET(env)) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "pmp violation - %c mode access denied\n",
+ mode_to_char(mode));
+ return false;
+ }
+ if (MSECCFG_MML_ISSET(env) && (mode != PRV_M || (privs & PMP_EXEC))) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "pmp violation - %c mode access denied\n",
+ mode_to_char(mode));
+ return false;
+ }
return true;
}
@@ -261,16 +314,65 @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
const uint8_t a_field =
pmp_get_a_field(env->pmp_state.pmp[i].cfg_reg);
- /*
- * If the PMP entry is not off and the address is in range, do the priv
- * check
- */
if (((s + e) == 2) && (PMP_AMATCH_OFF != a_field)) {
- allowed_privs = PMP_READ | PMP_WRITE | PMP_EXEC;
- if ((mode != PRV_M) || pmp_is_locked(env, i)) {
- allowed_privs &= env->pmp_state.pmp[i].cfg_reg;
+ /*
+ * If the PMP entry is not off and the address is in range,
+ * do the priv check
+ */
+ if (!MSECCFG_MML_ISSET(env)) {
+ /*
+ * If mseccfg.MML Bit is not set, do pmp priv check
+ */
+ allowed_privs = PMP_READ | PMP_WRITE | PMP_EXEC;
+ if ((mode != PRV_M) || pmp_is_locked(env, i)) {
+ allowed_privs &= env->pmp_state.pmp[i].cfg_reg;
+ }
+ } else {
+ /*
+ * If mseccfg.MML Bit set, do the enhanced pmp priv check
+ */
+ if (env->pmp_state.pmp[i].cfg_reg & PMP_LOCK) {
+ /*
+ * Shared Region
+ */
+ if ((env->pmp_state.pmp[i].cfg_reg &
+ (PMP_READ | PMP_WRITE)) == PMP_WRITE) {
+ allowed_privs = PMP_EXEC | ((mode == PRV_M &&
+ (env->pmp_state.pmp[i].cfg_reg & PMP_EXEC)) ?
+ PMP_READ : 0);
+ } else {
+ allowed_privs = env->pmp_state.pmp[i].cfg_reg &
+ (PMP_READ | PMP_WRITE | PMP_EXEC);
+
+ if (mode != PRV_M && allowed_privs) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "pmp violation - %c mode access denied\n",
+ mode_to_char(mode));
+ ret = 0;
+ break;
+ }
+ }
+ } else {
+ /*
+ * Shared Region
+ */
+ if ((env->pmp_state.pmp[i].cfg_reg &
+ (PMP_READ | PMP_WRITE)) == PMP_WRITE) {
+ allowed_privs = PMP_READ | ((mode == PRV_M ||
+ (env->pmp_state.pmp[i].cfg_reg & PMP_EXEC)) ?
+ PMP_WRITE : 0);
+ } else {
+ allowed_privs = env->pmp_state.pmp[i].cfg_reg &
+ (PMP_READ | PMP_WRITE | PMP_EXEC);
+ if (mode == PRV_M && allowed_privs) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "pmp violation - m mode access denied\n");
+ ret = 0;
+ break;
+ }
+ }
+ }
}
-
if ((privs & allowed_privs) == privs) {
ret = 1;
break;
@@ -284,15 +386,23 @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
/* No rule matched */
if (ret == -1) {
if (mode == PRV_M) {
- ret = 1; /* Privileged spec v1.10 states if no PMP entry matches an
- * M-Mode access, the access succeeds */
+ ret = !MSECCFG_MMWP_ISSET(env); /* PMP Enhancements */
+ if (MSECCFG_MML_ISSET(env) && (privs & PMP_EXEC)) {
+ ret = 0;
+ }
} else {
ret = 0; /* Other modes are not allowed to succeed if they don't
* match a rule, but there are rules. We've checked for
* no rule earlier in this function. */
}
}
-
+ if (ret) {
+ trace_pmp_hart_has_privs_pass_match(
+ env->mhartid, addr, size, privs, mode);
+ } else {
+ trace_pmp_hart_has_privs_violation(
+ env->mhartid, addr, size, privs, mode);
+ }
return ret == 1 ? true : false;
}
diff --git a/target/riscv/pmp.h b/target/riscv/pmp.h
index 8e19793132..7db2069204 100644
--- a/target/riscv/pmp.h
+++ b/target/riscv/pmp.h
@@ -36,6 +36,12 @@ typedef enum {
PMP_AMATCH_NAPOT /* Naturally aligned power-of-two region */
} pmp_am_t;
+typedef enum {
+ MSECCFG_MML = 1 << 0,
+ MSECCFG_MMWP = 1 << 1,
+ MSECCFG_RLB = 1 << 2
+} mseccfg_field_t;
+
typedef struct {
target_ulong addr_reg;
uint8_t cfg_reg;
@@ -58,7 +64,13 @@ target_ulong pmpcfg_csr_read(CPURISCVState *env, uint32_t reg_index);
void pmpaddr_csr_write(CPURISCVState *env, uint32_t addr_index,
target_ulong val);
target_ulong pmpaddr_csr_read(CPURISCVState *env, uint32_t addr_index);
+void mseccfg_csr_write(CPURISCVState *env, target_ulong val);
+target_ulong mseccfg_csr_read(CPURISCVState *env);
bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
target_ulong size, pmp_priv_t priv, target_ulong mode);
+#define MSECCFG_MML_ISSET(env) get_field(env->mseccfg, MSECCFG_MML)
+#define MSECCFG_MMWP_ISSET(env) get_field(env->mseccfg, MSECCFG_MMWP)
+#define MSECCFG_RLB_ISSET(env) get_field(env->mseccfg, MSECCFG_RLB)
+
#endif
diff --git a/target/riscv/trace-events b/target/riscv/trace-events
index 4b6c652ae9..4f877f90f7 100644
--- a/target/riscv/trace-events
+++ b/target/riscv/trace-events
@@ -6,3 +6,7 @@ pmpcfg_csr_read(uint64_t mhartid, uint32_t reg_index, uint64_t val) "hart %" PRI
pmpcfg_csr_write(uint64_t mhartid, uint32_t reg_index, uint64_t val) "hart %" PRIu64 ": write reg%" PRIu32", val: 0x%" PRIx64
pmpaddr_csr_read(uint64_t mhartid, uint32_t addr_index, uint64_t val) "hart %" PRIu64 ": read addr%" PRIu32", val: 0x%" PRIx64
pmpaddr_csr_write(uint64_t mhartid, uint32_t addr_index, uint64_t val) "hart %" PRIu64 ": write addr%" PRIu32", val: 0x%" PRIx64
+mseccfg_csr_read(uint64_t mhartid, uint64_t val) "hart %" PRIu64 ": read mseccfg, val: 0x%" PRIx64
+mseccfg_csr_write(uint64_t mhartid, uint64_t val) "hart %" PRIu64 ": write mseccfg, val: 0x%" PRIx64
+pmp_hart_has_privs_pass_match(uint64_t mhartid, uint64_t addr, uint64_t size, uint64_t privs, uint64_t mode) "hart %"PRId64 "pass PMP 0 match addr:%"PRIu64" size:%"PRIu64 "privs: %"PRIu64 "mode: %"PRIu64
+pmp_hart_has_privs_violation(uint64_t mhartid, uint64_t addr, uint64_t size, uint64_t privs, uint64_t mode) "hart %"PRId64 "pass PMP 0 match addr:%"PRIu64" size:%"PRIu64 "privs: %"PRIu64 "mode: %"PRIu64
--
2.20.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 3/4] Add ePMP CSR accesses
[not found] <20200808052031.19523-1-weiying_hou@outlook.com>
@ 2020-08-08 5:20 ` Hou Weiying
2020-08-08 5:20 ` Hou Weiying
` (2 subsequent siblings)
3 siblings, 0 replies; 12+ messages in thread
From: Hou Weiying @ 2020-08-08 5:20 UTC (permalink / raw
To: qemu-riscv, qemu-devel
Cc: sagark, kbastian, Hongzheng-Li, Alistair.Francis, Myriad-Dreamin,
palmer
Signed-off-by: Hongzheng-Li <Ethan.Lee.QNL@gmail.com>
Signed-off-by: Hou Weiying <weiying_hou@outlook.com>
Signed-off-by: Myriad-Dreamin <camiyoru@gmail.com>
---
target/riscv/csr.c | 18 ++++++++++++++++++
target/riscv/pmp.c | 40 ++++++++++++++++++++++++++++++++++++++++
2 files changed, 58 insertions(+)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 11d184cd16..e2395e3a51 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -112,6 +112,11 @@ static int hmode(CPURISCVState *env, int csrno)
return -1;
}
+static int epmp(CPURISCVState *env, int csrno)
+{
+ return -!(env->priv == PRV_M && riscv_feature(env, RISCV_FEATURE_EPMP));
+}
+
static int pmp(CPURISCVState *env, int csrno)
{
return -!riscv_feature(env, RISCV_FEATURE_PMP);
@@ -1160,6 +1165,18 @@ static int write_pmpaddr(CPURISCVState *env, int csrno, target_ulong val)
return 0;
}
+static int read_mseccfg(CPURISCVState *env, int csrno, target_ulong *val)
+{
+ *val = mseccfg_csr_read(env);
+ return 0;
+}
+
+static int write_mseccfg(CPURISCVState *env, int csrno, target_ulong val)
+{
+ mseccfg_csr_write(env, val);
+ return 0;
+}
+
#endif
/*
@@ -1368,6 +1385,7 @@ static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
[CSR_MTINST] = { hmode, read_mtinst, write_mtinst },
/* Physical Memory Protection */
+ [CSR_MSECCFG] = { epmp, read_mseccfg, write_mseccfg },
[CSR_PMPCFG0 ... CSR_PMPADDR9] = { pmp, read_pmpcfg, write_pmpcfg },
[CSR_PMPADDR0 ... CSR_PMPADDR15] = { pmp, read_pmpaddr, write_pmpaddr },
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index 8df389cecd..0eabaf690c 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -490,3 +490,43 @@ target_ulong pmpaddr_csr_read(CPURISCVState *env, uint32_t addr_index)
return val;
}
+
+
+/*
+ * Handle a write to a mseccfg CSR
+ */
+void mseccfg_csr_write(CPURISCVState *env, target_ulong val)
+{
+ int i;
+
+ if (!MSECCFG_RLB_ISSET(env)) {
+ for (i = 0; i < MAX_RISCV_PMPS; i++) {
+ if (pmp_is_locked(env, i)) {
+ /*
+ * Now that mseccfg.rlb is zero
+ * the value of mseccfg.rlb should be locked.
+ */
+ val &= ~MSECCFG_RLB;
+ break;
+ }
+ }
+ }
+
+ /*
+ * sticky bit
+ */
+ val |= (env->mseccfg & (MSECCFG_MMWP | MSECCFG_MML));
+
+ env->mseccfg = val;
+ trace_mseccfg_csr_write(env->mhartid, val);
+}
+
+
+/*
+ * Handle a read from a mseccfg CSR
+ */
+target_ulong mseccfg_csr_read(CPURISCVState *env)
+{
+ trace_mseccfg_csr_read(env->mhartid, env->mseccfg);
+ return env->mseccfg;
+}
--
2.20.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 3/4] Add ePMP CSR accesses
@ 2020-08-08 5:20 ` Hou Weiying
0 siblings, 0 replies; 12+ messages in thread
From: Hou Weiying @ 2020-08-08 5:20 UTC (permalink / raw
To: qemu-riscv, qemu-devel
Cc: palmer, Alistair.Francis, sagark, kbastian, Hongzheng-Li,
Myriad-Dreamin
Signed-off-by: Hongzheng-Li <Ethan.Lee.QNL@gmail.com>
Signed-off-by: Hou Weiying <weiying_hou@outlook.com>
Signed-off-by: Myriad-Dreamin <camiyoru@gmail.com>
---
target/riscv/csr.c | 18 ++++++++++++++++++
target/riscv/pmp.c | 40 ++++++++++++++++++++++++++++++++++++++++
2 files changed, 58 insertions(+)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 11d184cd16..e2395e3a51 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -112,6 +112,11 @@ static int hmode(CPURISCVState *env, int csrno)
return -1;
}
+static int epmp(CPURISCVState *env, int csrno)
+{
+ return -!(env->priv == PRV_M && riscv_feature(env, RISCV_FEATURE_EPMP));
+}
+
static int pmp(CPURISCVState *env, int csrno)
{
return -!riscv_feature(env, RISCV_FEATURE_PMP);
@@ -1160,6 +1165,18 @@ static int write_pmpaddr(CPURISCVState *env, int csrno, target_ulong val)
return 0;
}
+static int read_mseccfg(CPURISCVState *env, int csrno, target_ulong *val)
+{
+ *val = mseccfg_csr_read(env);
+ return 0;
+}
+
+static int write_mseccfg(CPURISCVState *env, int csrno, target_ulong val)
+{
+ mseccfg_csr_write(env, val);
+ return 0;
+}
+
#endif
/*
@@ -1368,6 +1385,7 @@ static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
[CSR_MTINST] = { hmode, read_mtinst, write_mtinst },
/* Physical Memory Protection */
+ [CSR_MSECCFG] = { epmp, read_mseccfg, write_mseccfg },
[CSR_PMPCFG0 ... CSR_PMPADDR9] = { pmp, read_pmpcfg, write_pmpcfg },
[CSR_PMPADDR0 ... CSR_PMPADDR15] = { pmp, read_pmpaddr, write_pmpaddr },
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index 8df389cecd..0eabaf690c 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -490,3 +490,43 @@ target_ulong pmpaddr_csr_read(CPURISCVState *env, uint32_t addr_index)
return val;
}
+
+
+/*
+ * Handle a write to a mseccfg CSR
+ */
+void mseccfg_csr_write(CPURISCVState *env, target_ulong val)
+{
+ int i;
+
+ if (!MSECCFG_RLB_ISSET(env)) {
+ for (i = 0; i < MAX_RISCV_PMPS; i++) {
+ if (pmp_is_locked(env, i)) {
+ /*
+ * Now that mseccfg.rlb is zero
+ * the value of mseccfg.rlb should be locked.
+ */
+ val &= ~MSECCFG_RLB;
+ break;
+ }
+ }
+ }
+
+ /*
+ * sticky bit
+ */
+ val |= (env->mseccfg & (MSECCFG_MMWP | MSECCFG_MML));
+
+ env->mseccfg = val;
+ trace_mseccfg_csr_write(env->mhartid, val);
+}
+
+
+/*
+ * Handle a read from a mseccfg CSR
+ */
+target_ulong mseccfg_csr_read(CPURISCVState *env)
+{
+ trace_mseccfg_csr_read(env->mhartid, env->mseccfg);
+ return env->mseccfg;
+}
--
2.20.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 4/4] Add a config option for ePMP.
[not found] <20200808052031.19523-1-weiying_hou@outlook.com>
@ 2020-08-08 5:20 ` Hou Weiying
2020-08-08 5:20 ` Hou Weiying
` (2 subsequent siblings)
3 siblings, 0 replies; 12+ messages in thread
From: Hou Weiying @ 2020-08-08 5:20 UTC (permalink / raw
To: qemu-riscv, qemu-devel
Cc: sagark, kbastian, Hongzheng-Li, Alistair.Francis, Myriad-Dreamin,
palmer
Add a config option to enable experimental support for ePMP. This
is disabled by default and can be enabled with 'x-epmp=true'.
Signed-off-by: Hongzheng-Li <Ethan.Lee.QNL@gmail.com>
Signed-off-by: Hou Weiying <weiying_hou@outlook.com>
Signed-off-by: Myriad-Dreamin <camiyoru@gmail.com>
---
target/riscv/cpu.c | 9 +++++++++
target/riscv/cpu.h | 3 +++
2 files changed, 12 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 059d71f2c7..79fa9d3c2f 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -407,6 +407,14 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
if (cpu->cfg.pmp) {
set_feature(env, RISCV_FEATURE_PMP);
+
+ /*
+ * Enhanced PMP should only be available
+ * on harts with PMP support
+ */
+ if (cpu->cfg.epmp) {
+ set_feature(env, RISCV_FEATURE_EPMP);
+ }
}
/* If misa isn't set (rv32 and rv64 machines) set it here */
@@ -509,6 +517,7 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
+ DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false),
DEFINE_PROP_END_OF_LIST(),
};
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index d0e7f5b9c5..afdc9fa2bf 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -77,6 +77,7 @@
enum {
RISCV_FEATURE_MMU,
RISCV_FEATURE_PMP,
+ RISCV_FEATURE_EPMP,
RISCV_FEATURE_MISA
};
@@ -202,6 +203,7 @@ struct CPURISCVState {
/* physical memory protection */
pmp_table_t pmp_state;
+ target_ulong mseccfg;
/* machine specific rdtime callback */
uint64_t (*rdtime_fn)(void);
@@ -272,6 +274,7 @@ typedef struct RISCVCPU {
char *user_spec;
bool mmu;
bool pmp;
+ bool epmp;
} cfg;
} RISCVCPU;
--
2.20.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 4/4] Add a config option for ePMP.
@ 2020-08-08 5:20 ` Hou Weiying
0 siblings, 0 replies; 12+ messages in thread
From: Hou Weiying @ 2020-08-08 5:20 UTC (permalink / raw
To: qemu-riscv, qemu-devel
Cc: palmer, Alistair.Francis, sagark, kbastian, Hongzheng-Li,
Myriad-Dreamin
Add a config option to enable experimental support for ePMP. This
is disabled by default and can be enabled with 'x-epmp=true'.
Signed-off-by: Hongzheng-Li <Ethan.Lee.QNL@gmail.com>
Signed-off-by: Hou Weiying <weiying_hou@outlook.com>
Signed-off-by: Myriad-Dreamin <camiyoru@gmail.com>
---
target/riscv/cpu.c | 9 +++++++++
target/riscv/cpu.h | 3 +++
2 files changed, 12 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 059d71f2c7..79fa9d3c2f 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -407,6 +407,14 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
if (cpu->cfg.pmp) {
set_feature(env, RISCV_FEATURE_PMP);
+
+ /*
+ * Enhanced PMP should only be available
+ * on harts with PMP support
+ */
+ if (cpu->cfg.epmp) {
+ set_feature(env, RISCV_FEATURE_EPMP);
+ }
}
/* If misa isn't set (rv32 and rv64 machines) set it here */
@@ -509,6 +517,7 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
+ DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false),
DEFINE_PROP_END_OF_LIST(),
};
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index d0e7f5b9c5..afdc9fa2bf 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -77,6 +77,7 @@
enum {
RISCV_FEATURE_MMU,
RISCV_FEATURE_PMP,
+ RISCV_FEATURE_EPMP,
RISCV_FEATURE_MISA
};
@@ -202,6 +203,7 @@ struct CPURISCVState {
/* physical memory protection */
pmp_table_t pmp_state;
+ target_ulong mseccfg;
/* machine specific rdtime callback */
uint64_t (*rdtime_fn)(void);
@@ -272,6 +274,7 @@ typedef struct RISCVCPU {
char *user_spec;
bool mmu;
bool pmp;
+ bool epmp;
} cfg;
} RISCVCPU;
--
2.20.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 3/4] Add ePMP CSR accesses
[not found] <20200808085656.28692-1-weiying_hou@outlook.com>
@ 2020-08-08 8:56 ` Hou Weiying
0 siblings, 0 replies; 12+ messages in thread
From: Hou Weiying @ 2020-08-08 8:56 UTC (permalink / raw
To: qemu-riscv, qemu-devel
Cc: sagark, kbastian, Hongzheng-Li, Alistair.Francis, Myriad-Dreamin,
palmer
Signed-off-by: Hongzheng-Li <Ethan.Lee.QNL@gmail.com>
Signed-off-by: Hou Weiying <weiying_hou@outlook.com>
Signed-off-by: Myriad-Dreamin <camiyoru@gmail.com>
---
target/riscv/csr.c | 18 ++++++++++++++++++
target/riscv/pmp.c | 40 ++++++++++++++++++++++++++++++++++++++++
2 files changed, 58 insertions(+)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 11d184cd16..e2395e3a51 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -112,6 +112,11 @@ static int hmode(CPURISCVState *env, int csrno)
return -1;
}
+static int epmp(CPURISCVState *env, int csrno)
+{
+ return -!(env->priv == PRV_M && riscv_feature(env, RISCV_FEATURE_EPMP));
+}
+
static int pmp(CPURISCVState *env, int csrno)
{
return -!riscv_feature(env, RISCV_FEATURE_PMP);
@@ -1160,6 +1165,18 @@ static int write_pmpaddr(CPURISCVState *env, int csrno, target_ulong val)
return 0;
}
+static int read_mseccfg(CPURISCVState *env, int csrno, target_ulong *val)
+{
+ *val = mseccfg_csr_read(env);
+ return 0;
+}
+
+static int write_mseccfg(CPURISCVState *env, int csrno, target_ulong val)
+{
+ mseccfg_csr_write(env, val);
+ return 0;
+}
+
#endif
/*
@@ -1368,6 +1385,7 @@ static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
[CSR_MTINST] = { hmode, read_mtinst, write_mtinst },
/* Physical Memory Protection */
+ [CSR_MSECCFG] = { epmp, read_mseccfg, write_mseccfg },
[CSR_PMPCFG0 ... CSR_PMPADDR9] = { pmp, read_pmpcfg, write_pmpcfg },
[CSR_PMPADDR0 ... CSR_PMPADDR15] = { pmp, read_pmpaddr, write_pmpaddr },
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index 8df389cecd..0eabaf690c 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -490,3 +490,43 @@ target_ulong pmpaddr_csr_read(CPURISCVState *env, uint32_t addr_index)
return val;
}
+
+
+/*
+ * Handle a write to a mseccfg CSR
+ */
+void mseccfg_csr_write(CPURISCVState *env, target_ulong val)
+{
+ int i;
+
+ if (!MSECCFG_RLB_ISSET(env)) {
+ for (i = 0; i < MAX_RISCV_PMPS; i++) {
+ if (pmp_is_locked(env, i)) {
+ /*
+ * Now that mseccfg.rlb is zero
+ * the value of mseccfg.rlb should be locked.
+ */
+ val &= ~MSECCFG_RLB;
+ break;
+ }
+ }
+ }
+
+ /*
+ * sticky bit
+ */
+ val |= (env->mseccfg & (MSECCFG_MMWP | MSECCFG_MML));
+
+ env->mseccfg = val;
+ trace_mseccfg_csr_write(env->mhartid, val);
+}
+
+
+/*
+ * Handle a read from a mseccfg CSR
+ */
+target_ulong mseccfg_csr_read(CPURISCVState *env)
+{
+ trace_mseccfg_csr_read(env->mhartid, env->mseccfg);
+ return env->mseccfg;
+}
--
2.20.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 3/4] Add ePMP CSR accesses
@ 2020-08-08 8:56 ` Hou Weiying
0 siblings, 0 replies; 12+ messages in thread
From: Hou Weiying @ 2020-08-08 8:56 UTC (permalink / raw
To: qemu-riscv, qemu-devel
Cc: palmer, Alistair.Francis, sagark, kbastian, Hongzheng-Li,
Myriad-Dreamin
Signed-off-by: Hongzheng-Li <Ethan.Lee.QNL@gmail.com>
Signed-off-by: Hou Weiying <weiying_hou@outlook.com>
Signed-off-by: Myriad-Dreamin <camiyoru@gmail.com>
---
target/riscv/csr.c | 18 ++++++++++++++++++
target/riscv/pmp.c | 40 ++++++++++++++++++++++++++++++++++++++++
2 files changed, 58 insertions(+)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 11d184cd16..e2395e3a51 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -112,6 +112,11 @@ static int hmode(CPURISCVState *env, int csrno)
return -1;
}
+static int epmp(CPURISCVState *env, int csrno)
+{
+ return -!(env->priv == PRV_M && riscv_feature(env, RISCV_FEATURE_EPMP));
+}
+
static int pmp(CPURISCVState *env, int csrno)
{
return -!riscv_feature(env, RISCV_FEATURE_PMP);
@@ -1160,6 +1165,18 @@ static int write_pmpaddr(CPURISCVState *env, int csrno, target_ulong val)
return 0;
}
+static int read_mseccfg(CPURISCVState *env, int csrno, target_ulong *val)
+{
+ *val = mseccfg_csr_read(env);
+ return 0;
+}
+
+static int write_mseccfg(CPURISCVState *env, int csrno, target_ulong val)
+{
+ mseccfg_csr_write(env, val);
+ return 0;
+}
+
#endif
/*
@@ -1368,6 +1385,7 @@ static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
[CSR_MTINST] = { hmode, read_mtinst, write_mtinst },
/* Physical Memory Protection */
+ [CSR_MSECCFG] = { epmp, read_mseccfg, write_mseccfg },
[CSR_PMPCFG0 ... CSR_PMPADDR9] = { pmp, read_pmpcfg, write_pmpcfg },
[CSR_PMPADDR0 ... CSR_PMPADDR15] = { pmp, read_pmpaddr, write_pmpaddr },
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index 8df389cecd..0eabaf690c 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -490,3 +490,43 @@ target_ulong pmpaddr_csr_read(CPURISCVState *env, uint32_t addr_index)
return val;
}
+
+
+/*
+ * Handle a write to a mseccfg CSR
+ */
+void mseccfg_csr_write(CPURISCVState *env, target_ulong val)
+{
+ int i;
+
+ if (!MSECCFG_RLB_ISSET(env)) {
+ for (i = 0; i < MAX_RISCV_PMPS; i++) {
+ if (pmp_is_locked(env, i)) {
+ /*
+ * Now that mseccfg.rlb is zero
+ * the value of mseccfg.rlb should be locked.
+ */
+ val &= ~MSECCFG_RLB;
+ break;
+ }
+ }
+ }
+
+ /*
+ * sticky bit
+ */
+ val |= (env->mseccfg & (MSECCFG_MMWP | MSECCFG_MML));
+
+ env->mseccfg = val;
+ trace_mseccfg_csr_write(env->mhartid, val);
+}
+
+
+/*
+ * Handle a read from a mseccfg CSR
+ */
+target_ulong mseccfg_csr_read(CPURISCVState *env)
+{
+ trace_mseccfg_csr_read(env->mhartid, env->mseccfg);
+ return env->mseccfg;
+}
--
2.20.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 3/4] Add ePMP CSR accesses
2020-08-08 9:09 [PATCH 0/4] riscv: Add enhanced PMP support Hongzheng-Li
@ 2020-08-08 9:09 ` Hongzheng-Li
0 siblings, 0 replies; 12+ messages in thread
From: Hongzheng-Li @ 2020-08-08 9:09 UTC (permalink / raw
To: qemu-riscv, qemu-devel
Cc: Hou Weiying, sagark, kbastian, Hongzheng-Li, Alistair.Francis,
palmer, Myriad-Dreamin
From: Hou Weiying <weiying_hou@outlook.com>
Signed-off-by: Hongzheng-Li <Ethan.Lee.QNL@gmail.com>
Signed-off-by: Hou Weiying <weiying_hou@outlook.com>
Signed-off-by: Myriad-Dreamin <camiyoru@gmail.com>
---
target/riscv/csr.c | 18 ++++++++++++++++++
target/riscv/pmp.c | 40 ++++++++++++++++++++++++++++++++++++++++
2 files changed, 58 insertions(+)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 11d184cd16..e2395e3a51 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -112,6 +112,11 @@ static int hmode(CPURISCVState *env, int csrno)
return -1;
}
+static int epmp(CPURISCVState *env, int csrno)
+{
+ return -!(env->priv == PRV_M && riscv_feature(env, RISCV_FEATURE_EPMP));
+}
+
static int pmp(CPURISCVState *env, int csrno)
{
return -!riscv_feature(env, RISCV_FEATURE_PMP);
@@ -1160,6 +1165,18 @@ static int write_pmpaddr(CPURISCVState *env, int csrno, target_ulong val)
return 0;
}
+static int read_mseccfg(CPURISCVState *env, int csrno, target_ulong *val)
+{
+ *val = mseccfg_csr_read(env);
+ return 0;
+}
+
+static int write_mseccfg(CPURISCVState *env, int csrno, target_ulong val)
+{
+ mseccfg_csr_write(env, val);
+ return 0;
+}
+
#endif
/*
@@ -1368,6 +1385,7 @@ static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
[CSR_MTINST] = { hmode, read_mtinst, write_mtinst },
/* Physical Memory Protection */
+ [CSR_MSECCFG] = { epmp, read_mseccfg, write_mseccfg },
[CSR_PMPCFG0 ... CSR_PMPADDR9] = { pmp, read_pmpcfg, write_pmpcfg },
[CSR_PMPADDR0 ... CSR_PMPADDR15] = { pmp, read_pmpaddr, write_pmpaddr },
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index 8df389cecd..0eabaf690c 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -490,3 +490,43 @@ target_ulong pmpaddr_csr_read(CPURISCVState *env, uint32_t addr_index)
return val;
}
+
+
+/*
+ * Handle a write to a mseccfg CSR
+ */
+void mseccfg_csr_write(CPURISCVState *env, target_ulong val)
+{
+ int i;
+
+ if (!MSECCFG_RLB_ISSET(env)) {
+ for (i = 0; i < MAX_RISCV_PMPS; i++) {
+ if (pmp_is_locked(env, i)) {
+ /*
+ * Now that mseccfg.rlb is zero
+ * the value of mseccfg.rlb should be locked.
+ */
+ val &= ~MSECCFG_RLB;
+ break;
+ }
+ }
+ }
+
+ /*
+ * sticky bit
+ */
+ val |= (env->mseccfg & (MSECCFG_MMWP | MSECCFG_MML));
+
+ env->mseccfg = val;
+ trace_mseccfg_csr_write(env->mhartid, val);
+}
+
+
+/*
+ * Handle a read from a mseccfg CSR
+ */
+target_ulong mseccfg_csr_read(CPURISCVState *env)
+{
+ trace_mseccfg_csr_read(env->mhartid, env->mseccfg);
+ return env->mseccfg;
+}
--
2.20.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 3/4] Add ePMP CSR accesses
@ 2020-08-08 9:09 ` Hongzheng-Li
0 siblings, 0 replies; 12+ messages in thread
From: Hongzheng-Li @ 2020-08-08 9:09 UTC (permalink / raw
To: qemu-riscv, qemu-devel
Cc: palmer, Alistair.Francis, sagark, kbastian, Hou Weiying,
Hongzheng-Li, Myriad-Dreamin
From: Hou Weiying <weiying_hou@outlook.com>
Signed-off-by: Hongzheng-Li <Ethan.Lee.QNL@gmail.com>
Signed-off-by: Hou Weiying <weiying_hou@outlook.com>
Signed-off-by: Myriad-Dreamin <camiyoru@gmail.com>
---
target/riscv/csr.c | 18 ++++++++++++++++++
target/riscv/pmp.c | 40 ++++++++++++++++++++++++++++++++++++++++
2 files changed, 58 insertions(+)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 11d184cd16..e2395e3a51 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -112,6 +112,11 @@ static int hmode(CPURISCVState *env, int csrno)
return -1;
}
+static int epmp(CPURISCVState *env, int csrno)
+{
+ return -!(env->priv == PRV_M && riscv_feature(env, RISCV_FEATURE_EPMP));
+}
+
static int pmp(CPURISCVState *env, int csrno)
{
return -!riscv_feature(env, RISCV_FEATURE_PMP);
@@ -1160,6 +1165,18 @@ static int write_pmpaddr(CPURISCVState *env, int csrno, target_ulong val)
return 0;
}
+static int read_mseccfg(CPURISCVState *env, int csrno, target_ulong *val)
+{
+ *val = mseccfg_csr_read(env);
+ return 0;
+}
+
+static int write_mseccfg(CPURISCVState *env, int csrno, target_ulong val)
+{
+ mseccfg_csr_write(env, val);
+ return 0;
+}
+
#endif
/*
@@ -1368,6 +1385,7 @@ static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
[CSR_MTINST] = { hmode, read_mtinst, write_mtinst },
/* Physical Memory Protection */
+ [CSR_MSECCFG] = { epmp, read_mseccfg, write_mseccfg },
[CSR_PMPCFG0 ... CSR_PMPADDR9] = { pmp, read_pmpcfg, write_pmpcfg },
[CSR_PMPADDR0 ... CSR_PMPADDR15] = { pmp, read_pmpaddr, write_pmpaddr },
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index 8df389cecd..0eabaf690c 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -490,3 +490,43 @@ target_ulong pmpaddr_csr_read(CPURISCVState *env, uint32_t addr_index)
return val;
}
+
+
+/*
+ * Handle a write to a mseccfg CSR
+ */
+void mseccfg_csr_write(CPURISCVState *env, target_ulong val)
+{
+ int i;
+
+ if (!MSECCFG_RLB_ISSET(env)) {
+ for (i = 0; i < MAX_RISCV_PMPS; i++) {
+ if (pmp_is_locked(env, i)) {
+ /*
+ * Now that mseccfg.rlb is zero
+ * the value of mseccfg.rlb should be locked.
+ */
+ val &= ~MSECCFG_RLB;
+ break;
+ }
+ }
+ }
+
+ /*
+ * sticky bit
+ */
+ val |= (env->mseccfg & (MSECCFG_MMWP | MSECCFG_MML));
+
+ env->mseccfg = val;
+ trace_mseccfg_csr_write(env->mhartid, val);
+}
+
+
+/*
+ * Handle a read from a mseccfg CSR
+ */
+target_ulong mseccfg_csr_read(CPURISCVState *env)
+{
+ trace_mseccfg_csr_read(env->mhartid, env->mseccfg);
+ return env->mseccfg;
+}
--
2.20.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
end of thread, other threads:[~2020-08-08 13:04 UTC | newest]
Thread overview: 12+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
[not found] <20200808052031.19523-1-weiying_hou@outlook.com>
2020-08-08 5:20 ` [PATCH 1/4] Define ePMP mseccfg Hou Weiying
2020-08-08 5:20 ` Hou Weiying
2020-08-08 5:20 ` [PATCH 2/4] Implementation of enhanced PMP(ePMP) support Hou Weiying
2020-08-08 5:20 ` Hou Weiying
2020-08-08 5:20 ` [PATCH 3/4] Add ePMP CSR accesses Hou Weiying
2020-08-08 5:20 ` Hou Weiying
2020-08-08 5:20 ` [PATCH 4/4] Add a config option for ePMP Hou Weiying
2020-08-08 5:20 ` Hou Weiying
[not found] <20200808085656.28692-1-weiying_hou@outlook.com>
2020-08-08 8:56 ` [PATCH 3/4] Add ePMP CSR accesses Hou Weiying
2020-08-08 8:56 ` Hou Weiying
2020-08-08 9:09 [PATCH 0/4] riscv: Add enhanced PMP support Hongzheng-Li
2020-08-08 9:09 ` [PATCH 3/4] Add ePMP CSR accesses Hongzheng-Li
2020-08-08 9:09 ` Hongzheng-Li
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