* [PATCH v1 -next 0/3] RISC-V: ACPI: Enable CPPC based cpufreq support
@ 2024-02-08 3:44 ` Sunil V L
0 siblings, 0 replies; 32+ messages in thread
From: Sunil V L @ 2024-02-08 3:44 UTC (permalink / raw
To: linux-riscv, linux-acpi, linux-kernel
Cc: Anup Patel, Albert Ou, Rafael J . Wysocki, Viresh Kumar,
Atish Kumar Patra, Conor Dooley, Palmer Dabbelt, Paul Walmsley,
Andrew Jones, Len Brown
This series enables the support for "Collaborative Processor Performance
Control (CPPC) on ACPI based RISC-V platforms. It depends on the
encoding of CPPC registers as defined in RISC-V FFH spec [2].
CPPC is described in the ACPI spec [1]. RISC-V FFH spec required to
enable this, is available at [2].
[1] - https://uefi.org/specs/ACPI/6.5/08_Processor_Configuration_and_Control.html#collaborative-processor-performance-control
[2] - https://github.com/riscv-non-isa/riscv-acpi-ffh/releases/download/v1.0.0/riscv-ffh.pdf
The series is based on the LPI support series.
Based-on: 20240118062930.245937-1-sunilvl@ventanamicro.com
(https://lore.kernel.org/lkml/20240118062930.245937-1-sunilvl@ventanamicro.com/)
Sunil V L (3):
ACPI: RISC-V: Add CPPC driver
cpufreq: Move CPPC configs to common Kconfig and add RISC-V
RISC-V: defconfig: Enable CONFIG_ACPI_CPPC_CPUFREQ
arch/riscv/configs/defconfig | 1 +
drivers/acpi/riscv/Makefile | 1 +
drivers/acpi/riscv/cppc.c | 157 +++++++++++++++++++++++++++++++++++
drivers/cpufreq/Kconfig | 29 +++++++
drivers/cpufreq/Kconfig.arm | 26 ------
5 files changed, 188 insertions(+), 26 deletions(-)
create mode 100644 drivers/acpi/riscv/cppc.c
--
2.34.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH v1 -next 0/3] RISC-V: ACPI: Enable CPPC based cpufreq support
@ 2024-02-08 3:44 ` Sunil V L
0 siblings, 0 replies; 32+ messages in thread
From: Sunil V L @ 2024-02-08 3:44 UTC (permalink / raw
To: linux-riscv, linux-acpi, linux-kernel
Cc: Rafael J . Wysocki, Len Brown, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Viresh Kumar, Conor Dooley, Andrew Jones,
Atish Kumar Patra, Anup Patel, Sunil V L
This series enables the support for "Collaborative Processor Performance
Control (CPPC) on ACPI based RISC-V platforms. It depends on the
encoding of CPPC registers as defined in RISC-V FFH spec [2].
CPPC is described in the ACPI spec [1]. RISC-V FFH spec required to
enable this, is available at [2].
[1] - https://uefi.org/specs/ACPI/6.5/08_Processor_Configuration_and_Control.html#collaborative-processor-performance-control
[2] - https://github.com/riscv-non-isa/riscv-acpi-ffh/releases/download/v1.0.0/riscv-ffh.pdf
The series is based on the LPI support series.
Based-on: 20240118062930.245937-1-sunilvl@ventanamicro.com
(https://lore.kernel.org/lkml/20240118062930.245937-1-sunilvl@ventanamicro.com/)
Sunil V L (3):
ACPI: RISC-V: Add CPPC driver
cpufreq: Move CPPC configs to common Kconfig and add RISC-V
RISC-V: defconfig: Enable CONFIG_ACPI_CPPC_CPUFREQ
arch/riscv/configs/defconfig | 1 +
drivers/acpi/riscv/Makefile | 1 +
drivers/acpi/riscv/cppc.c | 157 +++++++++++++++++++++++++++++++++++
drivers/cpufreq/Kconfig | 29 +++++++
drivers/cpufreq/Kconfig.arm | 26 ------
5 files changed, 188 insertions(+), 26 deletions(-)
create mode 100644 drivers/acpi/riscv/cppc.c
--
2.34.1
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH v1 -next 1/3] ACPI: RISC-V: Add CPPC driver
2024-02-08 3:44 ` Sunil V L
@ 2024-02-08 3:44 ` Sunil V L
-1 siblings, 0 replies; 32+ messages in thread
From: Sunil V L @ 2024-02-08 3:44 UTC (permalink / raw
To: linux-riscv, linux-acpi, linux-kernel
Cc: Anup Patel, Albert Ou, Rafael J . Wysocki, Viresh Kumar,
Atish Kumar Patra, Conor Dooley, Palmer Dabbelt, Paul Walmsley,
Andrew Jones, Len Brown
Add cpufreq driver based on ACPI CPPC for RISC-V. The driver uses either
SBI CPPC interfaces or the CSRs to access the CPPC registers as defined
by the RISC-V FFH spec.
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
---
drivers/acpi/riscv/Makefile | 1 +
drivers/acpi/riscv/cppc.c | 157 ++++++++++++++++++++++++++++++++++++
2 files changed, 158 insertions(+)
create mode 100644 drivers/acpi/riscv/cppc.c
diff --git a/drivers/acpi/riscv/Makefile b/drivers/acpi/riscv/Makefile
index 7309d92dd477..86b0925f612d 100644
--- a/drivers/acpi/riscv/Makefile
+++ b/drivers/acpi/riscv/Makefile
@@ -1,3 +1,4 @@
# SPDX-License-Identifier: GPL-2.0-only
obj-y += rhct.o
obj-$(CONFIG_ACPI_PROCESSOR_IDLE) += cpuidle.o
+obj-$(CONFIG_ACPI_CPPC_LIB) += cppc.o
diff --git a/drivers/acpi/riscv/cppc.c b/drivers/acpi/riscv/cppc.c
new file mode 100644
index 000000000000..4cdff387deff
--- /dev/null
+++ b/drivers/acpi/riscv/cppc.c
@@ -0,0 +1,157 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Implement CPPC FFH helper routines for RISC-V.
+ *
+ * Copyright (C) 2024 Ventana Micro Systems Inc.
+ */
+
+#include <acpi/cppc_acpi.h>
+#include <asm/csr.h>
+#include <asm/sbi.h>
+
+#define SBI_EXT_CPPC 0x43505043
+
+/* CPPC interfaces defined in SBI spec */
+#define SBI_CPPC_PROBE 0x0
+#define SBI_CPPC_READ 0x1
+#define SBI_CPPC_READ_HI 0x2
+#define SBI_CPPC_WRITE 0x3
+
+/* RISC-V FFH definitions from RISC-V FFH spec */
+#define FFH_CPPC_TYPE(r) (((r) & GENMASK_ULL(63, 60)) >> 60)
+#define FFH_CPPC_SBI_REG(r) ((r) & GENMASK(31, 0))
+#define FFH_CPPC_CSR_NUM(r) ((r) & GENMASK(11, 0))
+
+#define FFH_CPPC_SBI 0x1
+#define FFH_CPPC_CSR 0x2
+
+struct sbi_cppc_data {
+ u64 val;
+ u32 reg;
+ struct sbiret ret;
+};
+
+static bool cppc_ext_present;
+
+static int __init sbi_cppc_init(void)
+{
+ if (sbi_spec_version >= sbi_mk_version(2, 0) &&
+ sbi_probe_extension(SBI_EXT_CPPC) > 0) {
+ pr_info("SBI CPPC extension detected\n");
+ cppc_ext_present = true;
+ } else {
+ pr_info("SBI CPPC extension NOT detected!!\n");
+ cppc_ext_present = false;
+ }
+
+ return 0;
+}
+device_initcall(sbi_cppc_init);
+
+static void sbi_cppc_read(void *read_data)
+{
+ struct sbi_cppc_data *data = (struct sbi_cppc_data *)read_data;
+
+ data->ret = sbi_ecall(SBI_EXT_CPPC, SBI_CPPC_READ,
+ data->reg, 0, 0, 0, 0, 0);
+}
+
+static void sbi_cppc_write(void *write_data)
+{
+ struct sbi_cppc_data *data = (struct sbi_cppc_data *)write_data;
+
+ data->ret = sbi_ecall(SBI_EXT_CPPC, SBI_CPPC_WRITE,
+ data->reg, data->val, 0, 0, 0, 0);
+}
+
+static void cppc_ffh_csr_read(void *read_data)
+{
+ struct sbi_cppc_data *data = (struct sbi_cppc_data *)read_data;
+
+ switch (data->reg) {
+ /* Support only TIME CSR for now */
+ case CSR_TIME:
+ data->ret.value = csr_read(CSR_TIME);
+ data->ret.error = 0;
+ break;
+ default:
+ data->ret.error = -EINVAL;
+ break;
+ }
+}
+
+static void cppc_ffh_csr_write(void *write_data)
+{
+ struct sbi_cppc_data *data = (struct sbi_cppc_data *)write_data;
+
+ data->ret.error = -EINVAL;
+}
+
+/*
+ * Refer to drivers/acpi/cppc_acpi.c for the description of the functions
+ * below.
+ */
+bool cpc_ffh_supported(void)
+{
+ return true;
+}
+
+int cpc_read_ffh(int cpu, struct cpc_reg *reg, u64 *val)
+{
+ struct sbi_cppc_data data;
+
+ if (WARN_ON_ONCE(irqs_disabled()))
+ return -EPERM;
+
+ if (FFH_CPPC_TYPE(reg->address) == FFH_CPPC_SBI) {
+ if (!cppc_ext_present)
+ return -EINVAL;
+
+ data.reg = FFH_CPPC_SBI_REG(reg->address);
+
+ smp_call_function_single(cpu, sbi_cppc_read, &data, 1);
+
+ *val = data.ret.value;
+
+ return (data.ret.error) ? sbi_err_map_linux_errno(data.ret.error) : 0;
+ } else if (FFH_CPPC_TYPE(reg->address) == FFH_CPPC_CSR) {
+ data.reg = FFH_CPPC_CSR_NUM(reg->address);
+
+ smp_call_function_single(cpu, cppc_ffh_csr_read, &data, 1);
+
+ *val = data.ret.value;
+
+ return (data.ret.error) ? sbi_err_map_linux_errno(data.ret.error) : 0;
+ }
+
+ return -EINVAL;
+}
+
+int cpc_write_ffh(int cpu, struct cpc_reg *reg, u64 val)
+{
+ struct sbi_cppc_data data;
+
+ if (WARN_ON_ONCE(irqs_disabled()))
+ return -EPERM;
+
+ if (FFH_CPPC_TYPE(reg->address) == FFH_CPPC_SBI) {
+ if (!cppc_ext_present)
+ return -EINVAL;
+
+ data.reg = FFH_CPPC_SBI_REG(reg->address);
+ data.val = val;
+
+ smp_call_function_single(cpu, sbi_cppc_write, &data, 1);
+
+ return (data.ret.error) ? sbi_err_map_linux_errno(data.ret.error) : 0;
+ } else if (FFH_CPPC_TYPE(reg->address) == FFH_CPPC_CSR) {
+ data.reg = FFH_CPPC_CSR_NUM(reg->address);
+ data.val = val;
+
+ smp_call_function_single(cpu, cppc_ffh_csr_write, &data, 1);
+
+ return (data.ret.error) ? sbi_err_map_linux_errno(data.ret.error) : 0;
+ }
+
+ return -EINVAL;
+}
--
2.34.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH v1 -next 1/3] ACPI: RISC-V: Add CPPC driver
@ 2024-02-08 3:44 ` Sunil V L
0 siblings, 0 replies; 32+ messages in thread
From: Sunil V L @ 2024-02-08 3:44 UTC (permalink / raw
To: linux-riscv, linux-acpi, linux-kernel
Cc: Rafael J . Wysocki, Len Brown, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Viresh Kumar, Conor Dooley, Andrew Jones,
Atish Kumar Patra, Anup Patel, Sunil V L
Add cpufreq driver based on ACPI CPPC for RISC-V. The driver uses either
SBI CPPC interfaces or the CSRs to access the CPPC registers as defined
by the RISC-V FFH spec.
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
---
drivers/acpi/riscv/Makefile | 1 +
drivers/acpi/riscv/cppc.c | 157 ++++++++++++++++++++++++++++++++++++
2 files changed, 158 insertions(+)
create mode 100644 drivers/acpi/riscv/cppc.c
diff --git a/drivers/acpi/riscv/Makefile b/drivers/acpi/riscv/Makefile
index 7309d92dd477..86b0925f612d 100644
--- a/drivers/acpi/riscv/Makefile
+++ b/drivers/acpi/riscv/Makefile
@@ -1,3 +1,4 @@
# SPDX-License-Identifier: GPL-2.0-only
obj-y += rhct.o
obj-$(CONFIG_ACPI_PROCESSOR_IDLE) += cpuidle.o
+obj-$(CONFIG_ACPI_CPPC_LIB) += cppc.o
diff --git a/drivers/acpi/riscv/cppc.c b/drivers/acpi/riscv/cppc.c
new file mode 100644
index 000000000000..4cdff387deff
--- /dev/null
+++ b/drivers/acpi/riscv/cppc.c
@@ -0,0 +1,157 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Implement CPPC FFH helper routines for RISC-V.
+ *
+ * Copyright (C) 2024 Ventana Micro Systems Inc.
+ */
+
+#include <acpi/cppc_acpi.h>
+#include <asm/csr.h>
+#include <asm/sbi.h>
+
+#define SBI_EXT_CPPC 0x43505043
+
+/* CPPC interfaces defined in SBI spec */
+#define SBI_CPPC_PROBE 0x0
+#define SBI_CPPC_READ 0x1
+#define SBI_CPPC_READ_HI 0x2
+#define SBI_CPPC_WRITE 0x3
+
+/* RISC-V FFH definitions from RISC-V FFH spec */
+#define FFH_CPPC_TYPE(r) (((r) & GENMASK_ULL(63, 60)) >> 60)
+#define FFH_CPPC_SBI_REG(r) ((r) & GENMASK(31, 0))
+#define FFH_CPPC_CSR_NUM(r) ((r) & GENMASK(11, 0))
+
+#define FFH_CPPC_SBI 0x1
+#define FFH_CPPC_CSR 0x2
+
+struct sbi_cppc_data {
+ u64 val;
+ u32 reg;
+ struct sbiret ret;
+};
+
+static bool cppc_ext_present;
+
+static int __init sbi_cppc_init(void)
+{
+ if (sbi_spec_version >= sbi_mk_version(2, 0) &&
+ sbi_probe_extension(SBI_EXT_CPPC) > 0) {
+ pr_info("SBI CPPC extension detected\n");
+ cppc_ext_present = true;
+ } else {
+ pr_info("SBI CPPC extension NOT detected!!\n");
+ cppc_ext_present = false;
+ }
+
+ return 0;
+}
+device_initcall(sbi_cppc_init);
+
+static void sbi_cppc_read(void *read_data)
+{
+ struct sbi_cppc_data *data = (struct sbi_cppc_data *)read_data;
+
+ data->ret = sbi_ecall(SBI_EXT_CPPC, SBI_CPPC_READ,
+ data->reg, 0, 0, 0, 0, 0);
+}
+
+static void sbi_cppc_write(void *write_data)
+{
+ struct sbi_cppc_data *data = (struct sbi_cppc_data *)write_data;
+
+ data->ret = sbi_ecall(SBI_EXT_CPPC, SBI_CPPC_WRITE,
+ data->reg, data->val, 0, 0, 0, 0);
+}
+
+static void cppc_ffh_csr_read(void *read_data)
+{
+ struct sbi_cppc_data *data = (struct sbi_cppc_data *)read_data;
+
+ switch (data->reg) {
+ /* Support only TIME CSR for now */
+ case CSR_TIME:
+ data->ret.value = csr_read(CSR_TIME);
+ data->ret.error = 0;
+ break;
+ default:
+ data->ret.error = -EINVAL;
+ break;
+ }
+}
+
+static void cppc_ffh_csr_write(void *write_data)
+{
+ struct sbi_cppc_data *data = (struct sbi_cppc_data *)write_data;
+
+ data->ret.error = -EINVAL;
+}
+
+/*
+ * Refer to drivers/acpi/cppc_acpi.c for the description of the functions
+ * below.
+ */
+bool cpc_ffh_supported(void)
+{
+ return true;
+}
+
+int cpc_read_ffh(int cpu, struct cpc_reg *reg, u64 *val)
+{
+ struct sbi_cppc_data data;
+
+ if (WARN_ON_ONCE(irqs_disabled()))
+ return -EPERM;
+
+ if (FFH_CPPC_TYPE(reg->address) == FFH_CPPC_SBI) {
+ if (!cppc_ext_present)
+ return -EINVAL;
+
+ data.reg = FFH_CPPC_SBI_REG(reg->address);
+
+ smp_call_function_single(cpu, sbi_cppc_read, &data, 1);
+
+ *val = data.ret.value;
+
+ return (data.ret.error) ? sbi_err_map_linux_errno(data.ret.error) : 0;
+ } else if (FFH_CPPC_TYPE(reg->address) == FFH_CPPC_CSR) {
+ data.reg = FFH_CPPC_CSR_NUM(reg->address);
+
+ smp_call_function_single(cpu, cppc_ffh_csr_read, &data, 1);
+
+ *val = data.ret.value;
+
+ return (data.ret.error) ? sbi_err_map_linux_errno(data.ret.error) : 0;
+ }
+
+ return -EINVAL;
+}
+
+int cpc_write_ffh(int cpu, struct cpc_reg *reg, u64 val)
+{
+ struct sbi_cppc_data data;
+
+ if (WARN_ON_ONCE(irqs_disabled()))
+ return -EPERM;
+
+ if (FFH_CPPC_TYPE(reg->address) == FFH_CPPC_SBI) {
+ if (!cppc_ext_present)
+ return -EINVAL;
+
+ data.reg = FFH_CPPC_SBI_REG(reg->address);
+ data.val = val;
+
+ smp_call_function_single(cpu, sbi_cppc_write, &data, 1);
+
+ return (data.ret.error) ? sbi_err_map_linux_errno(data.ret.error) : 0;
+ } else if (FFH_CPPC_TYPE(reg->address) == FFH_CPPC_CSR) {
+ data.reg = FFH_CPPC_CSR_NUM(reg->address);
+ data.val = val;
+
+ smp_call_function_single(cpu, cppc_ffh_csr_write, &data, 1);
+
+ return (data.ret.error) ? sbi_err_map_linux_errno(data.ret.error) : 0;
+ }
+
+ return -EINVAL;
+}
--
2.34.1
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH v1 -next 2/3] cpufreq: Move CPPC configs to common Kconfig and add RISC-V
2024-02-08 3:44 ` Sunil V L
@ 2024-02-08 3:44 ` Sunil V L
-1 siblings, 0 replies; 32+ messages in thread
From: Sunil V L @ 2024-02-08 3:44 UTC (permalink / raw
To: linux-riscv, linux-acpi, linux-kernel
Cc: Anup Patel, Albert Ou, Rafael J . Wysocki, Viresh Kumar,
Atish Kumar Patra, Conor Dooley, Palmer Dabbelt, Paul Walmsley,
Andrew Jones, Len Brown
CPPC related config options are currently defined only in ARM specific
file. However, they are required for RISC-V as well. Instead of creating
a new Kconfig.riscv file and duplicating them, move them to the common
Kconfig file and enable RISC-V too.
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
---
drivers/cpufreq/Kconfig | 29 +++++++++++++++++++++++++++++
drivers/cpufreq/Kconfig.arm | 26 --------------------------
2 files changed, 29 insertions(+), 26 deletions(-)
diff --git a/drivers/cpufreq/Kconfig b/drivers/cpufreq/Kconfig
index 35efb53d5492..94e55c40970a 100644
--- a/drivers/cpufreq/Kconfig
+++ b/drivers/cpufreq/Kconfig
@@ -302,4 +302,33 @@ config QORIQ_CPUFREQ
which are capable of changing the CPU's frequency dynamically.
endif
+
+config ACPI_CPPC_CPUFREQ
+ tristate "CPUFreq driver based on the ACPI CPPC spec"
+ depends on ACPI_PROCESSOR
+ depends on ARM || ARM64 || RISCV
+ select ACPI_CPPC_LIB
+ help
+ This adds a CPUFreq driver which uses CPPC methods
+ as described in the ACPIv5.1 spec. CPPC stands for
+ Collaborative Processor Performance Controls. It
+ is based on an abstract continuous scale of CPU
+ performance values which allows the remote power
+ processor to flexibly optimize for power and
+ performance. CPPC relies on power management firmware
+ support for its operation.
+
+ If in doubt, say N.
+
+config ACPI_CPPC_CPUFREQ_FIE
+ bool "Frequency Invariance support for CPPC cpufreq driver"
+ depends on ACPI_CPPC_CPUFREQ && GENERIC_ARCH_TOPOLOGY
+ depends on ARM || ARM64 || RISCV
+ default y
+ help
+ This extends frequency invariance support in the CPPC cpufreq driver,
+ by using CPPC delivered and reference performance counters.
+
+ If in doubt, say N.
+
endmenu
diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm
index f911606897b8..987b3d900a89 100644
--- a/drivers/cpufreq/Kconfig.arm
+++ b/drivers/cpufreq/Kconfig.arm
@@ -3,32 +3,6 @@
# ARM CPU Frequency scaling drivers
#
-config ACPI_CPPC_CPUFREQ
- tristate "CPUFreq driver based on the ACPI CPPC spec"
- depends on ACPI_PROCESSOR
- select ACPI_CPPC_LIB
- help
- This adds a CPUFreq driver which uses CPPC methods
- as described in the ACPIv5.1 spec. CPPC stands for
- Collaborative Processor Performance Controls. It
- is based on an abstract continuous scale of CPU
- performance values which allows the remote power
- processor to flexibly optimize for power and
- performance. CPPC relies on power management firmware
- support for its operation.
-
- If in doubt, say N.
-
-config ACPI_CPPC_CPUFREQ_FIE
- bool "Frequency Invariance support for CPPC cpufreq driver"
- depends on ACPI_CPPC_CPUFREQ && GENERIC_ARCH_TOPOLOGY
- default y
- help
- This extends frequency invariance support in the CPPC cpufreq driver,
- by using CPPC delivered and reference performance counters.
-
- If in doubt, say N.
-
config ARM_ALLWINNER_SUN50I_CPUFREQ_NVMEM
tristate "Allwinner nvmem based SUN50I CPUFreq driver"
depends on ARCH_SUNXI
--
2.34.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH v1 -next 2/3] cpufreq: Move CPPC configs to common Kconfig and add RISC-V
@ 2024-02-08 3:44 ` Sunil V L
0 siblings, 0 replies; 32+ messages in thread
From: Sunil V L @ 2024-02-08 3:44 UTC (permalink / raw
To: linux-riscv, linux-acpi, linux-kernel
Cc: Rafael J . Wysocki, Len Brown, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Viresh Kumar, Conor Dooley, Andrew Jones,
Atish Kumar Patra, Anup Patel, Sunil V L
CPPC related config options are currently defined only in ARM specific
file. However, they are required for RISC-V as well. Instead of creating
a new Kconfig.riscv file and duplicating them, move them to the common
Kconfig file and enable RISC-V too.
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
---
drivers/cpufreq/Kconfig | 29 +++++++++++++++++++++++++++++
drivers/cpufreq/Kconfig.arm | 26 --------------------------
2 files changed, 29 insertions(+), 26 deletions(-)
diff --git a/drivers/cpufreq/Kconfig b/drivers/cpufreq/Kconfig
index 35efb53d5492..94e55c40970a 100644
--- a/drivers/cpufreq/Kconfig
+++ b/drivers/cpufreq/Kconfig
@@ -302,4 +302,33 @@ config QORIQ_CPUFREQ
which are capable of changing the CPU's frequency dynamically.
endif
+
+config ACPI_CPPC_CPUFREQ
+ tristate "CPUFreq driver based on the ACPI CPPC spec"
+ depends on ACPI_PROCESSOR
+ depends on ARM || ARM64 || RISCV
+ select ACPI_CPPC_LIB
+ help
+ This adds a CPUFreq driver which uses CPPC methods
+ as described in the ACPIv5.1 spec. CPPC stands for
+ Collaborative Processor Performance Controls. It
+ is based on an abstract continuous scale of CPU
+ performance values which allows the remote power
+ processor to flexibly optimize for power and
+ performance. CPPC relies on power management firmware
+ support for its operation.
+
+ If in doubt, say N.
+
+config ACPI_CPPC_CPUFREQ_FIE
+ bool "Frequency Invariance support for CPPC cpufreq driver"
+ depends on ACPI_CPPC_CPUFREQ && GENERIC_ARCH_TOPOLOGY
+ depends on ARM || ARM64 || RISCV
+ default y
+ help
+ This extends frequency invariance support in the CPPC cpufreq driver,
+ by using CPPC delivered and reference performance counters.
+
+ If in doubt, say N.
+
endmenu
diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm
index f911606897b8..987b3d900a89 100644
--- a/drivers/cpufreq/Kconfig.arm
+++ b/drivers/cpufreq/Kconfig.arm
@@ -3,32 +3,6 @@
# ARM CPU Frequency scaling drivers
#
-config ACPI_CPPC_CPUFREQ
- tristate "CPUFreq driver based on the ACPI CPPC spec"
- depends on ACPI_PROCESSOR
- select ACPI_CPPC_LIB
- help
- This adds a CPUFreq driver which uses CPPC methods
- as described in the ACPIv5.1 spec. CPPC stands for
- Collaborative Processor Performance Controls. It
- is based on an abstract continuous scale of CPU
- performance values which allows the remote power
- processor to flexibly optimize for power and
- performance. CPPC relies on power management firmware
- support for its operation.
-
- If in doubt, say N.
-
-config ACPI_CPPC_CPUFREQ_FIE
- bool "Frequency Invariance support for CPPC cpufreq driver"
- depends on ACPI_CPPC_CPUFREQ && GENERIC_ARCH_TOPOLOGY
- default y
- help
- This extends frequency invariance support in the CPPC cpufreq driver,
- by using CPPC delivered and reference performance counters.
-
- If in doubt, say N.
-
config ARM_ALLWINNER_SUN50I_CPUFREQ_NVMEM
tristate "Allwinner nvmem based SUN50I CPUFreq driver"
depends on ARCH_SUNXI
--
2.34.1
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH v1 -next 3/3] RISC-V: defconfig: Enable CONFIG_ACPI_CPPC_CPUFREQ
2024-02-08 3:44 ` Sunil V L
@ 2024-02-08 3:44 ` Sunil V L
-1 siblings, 0 replies; 32+ messages in thread
From: Sunil V L @ 2024-02-08 3:44 UTC (permalink / raw
To: linux-riscv, linux-acpi, linux-kernel
Cc: Anup Patel, Albert Ou, Rafael J . Wysocki, Viresh Kumar,
Atish Kumar Patra, Conor Dooley, Palmer Dabbelt, Paul Walmsley,
Andrew Jones, Len Brown
CONFIG_ACPI_CPPC_CPUFREQ is required to enable CPPC for RISC-V.
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
---
arch/riscv/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig
index eaf34e871e30..2988ecd3eb4d 100644
--- a/arch/riscv/configs/defconfig
+++ b/arch/riscv/configs/defconfig
@@ -44,6 +44,7 @@ CONFIG_CPU_FREQ_GOV_USERSPACE=y
CONFIG_CPU_FREQ_GOV_ONDEMAND=y
CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m
CONFIG_CPUFREQ_DT=y
+CONFIG_ACPI_CPPC_CPUFREQ=m
CONFIG_VIRTUALIZATION=y
CONFIG_KVM=m
CONFIG_ACPI=y
--
2.34.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH v1 -next 3/3] RISC-V: defconfig: Enable CONFIG_ACPI_CPPC_CPUFREQ
@ 2024-02-08 3:44 ` Sunil V L
0 siblings, 0 replies; 32+ messages in thread
From: Sunil V L @ 2024-02-08 3:44 UTC (permalink / raw
To: linux-riscv, linux-acpi, linux-kernel
Cc: Rafael J . Wysocki, Len Brown, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Viresh Kumar, Conor Dooley, Andrew Jones,
Atish Kumar Patra, Anup Patel, Sunil V L
CONFIG_ACPI_CPPC_CPUFREQ is required to enable CPPC for RISC-V.
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
---
arch/riscv/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig
index eaf34e871e30..2988ecd3eb4d 100644
--- a/arch/riscv/configs/defconfig
+++ b/arch/riscv/configs/defconfig
@@ -44,6 +44,7 @@ CONFIG_CPU_FREQ_GOV_USERSPACE=y
CONFIG_CPU_FREQ_GOV_ONDEMAND=y
CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m
CONFIG_CPUFREQ_DT=y
+CONFIG_ACPI_CPPC_CPUFREQ=m
CONFIG_VIRTUALIZATION=y
CONFIG_KVM=m
CONFIG_ACPI=y
--
2.34.1
^ permalink raw reply related [flat|nested] 32+ messages in thread
* Re: [PATCH v1 -next 0/3] RISC-V: ACPI: Enable CPPC based cpufreq support
2024-02-08 3:44 ` Sunil V L
@ 2024-02-09 11:11 ` Pierre Gondois
-1 siblings, 0 replies; 32+ messages in thread
From: Pierre Gondois @ 2024-02-09 11:11 UTC (permalink / raw
To: Sunil V L, linux-riscv, linux-acpi, linux-kernel
Cc: Anup Patel, Albert Ou, Rafael J . Wysocki, Viresh Kumar,
Atish Kumar Patra, Conor Dooley, Palmer Dabbelt, Paul Walmsley,
Andrew Jones, Len Brown, Sudeep Holla
The code looks good to me, so FWIW:
Reviewed-by: Pierre Gondois <pierre.gondois@arm.com>
+Sudeep as this touches cppc/arm in case he didn't see the patches
On 2/8/24 04:44, Sunil V L wrote:
> This series enables the support for "Collaborative Processor Performance
> Control (CPPC) on ACPI based RISC-V platforms. It depends on the
> encoding of CPPC registers as defined in RISC-V FFH spec [2].
>
> CPPC is described in the ACPI spec [1]. RISC-V FFH spec required to
> enable this, is available at [2].
>
> [1] - https://uefi.org/specs/ACPI/6.5/08_Processor_Configuration_and_Control.html#collaborative-processor-performance-control
> [2] - https://github.com/riscv-non-isa/riscv-acpi-ffh/releases/download/v1.0.0/riscv-ffh.pdf
>
> The series is based on the LPI support series.
> Based-on: 20240118062930.245937-1-sunilvl@ventanamicro.com
> (https://lore.kernel.org/lkml/20240118062930.245937-1-sunilvl@ventanamicro.com/)
>
> Sunil V L (3):
> ACPI: RISC-V: Add CPPC driver
> cpufreq: Move CPPC configs to common Kconfig and add RISC-V
> RISC-V: defconfig: Enable CONFIG_ACPI_CPPC_CPUFREQ
>
> arch/riscv/configs/defconfig | 1 +
> drivers/acpi/riscv/Makefile | 1 +
> drivers/acpi/riscv/cppc.c | 157 +++++++++++++++++++++++++++++++++++
> drivers/cpufreq/Kconfig | 29 +++++++
> drivers/cpufreq/Kconfig.arm | 26 ------
> 5 files changed, 188 insertions(+), 26 deletions(-)
> create mode 100644 drivers/acpi/riscv/cppc.c
>
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v1 -next 0/3] RISC-V: ACPI: Enable CPPC based cpufreq support
@ 2024-02-09 11:11 ` Pierre Gondois
0 siblings, 0 replies; 32+ messages in thread
From: Pierre Gondois @ 2024-02-09 11:11 UTC (permalink / raw
To: Sunil V L, linux-riscv, linux-acpi, linux-kernel
Cc: Anup Patel, Albert Ou, Rafael J . Wysocki, Viresh Kumar,
Atish Kumar Patra, Conor Dooley, Palmer Dabbelt, Paul Walmsley,
Andrew Jones, Len Brown, Sudeep Holla
The code looks good to me, so FWIW:
Reviewed-by: Pierre Gondois <pierre.gondois@arm.com>
+Sudeep as this touches cppc/arm in case he didn't see the patches
On 2/8/24 04:44, Sunil V L wrote:
> This series enables the support for "Collaborative Processor Performance
> Control (CPPC) on ACPI based RISC-V platforms. It depends on the
> encoding of CPPC registers as defined in RISC-V FFH spec [2].
>
> CPPC is described in the ACPI spec [1]. RISC-V FFH spec required to
> enable this, is available at [2].
>
> [1] - https://uefi.org/specs/ACPI/6.5/08_Processor_Configuration_and_Control.html#collaborative-processor-performance-control
> [2] - https://github.com/riscv-non-isa/riscv-acpi-ffh/releases/download/v1.0.0/riscv-ffh.pdf
>
> The series is based on the LPI support series.
> Based-on: 20240118062930.245937-1-sunilvl@ventanamicro.com
> (https://lore.kernel.org/lkml/20240118062930.245937-1-sunilvl@ventanamicro.com/)
>
> Sunil V L (3):
> ACPI: RISC-V: Add CPPC driver
> cpufreq: Move CPPC configs to common Kconfig and add RISC-V
> RISC-V: defconfig: Enable CONFIG_ACPI_CPPC_CPUFREQ
>
> arch/riscv/configs/defconfig | 1 +
> drivers/acpi/riscv/Makefile | 1 +
> drivers/acpi/riscv/cppc.c | 157 +++++++++++++++++++++++++++++++++++
> drivers/cpufreq/Kconfig | 29 +++++++
> drivers/cpufreq/Kconfig.arm | 26 ------
> 5 files changed, 188 insertions(+), 26 deletions(-)
> create mode 100644 drivers/acpi/riscv/cppc.c
>
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v1 -next 0/3] RISC-V: ACPI: Enable CPPC based cpufreq support
2024-02-08 3:44 ` Sunil V L
@ 2024-02-12 15:24 ` Rafael J. Wysocki
-1 siblings, 0 replies; 32+ messages in thread
From: Rafael J. Wysocki @ 2024-02-12 15:24 UTC (permalink / raw
To: Sunil V L
Cc: linux-riscv, linux-acpi, linux-kernel, Rafael J . Wysocki,
Len Brown, Paul Walmsley, Palmer Dabbelt, Albert Ou, Viresh Kumar,
Conor Dooley, Andrew Jones, Atish Kumar Patra, Anup Patel
On Thu, Feb 8, 2024 at 4:44 AM Sunil V L <sunilvl@ventanamicro.com> wrote:
>
> This series enables the support for "Collaborative Processor Performance
> Control (CPPC) on ACPI based RISC-V platforms. It depends on the
> encoding of CPPC registers as defined in RISC-V FFH spec [2].
>
> CPPC is described in the ACPI spec [1]. RISC-V FFH spec required to
> enable this, is available at [2].
>
> [1] - https://uefi.org/specs/ACPI/6.5/08_Processor_Configuration_and_Control.html#collaborative-processor-performance-control
> [2] - https://github.com/riscv-non-isa/riscv-acpi-ffh/releases/download/v1.0.0/riscv-ffh.pdf
>
> The series is based on the LPI support series.
> Based-on: 20240118062930.245937-1-sunilvl@ventanamicro.com
> (https://lore.kernel.org/lkml/20240118062930.245937-1-sunilvl@ventanamicro.com/)
>
> Sunil V L (3):
> ACPI: RISC-V: Add CPPC driver
> cpufreq: Move CPPC configs to common Kconfig and add RISC-V
> RISC-V: defconfig: Enable CONFIG_ACPI_CPPC_CPUFREQ
>
> arch/riscv/configs/defconfig | 1 +
> drivers/acpi/riscv/Makefile | 1 +
> drivers/acpi/riscv/cppc.c | 157 +++++++++++++++++++++++++++++++++++
> drivers/cpufreq/Kconfig | 29 +++++++
> drivers/cpufreq/Kconfig.arm | 26 ------
> 5 files changed, 188 insertions(+), 26 deletions(-)
> create mode 100644 drivers/acpi/riscv/cppc.c
>
> --
This is fine with me, so
Acked-by: Rafael J. Wysocki <rafael@kernel.org>
and it would be good to ask Viresh (who maintains the CPPC cpufreq
driver) for an ACK.
Thanks!
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v1 -next 0/3] RISC-V: ACPI: Enable CPPC based cpufreq support
@ 2024-02-12 15:24 ` Rafael J. Wysocki
0 siblings, 0 replies; 32+ messages in thread
From: Rafael J. Wysocki @ 2024-02-12 15:24 UTC (permalink / raw
To: Sunil V L
Cc: linux-riscv, linux-acpi, linux-kernel, Rafael J . Wysocki,
Len Brown, Paul Walmsley, Palmer Dabbelt, Albert Ou, Viresh Kumar,
Conor Dooley, Andrew Jones, Atish Kumar Patra, Anup Patel
On Thu, Feb 8, 2024 at 4:44 AM Sunil V L <sunilvl@ventanamicro.com> wrote:
>
> This series enables the support for "Collaborative Processor Performance
> Control (CPPC) on ACPI based RISC-V platforms. It depends on the
> encoding of CPPC registers as defined in RISC-V FFH spec [2].
>
> CPPC is described in the ACPI spec [1]. RISC-V FFH spec required to
> enable this, is available at [2].
>
> [1] - https://uefi.org/specs/ACPI/6.5/08_Processor_Configuration_and_Control.html#collaborative-processor-performance-control
> [2] - https://github.com/riscv-non-isa/riscv-acpi-ffh/releases/download/v1.0.0/riscv-ffh.pdf
>
> The series is based on the LPI support series.
> Based-on: 20240118062930.245937-1-sunilvl@ventanamicro.com
> (https://lore.kernel.org/lkml/20240118062930.245937-1-sunilvl@ventanamicro.com/)
>
> Sunil V L (3):
> ACPI: RISC-V: Add CPPC driver
> cpufreq: Move CPPC configs to common Kconfig and add RISC-V
> RISC-V: defconfig: Enable CONFIG_ACPI_CPPC_CPUFREQ
>
> arch/riscv/configs/defconfig | 1 +
> drivers/acpi/riscv/Makefile | 1 +
> drivers/acpi/riscv/cppc.c | 157 +++++++++++++++++++++++++++++++++++
> drivers/cpufreq/Kconfig | 29 +++++++
> drivers/cpufreq/Kconfig.arm | 26 ------
> 5 files changed, 188 insertions(+), 26 deletions(-)
> create mode 100644 drivers/acpi/riscv/cppc.c
>
> --
This is fine with me, so
Acked-by: Rafael J. Wysocki <rafael@kernel.org>
and it would be good to ask Viresh (who maintains the CPPC cpufreq
driver) for an ACK.
Thanks!
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v1 -next 2/3] cpufreq: Move CPPC configs to common Kconfig and add RISC-V
2024-02-08 3:44 ` Sunil V L
@ 2024-02-13 6:14 ` Viresh Kumar
-1 siblings, 0 replies; 32+ messages in thread
From: Viresh Kumar @ 2024-02-13 6:14 UTC (permalink / raw
To: Sunil V L
Cc: linux-riscv, linux-acpi, linux-kernel, Rafael J . Wysocki,
Len Brown, Paul Walmsley, Palmer Dabbelt, Albert Ou, Conor Dooley,
Andrew Jones, Atish Kumar Patra, Anup Patel
On 08-02-24, 09:14, Sunil V L wrote:
> CPPC related config options are currently defined only in ARM specific
> file. However, they are required for RISC-V as well. Instead of creating
> a new Kconfig.riscv file and duplicating them, move them to the common
> Kconfig file and enable RISC-V too.
>
> Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
> ---
> drivers/cpufreq/Kconfig | 29 +++++++++++++++++++++++++++++
> drivers/cpufreq/Kconfig.arm | 26 --------------------------
> 2 files changed, 29 insertions(+), 26 deletions(-)
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
--
viresh
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v1 -next 2/3] cpufreq: Move CPPC configs to common Kconfig and add RISC-V
@ 2024-02-13 6:14 ` Viresh Kumar
0 siblings, 0 replies; 32+ messages in thread
From: Viresh Kumar @ 2024-02-13 6:14 UTC (permalink / raw
To: Sunil V L
Cc: linux-riscv, linux-acpi, linux-kernel, Rafael J . Wysocki,
Len Brown, Paul Walmsley, Palmer Dabbelt, Albert Ou, Conor Dooley,
Andrew Jones, Atish Kumar Patra, Anup Patel
On 08-02-24, 09:14, Sunil V L wrote:
> CPPC related config options are currently defined only in ARM specific
> file. However, they are required for RISC-V as well. Instead of creating
> a new Kconfig.riscv file and duplicating them, move them to the common
> Kconfig file and enable RISC-V too.
>
> Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
> ---
> drivers/cpufreq/Kconfig | 29 +++++++++++++++++++++++++++++
> drivers/cpufreq/Kconfig.arm | 26 --------------------------
> 2 files changed, 29 insertions(+), 26 deletions(-)
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
--
viresh
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v1 -next 0/3] RISC-V: ACPI: Enable CPPC based cpufreq support
2024-02-12 15:24 ` Rafael J. Wysocki
@ 2024-02-13 6:15 ` Viresh Kumar
-1 siblings, 0 replies; 32+ messages in thread
From: Viresh Kumar @ 2024-02-13 6:15 UTC (permalink / raw
To: Rafael J. Wysocki
Cc: Sunil V L, linux-riscv, linux-acpi, linux-kernel, Len Brown,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Conor Dooley,
Andrew Jones, Atish Kumar Patra, Anup Patel
On 12-02-24, 16:24, Rafael J. Wysocki wrote:
> On Thu, Feb 8, 2024 at 4:44 AM Sunil V L <sunilvl@ventanamicro.com> wrote:
> >
> > This series enables the support for "Collaborative Processor Performance
> > Control (CPPC) on ACPI based RISC-V platforms. It depends on the
> > encoding of CPPC registers as defined in RISC-V FFH spec [2].
> >
> > CPPC is described in the ACPI spec [1]. RISC-V FFH spec required to
> > enable this, is available at [2].
> >
> > [1] - https://uefi.org/specs/ACPI/6.5/08_Processor_Configuration_and_Control.html#collaborative-processor-performance-control
> > [2] - https://github.com/riscv-non-isa/riscv-acpi-ffh/releases/download/v1.0.0/riscv-ffh.pdf
> >
> > The series is based on the LPI support series.
> > Based-on: 20240118062930.245937-1-sunilvl@ventanamicro.com
> > (https://lore.kernel.org/lkml/20240118062930.245937-1-sunilvl@ventanamicro.com/)
> >
> > Sunil V L (3):
> > ACPI: RISC-V: Add CPPC driver
> > cpufreq: Move CPPC configs to common Kconfig and add RISC-V
> > RISC-V: defconfig: Enable CONFIG_ACPI_CPPC_CPUFREQ
> >
> > arch/riscv/configs/defconfig | 1 +
> > drivers/acpi/riscv/Makefile | 1 +
> > drivers/acpi/riscv/cppc.c | 157 +++++++++++++++++++++++++++++++++++
> > drivers/cpufreq/Kconfig | 29 +++++++
> > drivers/cpufreq/Kconfig.arm | 26 ------
> > 5 files changed, 188 insertions(+), 26 deletions(-)
> > create mode 100644 drivers/acpi/riscv/cppc.c
> >
> > --
>
> This is fine with me, so
>
> Acked-by: Rafael J. Wysocki <rafael@kernel.org>
>
> and it would be good to ask Viresh (who maintains the CPPC cpufreq
> driver) for an ACK.
I have provided my Ack over the cpufreq patch. Thanks.
--
viresh
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v1 -next 0/3] RISC-V: ACPI: Enable CPPC based cpufreq support
@ 2024-02-13 6:15 ` Viresh Kumar
0 siblings, 0 replies; 32+ messages in thread
From: Viresh Kumar @ 2024-02-13 6:15 UTC (permalink / raw
To: Rafael J. Wysocki
Cc: Anup Patel, Albert Ou, Atish Kumar Patra, linux-kernel,
linux-acpi, Conor Dooley, Palmer Dabbelt, Paul Walmsley,
linux-riscv, Andrew Jones, Len Brown
On 12-02-24, 16:24, Rafael J. Wysocki wrote:
> On Thu, Feb 8, 2024 at 4:44 AM Sunil V L <sunilvl@ventanamicro.com> wrote:
> >
> > This series enables the support for "Collaborative Processor Performance
> > Control (CPPC) on ACPI based RISC-V platforms. It depends on the
> > encoding of CPPC registers as defined in RISC-V FFH spec [2].
> >
> > CPPC is described in the ACPI spec [1]. RISC-V FFH spec required to
> > enable this, is available at [2].
> >
> > [1] - https://uefi.org/specs/ACPI/6.5/08_Processor_Configuration_and_Control.html#collaborative-processor-performance-control
> > [2] - https://github.com/riscv-non-isa/riscv-acpi-ffh/releases/download/v1.0.0/riscv-ffh.pdf
> >
> > The series is based on the LPI support series.
> > Based-on: 20240118062930.245937-1-sunilvl@ventanamicro.com
> > (https://lore.kernel.org/lkml/20240118062930.245937-1-sunilvl@ventanamicro.com/)
> >
> > Sunil V L (3):
> > ACPI: RISC-V: Add CPPC driver
> > cpufreq: Move CPPC configs to common Kconfig and add RISC-V
> > RISC-V: defconfig: Enable CONFIG_ACPI_CPPC_CPUFREQ
> >
> > arch/riscv/configs/defconfig | 1 +
> > drivers/acpi/riscv/Makefile | 1 +
> > drivers/acpi/riscv/cppc.c | 157 +++++++++++++++++++++++++++++++++++
> > drivers/cpufreq/Kconfig | 29 +++++++
> > drivers/cpufreq/Kconfig.arm | 26 ------
> > 5 files changed, 188 insertions(+), 26 deletions(-)
> > create mode 100644 drivers/acpi/riscv/cppc.c
> >
> > --
>
> This is fine with me, so
>
> Acked-by: Rafael J. Wysocki <rafael@kernel.org>
>
> and it would be good to ask Viresh (who maintains the CPPC cpufreq
> driver) for an ACK.
I have provided my Ack over the cpufreq patch. Thanks.
--
viresh
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v1 -next 0/3] RISC-V: ACPI: Enable CPPC based cpufreq support
2024-02-09 11:11 ` Pierre Gondois
@ 2024-02-15 11:27 ` Sudeep Holla
-1 siblings, 0 replies; 32+ messages in thread
From: Sudeep Holla @ 2024-02-15 11:27 UTC (permalink / raw
To: Sunil V L, linux-riscv, Pierre Gondois
Cc: linux-acpi, linux-kernel, Anup Patel, Albert Ou,
Rafael J . Wysocki, Viresh Kumar, Atish Kumar Patra, Conor Dooley,
Palmer Dabbelt, Paul Walmsley, Andrew Jones, Len Brown
On Fri, Feb 09, 2024 at 12:11:11PM +0100, Pierre Gondois wrote:
> The code looks good to me, so FWIW:
> Reviewed-by: Pierre Gondois <pierre.gondois@arm.com>
>
> +Sudeep as this touches cppc/arm in case he didn't see the patches
>
Thanks!
> On 2/8/24 04:44, Sunil V L wrote:
> > This series enables the support for "Collaborative Processor Performance
> > Control (CPPC) on ACPI based RISC-V platforms. It depends on the
> > encoding of CPPC registers as defined in RISC-V FFH spec [2].
> >
> > CPPC is described in the ACPI spec [1]. RISC-V FFH spec required to
> > enable this, is available at [2].
> >
> > [1] - https://uefi.org/specs/ACPI/6.5/08_Processor_Configuration_and_Control.html#collaborative-processor-performance-control
> > [2] - https://github.com/riscv-non-isa/riscv-acpi-ffh/releases/download/v1.0.0/riscv-ffh.pdf
> >
> > The series is based on the LPI support series.
> > Based-on: 20240118062930.245937-1-sunilvl@ventanamicro.com
> > (https://lore.kernel.org/lkml/20240118062930.245937-1-sunilvl@ventanamicro.com/)
> >
> > Sunil V L (3):
> > ACPI: RISC-V: Add CPPC driver
> > cpufreq: Move CPPC configs to common Kconfig and add RISC-V
> > RISC-V: defconfig: Enable CONFIG_ACPI_CPPC_CPUFREQ
> >
Looks good to me.
Acked-by: Sudeep Holla <sudeep.holla@arm.com>
--
Regards,
Sudeep
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v1 -next 0/3] RISC-V: ACPI: Enable CPPC based cpufreq support
@ 2024-02-15 11:27 ` Sudeep Holla
0 siblings, 0 replies; 32+ messages in thread
From: Sudeep Holla @ 2024-02-15 11:27 UTC (permalink / raw
To: Sunil V L, linux-riscv, Pierre Gondois
Cc: linux-acpi, linux-kernel, Anup Patel, Albert Ou,
Rafael J . Wysocki, Viresh Kumar, Atish Kumar Patra, Conor Dooley,
Palmer Dabbelt, Paul Walmsley, Andrew Jones, Len Brown
On Fri, Feb 09, 2024 at 12:11:11PM +0100, Pierre Gondois wrote:
> The code looks good to me, so FWIW:
> Reviewed-by: Pierre Gondois <pierre.gondois@arm.com>
>
> +Sudeep as this touches cppc/arm in case he didn't see the patches
>
Thanks!
> On 2/8/24 04:44, Sunil V L wrote:
> > This series enables the support for "Collaborative Processor Performance
> > Control (CPPC) on ACPI based RISC-V platforms. It depends on the
> > encoding of CPPC registers as defined in RISC-V FFH spec [2].
> >
> > CPPC is described in the ACPI spec [1]. RISC-V FFH spec required to
> > enable this, is available at [2].
> >
> > [1] - https://uefi.org/specs/ACPI/6.5/08_Processor_Configuration_and_Control.html#collaborative-processor-performance-control
> > [2] - https://github.com/riscv-non-isa/riscv-acpi-ffh/releases/download/v1.0.0/riscv-ffh.pdf
> >
> > The series is based on the LPI support series.
> > Based-on: 20240118062930.245937-1-sunilvl@ventanamicro.com
> > (https://lore.kernel.org/lkml/20240118062930.245937-1-sunilvl@ventanamicro.com/)
> >
> > Sunil V L (3):
> > ACPI: RISC-V: Add CPPC driver
> > cpufreq: Move CPPC configs to common Kconfig and add RISC-V
> > RISC-V: defconfig: Enable CONFIG_ACPI_CPPC_CPUFREQ
> >
Looks good to me.
Acked-by: Sudeep Holla <sudeep.holla@arm.com>
--
Regards,
Sudeep
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v1 -next 0/3] RISC-V: ACPI: Enable CPPC based cpufreq support
2024-02-08 3:44 ` Sunil V L
@ 2024-03-18 18:40 ` Drew Fustini
-1 siblings, 0 replies; 32+ messages in thread
From: Drew Fustini @ 2024-03-18 18:40 UTC (permalink / raw
To: Sunil V L
Cc: linux-riscv, linux-acpi, linux-kernel, Rafael J . Wysocki,
Len Brown, Paul Walmsley, Palmer Dabbelt, Albert Ou, Viresh Kumar,
Conor Dooley, Andrew Jones, Atish Kumar Patra, Anup Patel
On Thu, Feb 08, 2024 at 09:14:11AM +0530, Sunil V L wrote:
> This series enables the support for "Collaborative Processor Performance
> Control (CPPC) on ACPI based RISC-V platforms. It depends on the
> encoding of CPPC registers as defined in RISC-V FFH spec [2].
>
> CPPC is described in the ACPI spec [1]. RISC-V FFH spec required to
> enable this, is available at [2].
>
> [1] - https://uefi.org/specs/ACPI/6.5/08_Processor_Configuration_and_Control.html#collaborative-processor-performance-control
> [2] - https://github.com/riscv-non-isa/riscv-acpi-ffh/releases/download/v1.0.0/riscv-ffh.pdf
>
> The series is based on the LPI support series.
> Based-on: 20240118062930.245937-1-sunilvl@ventanamicro.com
> (https://lore.kernel.org/lkml/20240118062930.245937-1-sunilvl@ventanamicro.com/)
Should the https://github.com/vlsunil/qemu/tree/lpi_exp branch also be
used for this CPPC series too?
Thanks,
Drew
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v1 -next 0/3] RISC-V: ACPI: Enable CPPC based cpufreq support
@ 2024-03-18 18:40 ` Drew Fustini
0 siblings, 0 replies; 32+ messages in thread
From: Drew Fustini @ 2024-03-18 18:40 UTC (permalink / raw
To: Sunil V L
Cc: linux-riscv, linux-acpi, linux-kernel, Rafael J . Wysocki,
Len Brown, Paul Walmsley, Palmer Dabbelt, Albert Ou, Viresh Kumar,
Conor Dooley, Andrew Jones, Atish Kumar Patra, Anup Patel
On Thu, Feb 08, 2024 at 09:14:11AM +0530, Sunil V L wrote:
> This series enables the support for "Collaborative Processor Performance
> Control (CPPC) on ACPI based RISC-V platforms. It depends on the
> encoding of CPPC registers as defined in RISC-V FFH spec [2].
>
> CPPC is described in the ACPI spec [1]. RISC-V FFH spec required to
> enable this, is available at [2].
>
> [1] - https://uefi.org/specs/ACPI/6.5/08_Processor_Configuration_and_Control.html#collaborative-processor-performance-control
> [2] - https://github.com/riscv-non-isa/riscv-acpi-ffh/releases/download/v1.0.0/riscv-ffh.pdf
>
> The series is based on the LPI support series.
> Based-on: 20240118062930.245937-1-sunilvl@ventanamicro.com
> (https://lore.kernel.org/lkml/20240118062930.245937-1-sunilvl@ventanamicro.com/)
Should the https://github.com/vlsunil/qemu/tree/lpi_exp branch also be
used for this CPPC series too?
Thanks,
Drew
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v1 -next 0/3] RISC-V: ACPI: Enable CPPC based cpufreq support
2024-03-18 18:40 ` Drew Fustini
@ 2024-03-19 2:27 ` Drew Fustini
-1 siblings, 0 replies; 32+ messages in thread
From: Drew Fustini @ 2024-03-19 2:27 UTC (permalink / raw
To: Sunil V L
Cc: linux-riscv, linux-acpi, linux-kernel, Rafael J . Wysocki,
Len Brown, Paul Walmsley, Palmer Dabbelt, Albert Ou, Viresh Kumar,
Conor Dooley, Andrew Jones, Atish Kumar Patra, Anup Patel
On Mon, Mar 18, 2024 at 11:40:34AM -0700, Drew Fustini wrote:
> On Thu, Feb 08, 2024 at 09:14:11AM +0530, Sunil V L wrote:
> > This series enables the support for "Collaborative Processor Performance
> > Control (CPPC) on ACPI based RISC-V platforms. It depends on the
> > encoding of CPPC registers as defined in RISC-V FFH spec [2].
> >
> > CPPC is described in the ACPI spec [1]. RISC-V FFH spec required to
> > enable this, is available at [2].
> >
> > [1] - https://uefi.org/specs/ACPI/6.5/08_Processor_Configuration_and_Control.html#collaborative-processor-performance-control
> > [2] - https://github.com/riscv-non-isa/riscv-acpi-ffh/releases/download/v1.0.0/riscv-ffh.pdf
> >
> > The series is based on the LPI support series.
> > Based-on: 20240118062930.245937-1-sunilvl@ventanamicro.com
> > (https://lore.kernel.org/lkml/20240118062930.245937-1-sunilvl@ventanamicro.com/)
>
> Should the https://github.com/vlsunil/qemu/tree/lpi_exp branch also be
> used for this CPPC series too?
I noticed the ventanamicro qemu repo has a dev-upstream branch [1] which
contains 4bb6ba4d0fb9 ("riscv/virt: acpi: Enable CPPC - _CPC and _PSD").
I've built that but I still see 'SBI CPPC extension NOT detected!!' in
the Linux boot log.
I'm using upstream opensbi. It seems that sbi_cppc_probe() fails because
cppc_dev is not set. Nothing in the upstream opensbi repo seems to call
sbi_cppc_set_device(), so I am uncertain how it is possible for it to
work. Is there an opensbi branch I should be using?
Thanks,
Drew
[1] https://github.com/ventanamicro/qemu/tree/dev-upstream
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v1 -next 0/3] RISC-V: ACPI: Enable CPPC based cpufreq support
@ 2024-03-19 2:27 ` Drew Fustini
0 siblings, 0 replies; 32+ messages in thread
From: Drew Fustini @ 2024-03-19 2:27 UTC (permalink / raw
To: Sunil V L
Cc: linux-riscv, linux-acpi, linux-kernel, Rafael J . Wysocki,
Len Brown, Paul Walmsley, Palmer Dabbelt, Albert Ou, Viresh Kumar,
Conor Dooley, Andrew Jones, Atish Kumar Patra, Anup Patel
On Mon, Mar 18, 2024 at 11:40:34AM -0700, Drew Fustini wrote:
> On Thu, Feb 08, 2024 at 09:14:11AM +0530, Sunil V L wrote:
> > This series enables the support for "Collaborative Processor Performance
> > Control (CPPC) on ACPI based RISC-V platforms. It depends on the
> > encoding of CPPC registers as defined in RISC-V FFH spec [2].
> >
> > CPPC is described in the ACPI spec [1]. RISC-V FFH spec required to
> > enable this, is available at [2].
> >
> > [1] - https://uefi.org/specs/ACPI/6.5/08_Processor_Configuration_and_Control.html#collaborative-processor-performance-control
> > [2] - https://github.com/riscv-non-isa/riscv-acpi-ffh/releases/download/v1.0.0/riscv-ffh.pdf
> >
> > The series is based on the LPI support series.
> > Based-on: 20240118062930.245937-1-sunilvl@ventanamicro.com
> > (https://lore.kernel.org/lkml/20240118062930.245937-1-sunilvl@ventanamicro.com/)
>
> Should the https://github.com/vlsunil/qemu/tree/lpi_exp branch also be
> used for this CPPC series too?
I noticed the ventanamicro qemu repo has a dev-upstream branch [1] which
contains 4bb6ba4d0fb9 ("riscv/virt: acpi: Enable CPPC - _CPC and _PSD").
I've built that but I still see 'SBI CPPC extension NOT detected!!' in
the Linux boot log.
I'm using upstream opensbi. It seems that sbi_cppc_probe() fails because
cppc_dev is not set. Nothing in the upstream opensbi repo seems to call
sbi_cppc_set_device(), so I am uncertain how it is possible for it to
work. Is there an opensbi branch I should be using?
Thanks,
Drew
[1] https://github.com/ventanamicro/qemu/tree/dev-upstream
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v1 -next 0/3] RISC-V: ACPI: Enable CPPC based cpufreq support
2024-03-19 2:27 ` Drew Fustini
@ 2024-03-19 10:20 ` Sunil V L
-1 siblings, 0 replies; 32+ messages in thread
From: Sunil V L @ 2024-03-19 10:20 UTC (permalink / raw
To: Drew Fustini
Cc: linux-riscv, linux-acpi, linux-kernel, Rafael J . Wysocki,
Len Brown, Paul Walmsley, Palmer Dabbelt, Albert Ou, Viresh Kumar,
Conor Dooley, Andrew Jones, Atish Kumar Patra, Anup Patel
On Mon, Mar 18, 2024 at 07:27:34PM -0700, Drew Fustini wrote:
> On Mon, Mar 18, 2024 at 11:40:34AM -0700, Drew Fustini wrote:
> > On Thu, Feb 08, 2024 at 09:14:11AM +0530, Sunil V L wrote:
> > > This series enables the support for "Collaborative Processor Performance
> > > Control (CPPC) on ACPI based RISC-V platforms. It depends on the
> > > encoding of CPPC registers as defined in RISC-V FFH spec [2].
> > >
> > > CPPC is described in the ACPI spec [1]. RISC-V FFH spec required to
> > > enable this, is available at [2].
> > >
> > > [1] - https://uefi.org/specs/ACPI/6.5/08_Processor_Configuration_and_Control.html#collaborative-processor-performance-control
> > > [2] - https://github.com/riscv-non-isa/riscv-acpi-ffh/releases/download/v1.0.0/riscv-ffh.pdf
> > >
> > > The series is based on the LPI support series.
> > > Based-on: 20240118062930.245937-1-sunilvl@ventanamicro.com
> > > (https://lore.kernel.org/lkml/20240118062930.245937-1-sunilvl@ventanamicro.com/)
> >
> > Should the https://github.com/vlsunil/qemu/tree/lpi_exp branch also be
> > used for this CPPC series too?
>
> I noticed the ventanamicro qemu repo has a dev-upstream branch [1] which
> contains 4bb6ba4d0fb9 ("riscv/virt: acpi: Enable CPPC - _CPC and _PSD").
> I've built that but I still see 'SBI CPPC extension NOT detected!!' in
> the Linux boot log.
>
> I'm using upstream opensbi. It seems that sbi_cppc_probe() fails because
> cppc_dev is not set. Nothing in the upstream opensbi repo seems to call
> sbi_cppc_set_device(), so I am uncertain how it is possible for it to
> work. Is there an opensbi branch I should be using?
>
> Thanks,
> Drew
>
> [1] https://github.com/ventanamicro/qemu/tree/dev-upstream
Please use below branches for qemu and opensbi. These are just dummy
objects/interfaces added to test the kernel change which are otherwise
platform specific features.
https://github.com/vlsunil/qemu/tree/lpi_cppc_exp
https://github.com/vlsunil/opensbi/tree/cppc_exp
Regards
Sunil
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v1 -next 0/3] RISC-V: ACPI: Enable CPPC based cpufreq support
@ 2024-03-19 10:20 ` Sunil V L
0 siblings, 0 replies; 32+ messages in thread
From: Sunil V L @ 2024-03-19 10:20 UTC (permalink / raw
To: Drew Fustini
Cc: linux-riscv, linux-acpi, linux-kernel, Rafael J . Wysocki,
Len Brown, Paul Walmsley, Palmer Dabbelt, Albert Ou, Viresh Kumar,
Conor Dooley, Andrew Jones, Atish Kumar Patra, Anup Patel
On Mon, Mar 18, 2024 at 07:27:34PM -0700, Drew Fustini wrote:
> On Mon, Mar 18, 2024 at 11:40:34AM -0700, Drew Fustini wrote:
> > On Thu, Feb 08, 2024 at 09:14:11AM +0530, Sunil V L wrote:
> > > This series enables the support for "Collaborative Processor Performance
> > > Control (CPPC) on ACPI based RISC-V platforms. It depends on the
> > > encoding of CPPC registers as defined in RISC-V FFH spec [2].
> > >
> > > CPPC is described in the ACPI spec [1]. RISC-V FFH spec required to
> > > enable this, is available at [2].
> > >
> > > [1] - https://uefi.org/specs/ACPI/6.5/08_Processor_Configuration_and_Control.html#collaborative-processor-performance-control
> > > [2] - https://github.com/riscv-non-isa/riscv-acpi-ffh/releases/download/v1.0.0/riscv-ffh.pdf
> > >
> > > The series is based on the LPI support series.
> > > Based-on: 20240118062930.245937-1-sunilvl@ventanamicro.com
> > > (https://lore.kernel.org/lkml/20240118062930.245937-1-sunilvl@ventanamicro.com/)
> >
> > Should the https://github.com/vlsunil/qemu/tree/lpi_exp branch also be
> > used for this CPPC series too?
>
> I noticed the ventanamicro qemu repo has a dev-upstream branch [1] which
> contains 4bb6ba4d0fb9 ("riscv/virt: acpi: Enable CPPC - _CPC and _PSD").
> I've built that but I still see 'SBI CPPC extension NOT detected!!' in
> the Linux boot log.
>
> I'm using upstream opensbi. It seems that sbi_cppc_probe() fails because
> cppc_dev is not set. Nothing in the upstream opensbi repo seems to call
> sbi_cppc_set_device(), so I am uncertain how it is possible for it to
> work. Is there an opensbi branch I should be using?
>
> Thanks,
> Drew
>
> [1] https://github.com/ventanamicro/qemu/tree/dev-upstream
Please use below branches for qemu and opensbi. These are just dummy
objects/interfaces added to test the kernel change which are otherwise
platform specific features.
https://github.com/vlsunil/qemu/tree/lpi_cppc_exp
https://github.com/vlsunil/opensbi/tree/cppc_exp
Regards
Sunil
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v1 -next 0/3] RISC-V: ACPI: Enable CPPC based cpufreq support
2024-03-19 10:20 ` Sunil V L
@ 2024-03-20 6:54 ` Drew Fustini
-1 siblings, 0 replies; 32+ messages in thread
From: Drew Fustini @ 2024-03-20 6:54 UTC (permalink / raw
To: Sunil V L
Cc: linux-riscv, linux-acpi, linux-kernel, Rafael J . Wysocki,
Len Brown, Paul Walmsley, Palmer Dabbelt, Albert Ou, Viresh Kumar,
Conor Dooley, Andrew Jones, Atish Kumar Patra, Anup Patel
On Tue, Mar 19, 2024 at 03:50:21PM +0530, Sunil V L wrote:
> On Mon, Mar 18, 2024 at 07:27:34PM -0700, Drew Fustini wrote:
> > On Mon, Mar 18, 2024 at 11:40:34AM -0700, Drew Fustini wrote:
> > > On Thu, Feb 08, 2024 at 09:14:11AM +0530, Sunil V L wrote:
> > > > This series enables the support for "Collaborative Processor Performance
> > > > Control (CPPC) on ACPI based RISC-V platforms. It depends on the
> > > > encoding of CPPC registers as defined in RISC-V FFH spec [2].
> > > >
> > > > CPPC is described in the ACPI spec [1]. RISC-V FFH spec required to
> > > > enable this, is available at [2].
> > > >
> > > > [1] - https://uefi.org/specs/ACPI/6.5/08_Processor_Configuration_and_Control.html#collaborative-processor-performance-control
> > > > [2] - https://github.com/riscv-non-isa/riscv-acpi-ffh/releases/download/v1.0.0/riscv-ffh.pdf
> > > >
> > > > The series is based on the LPI support series.
> > > > Based-on: 20240118062930.245937-1-sunilvl@ventanamicro.com
> > > > (https://lore.kernel.org/lkml/20240118062930.245937-1-sunilvl@ventanamicro.com/)
> > >
> > > Should the https://github.com/vlsunil/qemu/tree/lpi_exp branch also be
> > > used for this CPPC series too?
> >
> > I noticed the ventanamicro qemu repo has a dev-upstream branch [1] which
> > contains 4bb6ba4d0fb9 ("riscv/virt: acpi: Enable CPPC - _CPC and _PSD").
> > I've built that but I still see 'SBI CPPC extension NOT detected!!' in
> > the Linux boot log.
> >
> > I'm using upstream opensbi. It seems that sbi_cppc_probe() fails because
> > cppc_dev is not set. Nothing in the upstream opensbi repo seems to call
> > sbi_cppc_set_device(), so I am uncertain how it is possible for it to
> > work. Is there an opensbi branch I should be using?
> >
> > Thanks,
> > Drew
> >
> > [1] https://github.com/ventanamicro/qemu/tree/dev-upstream
>
> Please use below branches for qemu and opensbi. These are just dummy
> objects/interfaces added to test the kernel change which are otherwise
> platform specific features.
>
> https://github.com/vlsunil/qemu/tree/lpi_cppc_exp
> https://github.com/vlsunil/opensbi/tree/cppc_exp
Thank you for providing those branches.
The CPPC extension is now detected okay during boot but I see the
following in the boot log [1]:
[ 1.094707] cpufreq: cpufreq_online: ->get() failed
Have you seen that too?
This appears to be from the following in drivers/cpufreq/cpufreq.c
1500 if (cpufreq_driver->get && has_target()) {
1501 policy->cur = cpufreq_driver->get(policy->cpu);
1502 if (!policy->cur) {
1503 ret = -EIO;
1504 pr_err("%s: ->get() failed\n", __func__);
1505 goto out_destroy_policy;
1506 }
1507 }
I'm not very familiar with the cpufreq code yet. My first thought is
that maybe the get() function pointer isn't set correctly?
thanks,
drew
[1] https://gist.github.com/pdp7/00ab047509d25871f87b3dc1b2445eaa
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v1 -next 0/3] RISC-V: ACPI: Enable CPPC based cpufreq support
@ 2024-03-20 6:54 ` Drew Fustini
0 siblings, 0 replies; 32+ messages in thread
From: Drew Fustini @ 2024-03-20 6:54 UTC (permalink / raw
To: Sunil V L
Cc: linux-riscv, linux-acpi, linux-kernel, Rafael J . Wysocki,
Len Brown, Paul Walmsley, Palmer Dabbelt, Albert Ou, Viresh Kumar,
Conor Dooley, Andrew Jones, Atish Kumar Patra, Anup Patel
On Tue, Mar 19, 2024 at 03:50:21PM +0530, Sunil V L wrote:
> On Mon, Mar 18, 2024 at 07:27:34PM -0700, Drew Fustini wrote:
> > On Mon, Mar 18, 2024 at 11:40:34AM -0700, Drew Fustini wrote:
> > > On Thu, Feb 08, 2024 at 09:14:11AM +0530, Sunil V L wrote:
> > > > This series enables the support for "Collaborative Processor Performance
> > > > Control (CPPC) on ACPI based RISC-V platforms. It depends on the
> > > > encoding of CPPC registers as defined in RISC-V FFH spec [2].
> > > >
> > > > CPPC is described in the ACPI spec [1]. RISC-V FFH spec required to
> > > > enable this, is available at [2].
> > > >
> > > > [1] - https://uefi.org/specs/ACPI/6.5/08_Processor_Configuration_and_Control.html#collaborative-processor-performance-control
> > > > [2] - https://github.com/riscv-non-isa/riscv-acpi-ffh/releases/download/v1.0.0/riscv-ffh.pdf
> > > >
> > > > The series is based on the LPI support series.
> > > > Based-on: 20240118062930.245937-1-sunilvl@ventanamicro.com
> > > > (https://lore.kernel.org/lkml/20240118062930.245937-1-sunilvl@ventanamicro.com/)
> > >
> > > Should the https://github.com/vlsunil/qemu/tree/lpi_exp branch also be
> > > used for this CPPC series too?
> >
> > I noticed the ventanamicro qemu repo has a dev-upstream branch [1] which
> > contains 4bb6ba4d0fb9 ("riscv/virt: acpi: Enable CPPC - _CPC and _PSD").
> > I've built that but I still see 'SBI CPPC extension NOT detected!!' in
> > the Linux boot log.
> >
> > I'm using upstream opensbi. It seems that sbi_cppc_probe() fails because
> > cppc_dev is not set. Nothing in the upstream opensbi repo seems to call
> > sbi_cppc_set_device(), so I am uncertain how it is possible for it to
> > work. Is there an opensbi branch I should be using?
> >
> > Thanks,
> > Drew
> >
> > [1] https://github.com/ventanamicro/qemu/tree/dev-upstream
>
> Please use below branches for qemu and opensbi. These are just dummy
> objects/interfaces added to test the kernel change which are otherwise
> platform specific features.
>
> https://github.com/vlsunil/qemu/tree/lpi_cppc_exp
> https://github.com/vlsunil/opensbi/tree/cppc_exp
Thank you for providing those branches.
The CPPC extension is now detected okay during boot but I see the
following in the boot log [1]:
[ 1.094707] cpufreq: cpufreq_online: ->get() failed
Have you seen that too?
This appears to be from the following in drivers/cpufreq/cpufreq.c
1500 if (cpufreq_driver->get && has_target()) {
1501 policy->cur = cpufreq_driver->get(policy->cpu);
1502 if (!policy->cur) {
1503 ret = -EIO;
1504 pr_err("%s: ->get() failed\n", __func__);
1505 goto out_destroy_policy;
1506 }
1507 }
I'm not very familiar with the cpufreq code yet. My first thought is
that maybe the get() function pointer isn't set correctly?
thanks,
drew
[1] https://gist.github.com/pdp7/00ab047509d25871f87b3dc1b2445eaa
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linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v1 -next 0/3] RISC-V: ACPI: Enable CPPC based cpufreq support
2024-02-08 3:44 ` Sunil V L
@ 2024-03-20 20:50 ` patchwork-bot+linux-riscv
-1 siblings, 0 replies; 32+ messages in thread
From: patchwork-bot+linux-riscv @ 2024-03-20 20:50 UTC (permalink / raw
To: Sunil V L
Cc: linux-riscv, linux-acpi, linux-kernel, apatel, aou, rafael,
viresh.kumar, atishp, conor.dooley, palmer, paul.walmsley, ajones,
lenb
Hello:
This series was applied to riscv/linux.git (for-next)
by Palmer Dabbelt <palmer@rivosinc.com>:
On Thu, 8 Feb 2024 09:14:11 +0530 you wrote:
> This series enables the support for "Collaborative Processor Performance
> Control (CPPC) on ACPI based RISC-V platforms. It depends on the
> encoding of CPPC registers as defined in RISC-V FFH spec [2].
>
> CPPC is described in the ACPI spec [1]. RISC-V FFH spec required to
> enable this, is available at [2].
>
> [...]
Here is the summary with links:
- [v1,-next,1/3] ACPI: RISC-V: Add CPPC driver
https://git.kernel.org/riscv/c/30f3ffbee86b
- [v1,-next,2/3] cpufreq: Move CPPC configs to common Kconfig and add RISC-V
https://git.kernel.org/riscv/c/7ee1378736f0
- [v1,-next,3/3] RISC-V: defconfig: Enable CONFIG_ACPI_CPPC_CPUFREQ
https://git.kernel.org/riscv/c/282b9df4e960
You are awesome, thank you!
--
Deet-doot-dot, I am a bot.
https://korg.docs.kernel.org/patchwork/pwbot.html
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v1 -next 0/3] RISC-V: ACPI: Enable CPPC based cpufreq support
@ 2024-03-20 20:50 ` patchwork-bot+linux-riscv
0 siblings, 0 replies; 32+ messages in thread
From: patchwork-bot+linux-riscv @ 2024-03-20 20:50 UTC (permalink / raw
To: Sunil V L
Cc: linux-riscv, linux-acpi, linux-kernel, apatel, aou, rafael,
viresh.kumar, atishp, conor.dooley, palmer, paul.walmsley, ajones,
lenb
Hello:
This series was applied to riscv/linux.git (for-next)
by Palmer Dabbelt <palmer@rivosinc.com>:
On Thu, 8 Feb 2024 09:14:11 +0530 you wrote:
> This series enables the support for "Collaborative Processor Performance
> Control (CPPC) on ACPI based RISC-V platforms. It depends on the
> encoding of CPPC registers as defined in RISC-V FFH spec [2].
>
> CPPC is described in the ACPI spec [1]. RISC-V FFH spec required to
> enable this, is available at [2].
>
> [...]
Here is the summary with links:
- [v1,-next,1/3] ACPI: RISC-V: Add CPPC driver
https://git.kernel.org/riscv/c/30f3ffbee86b
- [v1,-next,2/3] cpufreq: Move CPPC configs to common Kconfig and add RISC-V
https://git.kernel.org/riscv/c/7ee1378736f0
- [v1,-next,3/3] RISC-V: defconfig: Enable CONFIG_ACPI_CPPC_CPUFREQ
https://git.kernel.org/riscv/c/282b9df4e960
You are awesome, thank you!
--
Deet-doot-dot, I am a bot.
https://korg.docs.kernel.org/patchwork/pwbot.html
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v1 -next 0/3] RISC-V: ACPI: Enable CPPC based cpufreq support
2024-03-19 10:20 ` Sunil V L
@ 2024-03-21 4:12 ` Drew Fustini
-1 siblings, 0 replies; 32+ messages in thread
From: Drew Fustini @ 2024-03-21 4:12 UTC (permalink / raw
To: Sunil V L
Cc: linux-riscv, linux-acpi, linux-kernel, Rafael J . Wysocki,
Len Brown, Paul Walmsley, Palmer Dabbelt, Albert Ou, Viresh Kumar,
Conor Dooley, Andrew Jones, Atish Kumar Patra, Anup Patel
On Tue, Mar 19, 2024 at 03:50:21PM +0530, Sunil V L wrote:
> On Mon, Mar 18, 2024 at 07:27:34PM -0700, Drew Fustini wrote:
> > On Mon, Mar 18, 2024 at 11:40:34AM -0700, Drew Fustini wrote:
> > > On Thu, Feb 08, 2024 at 09:14:11AM +0530, Sunil V L wrote:
> > > > This series enables the support for "Collaborative Processor Performance
> > > > Control (CPPC) on ACPI based RISC-V platforms. It depends on the
> > > > encoding of CPPC registers as defined in RISC-V FFH spec [2].
> > > >
> > > > CPPC is described in the ACPI spec [1]. RISC-V FFH spec required to
> > > > enable this, is available at [2].
> > > >
> > > > [1] - https://uefi.org/specs/ACPI/6.5/08_Processor_Configuration_and_Control.html#collaborative-processor-performance-control
> > > > [2] - https://github.com/riscv-non-isa/riscv-acpi-ffh/releases/download/v1.0.0/riscv-ffh.pdf
> > > >
> > > > The series is based on the LPI support series.
> > > > Based-on: 20240118062930.245937-1-sunilvl@ventanamicro.com
> > > > (https://lore.kernel.org/lkml/20240118062930.245937-1-sunilvl@ventanamicro.com/)
> > >
> > > Should the https://github.com/vlsunil/qemu/tree/lpi_exp branch also be
> > > used for this CPPC series too?
> >
> > I noticed the ventanamicro qemu repo has a dev-upstream branch [1] which
> > contains 4bb6ba4d0fb9 ("riscv/virt: acpi: Enable CPPC - _CPC and _PSD").
> > I've built that but I still see 'SBI CPPC extension NOT detected!!' in
> > the Linux boot log.
> >
> > I'm using upstream opensbi. It seems that sbi_cppc_probe() fails because
> > cppc_dev is not set. Nothing in the upstream opensbi repo seems to call
> > sbi_cppc_set_device(), so I am uncertain how it is possible for it to
> > work. Is there an opensbi branch I should be using?
> >
> > Thanks,
> > Drew
> >
> > [1] https://github.com/ventanamicro/qemu/tree/dev-upstream
>
> Please use below branches for qemu and opensbi. These are just dummy
> objects/interfaces added to test the kernel change which are otherwise
> platform specific features.
>
> https://github.com/vlsunil/qemu/tree/lpi_cppc_exp
> https://github.com/vlsunil/opensbi/tree/cppc_exp
I know the opensbi branch is just for the purpose of testing the kernel
driver. However, I am new to ACPI and I am trying to understand how a
real system might work.
The _CPC register address encoding in the RISC-V FFH spec enables the
SBI CPPC register ID to be specified. But how would SBI firmware know
what physical address corresponds to the CPPC register?
If sbi_cppc_test_write() [1] was implemented for a real system, then how
would it know what physical address to write to for a CPPC register like
SBI_CPPC_DESIRED_PERF?
Thanks,
Drew
[1] https://github.com/vlsunil/opensbi/commit/e23cda47158626f96e5992db00efaaac5dab31b0
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v1 -next 0/3] RISC-V: ACPI: Enable CPPC based cpufreq support
@ 2024-03-21 4:12 ` Drew Fustini
0 siblings, 0 replies; 32+ messages in thread
From: Drew Fustini @ 2024-03-21 4:12 UTC (permalink / raw
To: Sunil V L
Cc: linux-riscv, linux-acpi, linux-kernel, Rafael J . Wysocki,
Len Brown, Paul Walmsley, Palmer Dabbelt, Albert Ou, Viresh Kumar,
Conor Dooley, Andrew Jones, Atish Kumar Patra, Anup Patel
On Tue, Mar 19, 2024 at 03:50:21PM +0530, Sunil V L wrote:
> On Mon, Mar 18, 2024 at 07:27:34PM -0700, Drew Fustini wrote:
> > On Mon, Mar 18, 2024 at 11:40:34AM -0700, Drew Fustini wrote:
> > > On Thu, Feb 08, 2024 at 09:14:11AM +0530, Sunil V L wrote:
> > > > This series enables the support for "Collaborative Processor Performance
> > > > Control (CPPC) on ACPI based RISC-V platforms. It depends on the
> > > > encoding of CPPC registers as defined in RISC-V FFH spec [2].
> > > >
> > > > CPPC is described in the ACPI spec [1]. RISC-V FFH spec required to
> > > > enable this, is available at [2].
> > > >
> > > > [1] - https://uefi.org/specs/ACPI/6.5/08_Processor_Configuration_and_Control.html#collaborative-processor-performance-control
> > > > [2] - https://github.com/riscv-non-isa/riscv-acpi-ffh/releases/download/v1.0.0/riscv-ffh.pdf
> > > >
> > > > The series is based on the LPI support series.
> > > > Based-on: 20240118062930.245937-1-sunilvl@ventanamicro.com
> > > > (https://lore.kernel.org/lkml/20240118062930.245937-1-sunilvl@ventanamicro.com/)
> > >
> > > Should the https://github.com/vlsunil/qemu/tree/lpi_exp branch also be
> > > used for this CPPC series too?
> >
> > I noticed the ventanamicro qemu repo has a dev-upstream branch [1] which
> > contains 4bb6ba4d0fb9 ("riscv/virt: acpi: Enable CPPC - _CPC and _PSD").
> > I've built that but I still see 'SBI CPPC extension NOT detected!!' in
> > the Linux boot log.
> >
> > I'm using upstream opensbi. It seems that sbi_cppc_probe() fails because
> > cppc_dev is not set. Nothing in the upstream opensbi repo seems to call
> > sbi_cppc_set_device(), so I am uncertain how it is possible for it to
> > work. Is there an opensbi branch I should be using?
> >
> > Thanks,
> > Drew
> >
> > [1] https://github.com/ventanamicro/qemu/tree/dev-upstream
>
> Please use below branches for qemu and opensbi. These are just dummy
> objects/interfaces added to test the kernel change which are otherwise
> platform specific features.
>
> https://github.com/vlsunil/qemu/tree/lpi_cppc_exp
> https://github.com/vlsunil/opensbi/tree/cppc_exp
I know the opensbi branch is just for the purpose of testing the kernel
driver. However, I am new to ACPI and I am trying to understand how a
real system might work.
The _CPC register address encoding in the RISC-V FFH spec enables the
SBI CPPC register ID to be specified. But how would SBI firmware know
what physical address corresponds to the CPPC register?
If sbi_cppc_test_write() [1] was implemented for a real system, then how
would it know what physical address to write to for a CPPC register like
SBI_CPPC_DESIRED_PERF?
Thanks,
Drew
[1] https://github.com/vlsunil/opensbi/commit/e23cda47158626f96e5992db00efaaac5dab31b0
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v1 -next 0/3] RISC-V: ACPI: Enable CPPC based cpufreq support
2024-03-21 4:12 ` Drew Fustini
@ 2024-03-21 5:49 ` Sunil V L
-1 siblings, 0 replies; 32+ messages in thread
From: Sunil V L @ 2024-03-21 5:49 UTC (permalink / raw
To: Drew Fustini
Cc: linux-riscv, linux-acpi, linux-kernel, Rafael J . Wysocki,
Len Brown, Paul Walmsley, Palmer Dabbelt, Albert Ou, Viresh Kumar,
Conor Dooley, Andrew Jones, Atish Kumar Patra, Anup Patel
On Wed, Mar 20, 2024 at 09:12:11PM -0700, Drew Fustini wrote:
> On Tue, Mar 19, 2024 at 03:50:21PM +0530, Sunil V L wrote:
> > On Mon, Mar 18, 2024 at 07:27:34PM -0700, Drew Fustini wrote:
> > > On Mon, Mar 18, 2024 at 11:40:34AM -0700, Drew Fustini wrote:
> > > > On Thu, Feb 08, 2024 at 09:14:11AM +0530, Sunil V L wrote:
> > > > > This series enables the support for "Collaborative Processor Performance
> > > > > Control (CPPC) on ACPI based RISC-V platforms. It depends on the
> > > > > encoding of CPPC registers as defined in RISC-V FFH spec [2].
> > > > >
> > > > > CPPC is described in the ACPI spec [1]. RISC-V FFH spec required to
> > > > > enable this, is available at [2].
> > > > >
> > > > > [1] - https://uefi.org/specs/ACPI/6.5/08_Processor_Configuration_and_Control.html#collaborative-processor-performance-control
> > > > > [2] - https://github.com/riscv-non-isa/riscv-acpi-ffh/releases/download/v1.0.0/riscv-ffh.pdf
> > > > >
> > > > > The series is based on the LPI support series.
> > > > > Based-on: 20240118062930.245937-1-sunilvl@ventanamicro.com
> > > > > (https://lore.kernel.org/lkml/20240118062930.245937-1-sunilvl@ventanamicro.com/)
> > > >
> > > > Should the https://github.com/vlsunil/qemu/tree/lpi_exp branch also be
> > > > used for this CPPC series too?
> > >
> > > I noticed the ventanamicro qemu repo has a dev-upstream branch [1] which
> > > contains 4bb6ba4d0fb9 ("riscv/virt: acpi: Enable CPPC - _CPC and _PSD").
> > > I've built that but I still see 'SBI CPPC extension NOT detected!!' in
> > > the Linux boot log.
> > >
> > > I'm using upstream opensbi. It seems that sbi_cppc_probe() fails because
> > > cppc_dev is not set. Nothing in the upstream opensbi repo seems to call
> > > sbi_cppc_set_device(), so I am uncertain how it is possible for it to
> > > work. Is there an opensbi branch I should be using?
> > >
> > > Thanks,
> > > Drew
> > >
> > > [1] https://github.com/ventanamicro/qemu/tree/dev-upstream
> >
> > Please use below branches for qemu and opensbi. These are just dummy
> > objects/interfaces added to test the kernel change which are otherwise
> > platform specific features.
> >
> > https://github.com/vlsunil/qemu/tree/lpi_cppc_exp
> > https://github.com/vlsunil/opensbi/tree/cppc_exp
>
> I know the opensbi branch is just for the purpose of testing the kernel
> driver. However, I am new to ACPI and I am trying to understand how a
> real system might work.
>
> The _CPC register address encoding in the RISC-V FFH spec enables the
> SBI CPPC register ID to be specified. But how would SBI firmware know
> what physical address corresponds to the CPPC register?
>
> If sbi_cppc_test_write() [1] was implemented for a real system, then how
> would it know what physical address to write to for a CPPC register like
> SBI_CPPC_DESIRED_PERF?
>
The SBI extension provides an abstraction to access the CPPC registers.
SBI implementation for the platform should be aware of how to access a
particular register in the back end when it supports the extension.
Regards,
Sunil
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v1 -next 0/3] RISC-V: ACPI: Enable CPPC based cpufreq support
@ 2024-03-21 5:49 ` Sunil V L
0 siblings, 0 replies; 32+ messages in thread
From: Sunil V L @ 2024-03-21 5:49 UTC (permalink / raw
To: Drew Fustini
Cc: linux-riscv, linux-acpi, linux-kernel, Rafael J . Wysocki,
Len Brown, Paul Walmsley, Palmer Dabbelt, Albert Ou, Viresh Kumar,
Conor Dooley, Andrew Jones, Atish Kumar Patra, Anup Patel
On Wed, Mar 20, 2024 at 09:12:11PM -0700, Drew Fustini wrote:
> On Tue, Mar 19, 2024 at 03:50:21PM +0530, Sunil V L wrote:
> > On Mon, Mar 18, 2024 at 07:27:34PM -0700, Drew Fustini wrote:
> > > On Mon, Mar 18, 2024 at 11:40:34AM -0700, Drew Fustini wrote:
> > > > On Thu, Feb 08, 2024 at 09:14:11AM +0530, Sunil V L wrote:
> > > > > This series enables the support for "Collaborative Processor Performance
> > > > > Control (CPPC) on ACPI based RISC-V platforms. It depends on the
> > > > > encoding of CPPC registers as defined in RISC-V FFH spec [2].
> > > > >
> > > > > CPPC is described in the ACPI spec [1]. RISC-V FFH spec required to
> > > > > enable this, is available at [2].
> > > > >
> > > > > [1] - https://uefi.org/specs/ACPI/6.5/08_Processor_Configuration_and_Control.html#collaborative-processor-performance-control
> > > > > [2] - https://github.com/riscv-non-isa/riscv-acpi-ffh/releases/download/v1.0.0/riscv-ffh.pdf
> > > > >
> > > > > The series is based on the LPI support series.
> > > > > Based-on: 20240118062930.245937-1-sunilvl@ventanamicro.com
> > > > > (https://lore.kernel.org/lkml/20240118062930.245937-1-sunilvl@ventanamicro.com/)
> > > >
> > > > Should the https://github.com/vlsunil/qemu/tree/lpi_exp branch also be
> > > > used for this CPPC series too?
> > >
> > > I noticed the ventanamicro qemu repo has a dev-upstream branch [1] which
> > > contains 4bb6ba4d0fb9 ("riscv/virt: acpi: Enable CPPC - _CPC and _PSD").
> > > I've built that but I still see 'SBI CPPC extension NOT detected!!' in
> > > the Linux boot log.
> > >
> > > I'm using upstream opensbi. It seems that sbi_cppc_probe() fails because
> > > cppc_dev is not set. Nothing in the upstream opensbi repo seems to call
> > > sbi_cppc_set_device(), so I am uncertain how it is possible for it to
> > > work. Is there an opensbi branch I should be using?
> > >
> > > Thanks,
> > > Drew
> > >
> > > [1] https://github.com/ventanamicro/qemu/tree/dev-upstream
> >
> > Please use below branches for qemu and opensbi. These are just dummy
> > objects/interfaces added to test the kernel change which are otherwise
> > platform specific features.
> >
> > https://github.com/vlsunil/qemu/tree/lpi_cppc_exp
> > https://github.com/vlsunil/opensbi/tree/cppc_exp
>
> I know the opensbi branch is just for the purpose of testing the kernel
> driver. However, I am new to ACPI and I am trying to understand how a
> real system might work.
>
> The _CPC register address encoding in the RISC-V FFH spec enables the
> SBI CPPC register ID to be specified. But how would SBI firmware know
> what physical address corresponds to the CPPC register?
>
> If sbi_cppc_test_write() [1] was implemented for a real system, then how
> would it know what physical address to write to for a CPPC register like
> SBI_CPPC_DESIRED_PERF?
>
The SBI extension provides an abstraction to access the CPPC registers.
SBI implementation for the platform should be aware of how to access a
particular register in the back end when it supports the extension.
Regards,
Sunil
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 32+ messages in thread
end of thread, other threads:[~2024-03-21 5:50 UTC | newest]
Thread overview: 32+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2024-02-08 3:44 [PATCH v1 -next 0/3] RISC-V: ACPI: Enable CPPC based cpufreq support Sunil V L
2024-02-08 3:44 ` Sunil V L
2024-02-08 3:44 ` [PATCH v1 -next 1/3] ACPI: RISC-V: Add CPPC driver Sunil V L
2024-02-08 3:44 ` Sunil V L
2024-02-08 3:44 ` [PATCH v1 -next 2/3] cpufreq: Move CPPC configs to common Kconfig and add RISC-V Sunil V L
2024-02-08 3:44 ` Sunil V L
2024-02-13 6:14 ` Viresh Kumar
2024-02-13 6:14 ` Viresh Kumar
2024-02-08 3:44 ` [PATCH v1 -next 3/3] RISC-V: defconfig: Enable CONFIG_ACPI_CPPC_CPUFREQ Sunil V L
2024-02-08 3:44 ` Sunil V L
2024-02-09 11:11 ` [PATCH v1 -next 0/3] RISC-V: ACPI: Enable CPPC based cpufreq support Pierre Gondois
2024-02-09 11:11 ` Pierre Gondois
2024-02-15 11:27 ` Sudeep Holla
2024-02-15 11:27 ` Sudeep Holla
2024-02-12 15:24 ` Rafael J. Wysocki
2024-02-12 15:24 ` Rafael J. Wysocki
2024-02-13 6:15 ` Viresh Kumar
2024-02-13 6:15 ` Viresh Kumar
2024-03-18 18:40 ` Drew Fustini
2024-03-18 18:40 ` Drew Fustini
2024-03-19 2:27 ` Drew Fustini
2024-03-19 2:27 ` Drew Fustini
2024-03-19 10:20 ` Sunil V L
2024-03-19 10:20 ` Sunil V L
2024-03-20 6:54 ` Drew Fustini
2024-03-20 6:54 ` Drew Fustini
2024-03-21 4:12 ` Drew Fustini
2024-03-21 4:12 ` Drew Fustini
2024-03-21 5:49 ` Sunil V L
2024-03-21 5:49 ` Sunil V L
2024-03-20 20:50 ` patchwork-bot+linux-riscv
2024-03-20 20:50 ` patchwork-bot+linux-riscv
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