From mboxrd@z Thu Jan  1 00:00:00 1970
From: Stefano Stabellini <stefano.stabellini@eu.citrix.com>
Subject: Re: [PATCH 3/6] xen/MSI-X: really enforce alignment
Date: Tue, 16 Jun 2015 15:08:47 +0100
Message-ID: <alpine.DEB.2.02.1506161505030.21829__24658.3135486164$1434464002$gmane$org@kaball.uk.xensource.com>
References: <5571AA3B020000780008152E@mail.emea.novell.com>
	<5571AC000200007800081567@mail.emea.novell.com>
Mime-Version: 1.0
Content-Type: text/plain; charset="us-ascii"
Content-Transfer-Encoding: 7bit
Return-path: <xen-devel-bounces@lists.xen.org>
Received: from mail6.bemta5.messagelabs.com ([195.245.231.135])
	by lists.xen.org with esmtp (Exim 4.72)
	(envelope-from <prvs=6027ea2fc=Stefano.Stabellini@citrix.com>)
	id 1Z4raA-0003Kp-Bk
	for xen-devel@lists.xenproject.org; Tue, 16 Jun 2015 14:11:18 +0000
In-Reply-To: <5571AC000200007800081567@mail.emea.novell.com>
List-Unsubscribe: <http://lists.xen.org/cgi-bin/mailman/options/xen-devel>,
	<mailto:xen-devel-request@lists.xen.org?subject=unsubscribe>
List-Post: <mailto:xen-devel@lists.xen.org>
List-Help: <mailto:xen-devel-request@lists.xen.org?subject=help>
List-Subscribe: <http://lists.xen.org/cgi-bin/mailman/listinfo/xen-devel>,
	<mailto:xen-devel-request@lists.xen.org?subject=subscribe>
Sender: xen-devel-bounces@lists.xen.org
Errors-To: xen-devel-bounces@lists.xen.org
To: Jan Beulich <JBeulich@suse.com>
Cc: xen-devel <xen-devel@lists.xenproject.org>, qemu-devel@nongnu.org, Stefano Stabellini <stefano.stabellini@eu.citrix.com>
List-Id: xen-devel@lists.xenproject.org

On Fri, 5 Jun 2015, Jan Beulich wrote:
> The way the generic infrastructure works the intention of not allowing
> unaligned accesses can't be achieved by simply setting .unaligned to
> false. The benefit is that we can now replace the conditionals in
> {get,set}_entry_value() by assert()-s.
> 
> Signed-off-by: Jan Beulich <jbeulich@suse.com>

Reviewed-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com>


> --- a/qemu/upstream/hw/xen/xen_pt_msi.c
> +++ b/qemu/upstream/hw/xen/xen_pt_msi.c
> @@ -421,16 +421,14 @@ int xen_pt_msix_update_remap(XenPCIPasst
>  
>  static uint32_t get_entry_value(XenPTMSIXEntry *e, int offset)
>  {
> -    return !(offset % sizeof(*e->latch))
> -           ? e->latch[offset / sizeof(*e->latch)] : 0;
> +    assert(!(offset % sizeof(*e->latch)));
> +    return e->latch[offset / sizeof(*e->latch)];
>  }
>  
>  static void set_entry_value(XenPTMSIXEntry *e, int offset, uint32_t val)
>  {
> -    if (!(offset % sizeof(*e->latch)))
> -    {
> -        e->latch[offset / sizeof(*e->latch)] = val;
> -    }
> +    assert(!(offset % sizeof(*e->latch)));
> +    e->latch[offset / sizeof(*e->latch)] = val;
>  }
>  
>  static void pci_msix_write(void *opaque, hwaddr addr,
> @@ -496,6 +494,12 @@ static uint64_t pci_msix_read(void *opaq
>      }
>  }
>  
> +static bool pci_msix_accepts(void *opaque, hwaddr addr,
> +                             unsigned size, bool is_write)
> +{
> +    return !(addr & (size - 1));
> +}
> +
>  static const MemoryRegionOps pci_msix_ops = {
>      .read = pci_msix_read,
>      .write = pci_msix_write,
> @@ -504,7 +508,13 @@ static const MemoryRegionOps pci_msix_op
>          .min_access_size = 4,
>          .max_access_size = 4,
>          .unaligned = false,
> +        .accepts = pci_msix_accepts
>      },
> +    .impl = {
> +        .min_access_size = 4,
> +        .max_access_size = 4,
> +        .unaligned = false
> +    }
>  };
>  
>  int xen_pt_msix_init(XenPCIPassthroughState *s, uint32_t base)
> 
> 
> 
>