* [PATCH u-boot-marvell] ARM: mvebu: a38x: sync ddr training code with mv_ddr-armada-14.0.0
@ 2021-02-08 16:04 Marek Behún
2021-02-08 16:24 ` Stefan Roese
0 siblings, 1 reply; 3+ messages in thread
From: Marek Behún @ 2021-02-08 16:04 UTC (permalink / raw
To: u-boot
This syncs drivers/ddr/marvell/a38x/ with the mv-ddr-devel branch
of https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git.
Specifically this syncs with commit fae3f6c98230 ("Bump mv_ddr to
release 14.0.0").
There is a new version numbering system, where after 18.12.0 came
1.0.0, 2.0.0, and so on until 14.0.0. So 14.0.0 is newer than 18.12.0.
There are some commits regarding DDR3 on top of version 14.0.0 in the
mv-ddr-marvell repository (from Chris Packham), but these changes
already are in U-Boot.
The complete log of changes is best obtained from the mv-ddr-marvell.git
repository but some relevant highlights are:
ddr3: allow board specific ODT configuration
mv_ddr: add 16Gbit memory devices support
mv_ddr: add support for twin-die combined memory device
mv_ddr: a38x: disable WL phase correction stage in case of bus_width=16bit
mv_ddr: a38x : fix memory cs size function
The default value for new option twin_die_combined is set to
NOT_COMBINED for all boards, as this was default behaviour prior this
change.
Signed-off-by: Marek Beh?n <marek.behun@nic.cz>
Cc: Chris Packham <judge.packham@gmail.com>
Cc: Chris Packham <chris.packham@alliedtelesis.co.nz>
Cc: Stefan Roese <sr@denx.de>
Cc: Baruch Siach <baruch@tkos.co.il>
Cc: Pavol Roh?r <pali@kernel.org>
---
board/CZ.NIC/turris_omnia/turris_omnia.c | 2 ++
board/Marvell/db-88f6820-amc/db-88f6820-amc.c | 1 +
board/Marvell/db-88f6820-gp/db-88f6820-gp.c | 1 +
board/alliedtelesis/x530/x530.c | 1 +
board/gdsys/a38x/controlcenterdc.c | 1 +
board/kobol/helios4/helios4.c | 1 +
board/solidrun/clearfog/clearfog.c | 1 +
drivers/ddr/marvell/a38x/ddr3_init.c | 5 ++++
drivers/ddr/marvell/a38x/ddr3_init.h | 2 +-
drivers/ddr/marvell/a38x/ddr3_training.c | 5 +++-
drivers/ddr/marvell/a38x/ddr3_training_db.c | 3 +++
.../ddr/marvell/a38x/ddr3_training_ip_def.h | 2 ++
.../marvell/a38x/ddr3_training_ip_engine.c | 5 +++-
drivers/ddr/marvell/a38x/ddr_topology_def.h | 23 ++++++++++++++++++-
.../ddr/marvell/a38x/mv_ddr_build_message.c | 2 +-
drivers/ddr/marvell/a38x/mv_ddr_plat.c | 9 ++++++--
drivers/ddr/marvell/a38x/mv_ddr_topology.c | 14 ++++++++---
drivers/ddr/marvell/a38x/mv_ddr_topology.h | 2 ++
drivers/ddr/marvell/a38x/xor.c | 6 ++---
19 files changed, 73 insertions(+), 13 deletions(-)
diff --git a/board/CZ.NIC/turris_omnia/turris_omnia.c b/board/CZ.NIC/turris_omnia/turris_omnia.c
index 2da878d364..78b125edfe 100644
--- a/board/CZ.NIC/turris_omnia/turris_omnia.c
+++ b/board/CZ.NIC/turris_omnia/turris_omnia.c
@@ -285,6 +285,7 @@ static struct mv_ddr_topology_map board_topology_map_1g = {
MV_DDR_TIM_2T} }, /* timing */
BUS_MASK_32BIT, /* Busses mask */
MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
+ NOT_COMBINED, /* ddr twin-die combined */
{ {0} }, /* raw spd data */
{0} /* timing parameters */
};
@@ -307,6 +308,7 @@ static struct mv_ddr_topology_map board_topology_map_2g = {
MV_DDR_TIM_2T} }, /* timing */
BUS_MASK_32BIT, /* Busses mask */
MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
+ NOT_COMBINED, /* ddr twin-die combined */
{ {0} }, /* raw spd data */
{0} /* timing parameters */
};
diff --git a/board/Marvell/db-88f6820-amc/db-88f6820-amc.c b/board/Marvell/db-88f6820-amc/db-88f6820-amc.c
index 9cd9ea2c06..acc8a5ec6d 100644
--- a/board/Marvell/db-88f6820-amc/db-88f6820-amc.c
+++ b/board/Marvell/db-88f6820-amc/db-88f6820-amc.c
@@ -72,6 +72,7 @@ static struct mv_ddr_topology_map board_topology_map = {
MV_DDR_TIM_DEFAULT} }, /* timing */
BUS_MASK_32BIT, /* Busses mask */
MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
+ NOT_COMBINED, /* ddr twin-die combined */
{ {0} }, /* raw spd data */
{0} /* timing parameters */
};
diff --git a/board/Marvell/db-88f6820-gp/db-88f6820-gp.c b/board/Marvell/db-88f6820-gp/db-88f6820-gp.c
index 2bdd55329d..a1d0104526 100644
--- a/board/Marvell/db-88f6820-gp/db-88f6820-gp.c
+++ b/board/Marvell/db-88f6820-gp/db-88f6820-gp.c
@@ -93,6 +93,7 @@ static struct mv_ddr_topology_map board_topology_map = {
MV_DDR_TIM_DEFAULT} }, /* timing */
BUS_MASK_32BIT, /* Busses mask */
MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
+ NOT_COMBINED, /* ddr twin-die combined */
{ {0} }, /* raw spd data */
{0} /* timing parameters */
};
diff --git a/board/alliedtelesis/x530/x530.c b/board/alliedtelesis/x530/x530.c
index c7438aeaf1..6caba24196 100644
--- a/board/alliedtelesis/x530/x530.c
+++ b/board/alliedtelesis/x530/x530.c
@@ -67,6 +67,7 @@ static struct mv_ddr_topology_map board_topology_map = {
MV_DDR_TIM_2T} }, /* timing */
BUS_MASK_32BIT_ECC, /* subphys mask */
MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
+ NOT_COMBINED, /* ddr twin-die combined */
{ {0} }, /* raw spd data */
{0}, /* timing parameters */
{ {0} }, /* electrical configuration */
diff --git a/board/gdsys/a38x/controlcenterdc.c b/board/gdsys/a38x/controlcenterdc.c
index a2287f9deb..66a0d769ce 100644
--- a/board/gdsys/a38x/controlcenterdc.c
+++ b/board/gdsys/a38x/controlcenterdc.c
@@ -70,6 +70,7 @@ static struct mv_ddr_topology_map ddr_topology_map = {
MV_DDR_TIM_DEFAULT} }, /* timing */
BUS_MASK_32BIT, /* Busses mask */
MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
+ NOT_COMBINED, /* ddr twin-die combined */
{ {0} }, /* raw spd data */
{0} /* timing parameters */
diff --git a/board/kobol/helios4/helios4.c b/board/kobol/helios4/helios4.c
index 17d2489415..5007194a52 100644
--- a/board/kobol/helios4/helios4.c
+++ b/board/kobol/helios4/helios4.c
@@ -70,6 +70,7 @@ static struct mv_ddr_topology_map board_topology_map = {
MV_DDR_TIM_DEFAULT} }, /* timing */
BUS_MASK_32BIT_ECC, /* Busses mask */
MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
+ NOT_COMBINED, /* ddr twin-die combined */
{ {0} }, /* raw spd data */
{0} /* timing parameters */
};
diff --git a/board/solidrun/clearfog/clearfog.c b/board/solidrun/clearfog/clearfog.c
index 92443d5177..3166f0abe0 100644
--- a/board/solidrun/clearfog/clearfog.c
+++ b/board/solidrun/clearfog/clearfog.c
@@ -141,6 +141,7 @@ static struct mv_ddr_topology_map board_topology_map = {
MV_DDR_TIM_DEFAULT} }, /* timing */
BUS_MASK_32BIT, /* Busses mask */
MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
+ NOT_COMBINED, /* ddr twin-die combined */
{ {0} }, /* raw spd data */
{0}, /* timing parameters */
{ {0} }, /* electrical configuration */
diff --git a/drivers/ddr/marvell/a38x/ddr3_init.c b/drivers/ddr/marvell/a38x/ddr3_init.c
index a971cc155a..7488770268 100644
--- a/drivers/ddr/marvell/a38x/ddr3_init.c
+++ b/drivers/ddr/marvell/a38x/ddr3_init.c
@@ -104,6 +104,7 @@ int ddr3_init(void)
static int mv_ddr_training_params_set(u8 dev_num)
{
struct tune_train_params params;
+ struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
int status;
u32 cs_num;
int ck_delay;
@@ -136,6 +137,10 @@ static int mv_ddr_training_params_set(u8 dev_num)
if (ck_delay > 0)
params.ck_delay = ck_delay;
+ /* Use platform specific override ODT value */
+ if (tm->odt_config)
+ params.g_odt_config = tm->odt_config;
+
status = ddr3_tip_tune_training_params(dev_num, ¶ms);
if (MV_OK != status) {
printf("%s Training Sequence - FAILED\n", ddr_type);
diff --git a/drivers/ddr/marvell/a38x/ddr3_training.c b/drivers/ddr/marvell/a38x/ddr3_training.c
index 34cc170910..2b3af23202 100644
--- a/drivers/ddr/marvell/a38x/ddr3_training.c
+++ b/drivers/ddr/marvell/a38x/ddr3_training.c
@@ -143,6 +143,7 @@ static struct reg_data odpg_default_value[] = {
{0x15a4, 0x0, MASK_ALL_BITS},
{0x15a8, 0x0, MASK_ALL_BITS},
{0x15ac, 0x0, MASK_ALL_BITS},
+ {0x1600, 0x0, MASK_ALL_BITS},
{0x1604, 0x0, MASK_ALL_BITS},
{0x1608, 0x0, MASK_ALL_BITS},
{0x160c, 0x0, MASK_ALL_BITS},
@@ -218,7 +219,7 @@ static int ddr3_tip_pad_inv(void)
DDR_PHY_CONTROL,
PHY_CTRL_PHY_REG,
data, data);
-#else /* !CONFIG_ARMADA_38X && !CONFIG_ARMADA_39X && !A70X0 && !A80X0 && !A3900 */
+#else /* !CONFIG_ARMADA_38X && !CONFIG_ARMADA_39X */
#pragma message "unknown platform to configure ddr clock swap"
#endif
}
@@ -1569,6 +1570,8 @@ int ddr3_tip_freq_set(u32 dev_num, enum hws_access_type access_type,
val = ((cl_mask_table[cl_value] & 0x1) << 2) |
((cl_mask_table[cl_value] & 0xe) << 3);
+ cs_mask[0] = 0xc;
+
CHECK_STATUS(ddr3_tip_write_mrs_cmd(dev_num, cs_mask, MR_CMD0,
val, (0x7 << 4) | (0x1 << 2)));
diff --git a/drivers/ddr/marvell/a38x/ddr3_training_db.c b/drivers/ddr/marvell/a38x/ddr3_training_db.c
index b2f11a8399..6aa7b6069e 100644
--- a/drivers/ddr/marvell/a38x/ddr3_training_db.c
+++ b/drivers/ddr/marvell/a38x/ddr3_training_db.c
@@ -833,6 +833,9 @@ u32 pattern_table_get_word(u32 dev_num, enum hws_pattern type, u8 index)
pattern = pattern_table_get_isi_word16(index);
break;
default:
+ if (((int)type == 29) || ((int)type == 30))
+ break;
+
printf("error: %s: unsupported pattern type [%d] found\n",
__func__, (int)type);
pattern = 0;
diff --git a/drivers/ddr/marvell/a38x/ddr3_training_ip_def.h b/drivers/ddr/marvell/a38x/ddr3_training_ip_def.h
index 2a68669f36..8765df7cfb 100644
--- a/drivers/ddr/marvell/a38x/ddr3_training_ip_def.h
+++ b/drivers/ddr/marvell/a38x/ddr3_training_ip_def.h
@@ -80,6 +80,8 @@
#define ADDR_SIZE_2GB 0x10000000
#define ADDR_SIZE_4GB 0x20000000
#define ADDR_SIZE_8GB 0x40000000
+#define ADDR_SIZE_16GB 0x80000000
+
enum hws_edge_compare {
EDGE_PF,
diff --git a/drivers/ddr/marvell/a38x/ddr3_training_ip_engine.c b/drivers/ddr/marvell/a38x/ddr3_training_ip_engine.c
index 979f3530b7..5fd9a052fa 100644
--- a/drivers/ddr/marvell/a38x/ddr3_training_ip_engine.c
+++ b/drivers/ddr/marvell/a38x/ddr3_training_ip_engine.c
@@ -864,8 +864,11 @@ int ddr3_tip_load_all_pattern_to_mem(u32 dev_num)
DUAL_DUNIT_CFG_REG, (1 << 3), (1 << 3)));
}
- for (pattern = 0; pattern < PATTERN_LAST; pattern++)
+ for (pattern = 0; pattern < PATTERN_LAST; pattern++) {
+ if (pattern == PATTERN_TEST)
+ continue;
ddr3_tip_load_pattern_to_mem(dev_num, pattern);
+ }
return MV_OK;
}
diff --git a/drivers/ddr/marvell/a38x/ddr_topology_def.h b/drivers/ddr/marvell/a38x/ddr_topology_def.h
index 34196b1662..2cca5676a0 100644
--- a/drivers/ddr/marvell/a38x/ddr_topology_def.h
+++ b/drivers/ddr/marvell/a38x/ddr_topology_def.h
@@ -14,6 +14,11 @@
#define MV_DDR_MAX_BUS_NUM 9
#define MV_DDR_MAX_IFACE_NUM 1
+enum mv_ddr_twin_die {
+ NOT_COMBINED,
+ COMBINED,
+};
+
struct bus_params {
/* Chip Select (CS) bitmask (bits 0-CS0, bit 1- CS1 ...) */
u8 cs_bitmask;
@@ -113,6 +118,9 @@ struct mv_ddr_topology_map {
/* source of ddr configuration data */
enum mv_ddr_cfg_src cfg_src;
+ /* ddr twin-die */
+ enum mv_ddr_twin_die twin_die_combined;
+
/* raw spd data */
union mv_ddr_spd_data spd_data;
@@ -125,6 +133,9 @@ struct mv_ddr_topology_map {
/* electrical parameters */
unsigned int electrical_data[MV_DDR_EDATA_LAST];
+ /* ODT configuration */
+ u32 odt_config;
+
/* Clock enable mask */
u32 clk_enable;
@@ -148,7 +159,13 @@ enum mv_ddr_validation {
MV_DDR_VAL_DIS,
MV_DDR_VAL_RX,
MV_DDR_VAL_TX,
- MV_DDR_VAL_RX_TX
+ MV_DDR_VAL_RX_TX,
+ MV_DDR_MEMORY_CHECK
+};
+
+enum mv_ddr_sscg {
+ SSCG_EN,
+ SSCG_DIS,
};
struct mv_ddr_iface {
@@ -179,8 +196,12 @@ struct mv_ddr_iface {
/* ddr interface validation mode */
enum mv_ddr_validation validation;
+ /* ddr interface validation mode */
+ enum mv_ddr_sscg sscg;
+
/* ddr interface topology map */
struct mv_ddr_topology_map tm;
+
};
struct mv_ddr_iface *mv_ddr_iface_get(void);
diff --git a/drivers/ddr/marvell/a38x/mv_ddr_build_message.c b/drivers/ddr/marvell/a38x/mv_ddr_build_message.c
index cc6234fd40..a2bb8a96a6 100644
--- a/drivers/ddr/marvell/a38x/mv_ddr_build_message.c
+++ b/drivers/ddr/marvell/a38x/mv_ddr_build_message.c
@@ -1,3 +1,3 @@
// SPDX-License-Identifier: GPL-2.0
const char mv_ddr_build_message[] = "";
-const char mv_ddr_version_string[] = "mv_ddr: mv_ddr-armada-18.09.2";
+const char mv_ddr_version_string[] = "mv_ddr: 14.0.0";
diff --git a/drivers/ddr/marvell/a38x/mv_ddr_plat.c b/drivers/ddr/marvell/a38x/mv_ddr_plat.c
index 72f0dfbbbb..0d1df189e8 100644
--- a/drivers/ddr/marvell/a38x/mv_ddr_plat.c
+++ b/drivers/ddr/marvell/a38x/mv_ddr_plat.c
@@ -4,6 +4,7 @@
*/
#include "ddr3_init.h"
+#include "mv_ddr_common.h"
#include "mv_ddr_training_db.h"
#include "mv_ddr_regs.h"
#include "mv_ddr_sys_env_lib.h"
@@ -1016,7 +1017,7 @@ int ddr3_calc_mem_cs_size(u32 cs, uint64_t *cs_size)
return MV_BAD_VALUE;
}
- *cs_size = cs_mem_size << 20; /* write cs size in bytes */
+ *cs_size = cs_mem_size;
return MV_OK;
}
@@ -1025,9 +1026,11 @@ static int ddr3_fast_path_dynamic_cs_size_config(u32 cs_ena)
{
u32 reg, cs;
uint64_t mem_total_size = 0;
+ uint64_t cs_mem_size_mb = 0;
uint64_t cs_mem_size = 0;
uint64_t mem_total_size_c, cs_mem_size_c;
+
#ifdef DEVICE_MAX_DRAM_ADDRESS_SIZE
u32 physical_mem_size;
u32 max_mem_size = DEVICE_MAX_DRAM_ADDRESS_SIZE;
@@ -1038,8 +1041,9 @@ static int ddr3_fast_path_dynamic_cs_size_config(u32 cs_ena)
for (cs = 0; cs < MAX_CS_NUM; cs++) {
if (cs_ena & (1 << cs)) {
/* get CS size */
- if (ddr3_calc_mem_cs_size(cs, &cs_mem_size) != MV_OK)
+ if (ddr3_calc_mem_cs_size(cs, &cs_mem_size_mb) != MV_OK)
return MV_FAIL;
+ cs_mem_size = cs_mem_size_mb * _1M;
#ifdef DEVICE_MAX_DRAM_ADDRESS_SIZE
/*
@@ -1088,6 +1092,7 @@ static int ddr3_fast_path_dynamic_cs_size_config(u32 cs_ena)
*/
mem_total_size_c = (mem_total_size >> 16) & 0xffffffffffff;
cs_mem_size_c = (cs_mem_size >> 16) & 0xffffffffffff;
+
/* if the sum less than 2 G - calculate the value */
if (mem_total_size_c + cs_mem_size_c < 0x10000)
mem_total_size += cs_mem_size;
diff --git a/drivers/ddr/marvell/a38x/mv_ddr_topology.c b/drivers/ddr/marvell/a38x/mv_ddr_topology.c
index 09840b1e70..2db6283c23 100644
--- a/drivers/ddr/marvell/a38x/mv_ddr_topology.c
+++ b/drivers/ddr/marvell/a38x/mv_ddr_topology.c
@@ -127,6 +127,11 @@ int mv_ddr_topology_map_update(void)
speed_bin_index = iface_params->speed_bin_index;
freq = iface_params->memory_freq;
+ if (tm->twin_die_combined == COMBINED) {
+ iface_params->bus_width = MV_DDR_DEV_WIDTH_8BIT;
+ iface_params->memory_size -= 1;
+ }
+
if (iface_params->cas_l == 0)
iface_params->cas_l = mv_ddr_cl_val_get(speed_bin_index, freq);
@@ -144,6 +149,9 @@ unsigned short mv_ddr_bus_bit_mask_get(void)
unsigned int octets_per_if_num = ddr3_tip_dev_attr_get(0, MV_ATTR_OCTET_PER_INTERFACE);
if (tm->cfg_src == MV_DDR_CFG_SPD) {
+ if (tm->bus_act_mask == MV_DDR_32BIT_ECC_PUP8_BUS_MASK)
+ tm->spd_data.byte_fields.byte_13.bit_fields.primary_bus_width = MV_DDR_PRI_BUS_WIDTH_32;
+
enum mv_ddr_pri_bus_width pri_bus_width = mv_ddr_spd_pri_bus_width_get(&tm->spd_data);
enum mv_ddr_bus_width_ext bus_width_ext = mv_ddr_spd_bus_width_ext_get(&tm->spd_data);
@@ -151,7 +159,7 @@ unsigned short mv_ddr_bus_bit_mask_get(void)
case MV_DDR_PRI_BUS_WIDTH_16:
pri_and_ext_bus_width = BUS_MASK_16BIT;
break;
- case MV_DDR_PRI_BUS_WIDTH_32:
+ case MV_DDR_PRI_BUS_WIDTH_32: /*each bit represents byte, so 0xf-is means 4 bytes-32 bit*/
pri_and_ext_bus_width = BUS_MASK_32BIT;
break;
case MV_DDR_PRI_BUS_WIDTH_64:
@@ -245,7 +253,8 @@ static unsigned int mem_size[] = {
ADDR_SIZE_1GB,
ADDR_SIZE_2GB,
ADDR_SIZE_4GB,
- ADDR_SIZE_8GB
+ ADDR_SIZE_8GB,
+ ADDR_SIZE_16GB
/* TODO: add capacity up to 256GB */
};
@@ -277,7 +286,6 @@ unsigned long long mv_ddr_mem_sz_per_cs_get(void)
mem_sz_per_cs = (unsigned long long)mem_size[iface_params->memory_size] *
(unsigned long long)sphys /
(unsigned long long)sphys_per_dunit;
-
return mem_sz_per_cs;
}
diff --git a/drivers/ddr/marvell/a38x/mv_ddr_topology.h b/drivers/ddr/marvell/a38x/mv_ddr_topology.h
index 4fca47689f..1cb69ad085 100644
--- a/drivers/ddr/marvell/a38x/mv_ddr_topology.h
+++ b/drivers/ddr/marvell/a38x/mv_ddr_topology.h
@@ -179,7 +179,9 @@ enum mv_ddr_dic_evalue {
/* phy electrical configuration values */
enum mv_ddr_ohm_evalue {
+ MV_DDR_OHM_20 = 20,/*relevant for Synopsys C/A Drive strength only*/
MV_DDR_OHM_30 = 30,
+ MV_DDR_OHM_40 = 40,/*relevant for Synopsys C/A Drive strength only*/
MV_DDR_OHM_48 = 48,
MV_DDR_OHM_60 = 60,
MV_DDR_OHM_80 = 80,
diff --git a/drivers/ddr/marvell/a38x/xor.c b/drivers/ddr/marvell/a38x/xor.c
index 5fb9e216d3..98fb39eaf0 100644
--- a/drivers/ddr/marvell/a38x/xor.c
+++ b/drivers/ddr/marvell/a38x/xor.c
@@ -340,7 +340,7 @@ void ddr3_new_tip_ecc_scrub(void)
{
u32 cs_c, max_cs;
u32 cs_ena = 0;
- uint64_t total_mem_size, cs_mem_size = 0;
+ uint64_t total_mem_size, cs_mem_size_mb = 0, cs_mem_size = 0;
printf("DDR Training Sequence - Start scrubbing\n");
max_cs = mv_ddr_cs_num_get();
@@ -349,9 +349,9 @@ void ddr3_new_tip_ecc_scrub(void)
#if defined(CONFIG_ARMADA_38X) || defined(CONFIG_ARMADA_39X)
/* all chip-selects are of same size */
- ddr3_calc_mem_cs_size(0, &cs_mem_size);
+ ddr3_calc_mem_cs_size(0, &cs_mem_size_mb);
#endif
-
+ cs_mem_size = cs_mem_size_mb * _1M;
mv_sys_xor_init(max_cs, cs_ena, cs_mem_size, 0);
total_mem_size = max_cs * cs_mem_size;
mv_xor_mem_init(0, 0, total_mem_size, 0xdeadbeef, 0xdeadbeef);
--
2.26.2
^ permalink raw reply related [flat|nested] 3+ messages in thread
* [PATCH u-boot-marvell] ARM: mvebu: a38x: sync ddr training code with mv_ddr-armada-14.0.0
2021-02-08 16:04 [PATCH u-boot-marvell] ARM: mvebu: a38x: sync ddr training code with mv_ddr-armada-14.0.0 Marek Behún
@ 2021-02-08 16:24 ` Stefan Roese
2021-02-08 16:31 ` Marek Behun
0 siblings, 1 reply; 3+ messages in thread
From: Stefan Roese @ 2021-02-08 16:24 UTC (permalink / raw
To: u-boot
Hi Marek,
On 08.02.21 17:04, Marek Beh?n wrote:
> This syncs drivers/ddr/marvell/a38x/ with the mv-ddr-devel branch
> of https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git.
> Specifically this syncs with commit fae3f6c98230 ("Bump mv_ddr to
> release 14.0.0").
>
> There is a new version numbering system, where after 18.12.0 came
> 1.0.0, 2.0.0, and so on until 14.0.0. So 14.0.0 is newer than 18.12.0.
>
> There are some commits regarding DDR3 on top of version 14.0.0 in the
> mv-ddr-marvell repository (from Chris Packham), but these changes
> already are in U-Boot.
>
> The complete log of changes is best obtained from the mv-ddr-marvell.git
> repository but some relevant highlights are:
>
> ddr3: allow board specific ODT configuration
> mv_ddr: add 16Gbit memory devices support
> mv_ddr: add support for twin-die combined memory device
> mv_ddr: a38x: disable WL phase correction stage in case of bus_width=16bit
> mv_ddr: a38x : fix memory cs size function
Great, thanks for working on this. But can't you instead of sending this
one big patch not send a list of separate patches (list above etc)? This
would make it easier to see and review the changes and also would
preserve the authorship of the patches.
Thanks,
Stefan
> The default value for new option twin_die_combined is set to
> NOT_COMBINED for all boards, as this was default behaviour prior this
> change.
>
> Signed-off-by: Marek Beh?n <marek.behun@nic.cz>
> Cc: Chris Packham <judge.packham@gmail.com>
> Cc: Chris Packham <chris.packham@alliedtelesis.co.nz>
> Cc: Stefan Roese <sr@denx.de>
> Cc: Baruch Siach <baruch@tkos.co.il>
> Cc: Pavol Roh?r <pali@kernel.org>
> ---
> board/CZ.NIC/turris_omnia/turris_omnia.c | 2 ++
> board/Marvell/db-88f6820-amc/db-88f6820-amc.c | 1 +
> board/Marvell/db-88f6820-gp/db-88f6820-gp.c | 1 +
> board/alliedtelesis/x530/x530.c | 1 +
> board/gdsys/a38x/controlcenterdc.c | 1 +
> board/kobol/helios4/helios4.c | 1 +
> board/solidrun/clearfog/clearfog.c | 1 +
> drivers/ddr/marvell/a38x/ddr3_init.c | 5 ++++
> drivers/ddr/marvell/a38x/ddr3_init.h | 2 +-
> drivers/ddr/marvell/a38x/ddr3_training.c | 5 +++-
> drivers/ddr/marvell/a38x/ddr3_training_db.c | 3 +++
> .../ddr/marvell/a38x/ddr3_training_ip_def.h | 2 ++
> .../marvell/a38x/ddr3_training_ip_engine.c | 5 +++-
> drivers/ddr/marvell/a38x/ddr_topology_def.h | 23 ++++++++++++++++++-
> .../ddr/marvell/a38x/mv_ddr_build_message.c | 2 +-
> drivers/ddr/marvell/a38x/mv_ddr_plat.c | 9 ++++++--
> drivers/ddr/marvell/a38x/mv_ddr_topology.c | 14 ++++++++---
> drivers/ddr/marvell/a38x/mv_ddr_topology.h | 2 ++
> drivers/ddr/marvell/a38x/xor.c | 6 ++---
> 19 files changed, 73 insertions(+), 13 deletions(-)
>
> diff --git a/board/CZ.NIC/turris_omnia/turris_omnia.c b/board/CZ.NIC/turris_omnia/turris_omnia.c
> index 2da878d364..78b125edfe 100644
> --- a/board/CZ.NIC/turris_omnia/turris_omnia.c
> +++ b/board/CZ.NIC/turris_omnia/turris_omnia.c
> @@ -285,6 +285,7 @@ static struct mv_ddr_topology_map board_topology_map_1g = {
> MV_DDR_TIM_2T} }, /* timing */
> BUS_MASK_32BIT, /* Busses mask */
> MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
> + NOT_COMBINED, /* ddr twin-die combined */
> { {0} }, /* raw spd data */
> {0} /* timing parameters */
> };
> @@ -307,6 +308,7 @@ static struct mv_ddr_topology_map board_topology_map_2g = {
> MV_DDR_TIM_2T} }, /* timing */
> BUS_MASK_32BIT, /* Busses mask */
> MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
> + NOT_COMBINED, /* ddr twin-die combined */
> { {0} }, /* raw spd data */
> {0} /* timing parameters */
> };
> diff --git a/board/Marvell/db-88f6820-amc/db-88f6820-amc.c b/board/Marvell/db-88f6820-amc/db-88f6820-amc.c
> index 9cd9ea2c06..acc8a5ec6d 100644
> --- a/board/Marvell/db-88f6820-amc/db-88f6820-amc.c
> +++ b/board/Marvell/db-88f6820-amc/db-88f6820-amc.c
> @@ -72,6 +72,7 @@ static struct mv_ddr_topology_map board_topology_map = {
> MV_DDR_TIM_DEFAULT} }, /* timing */
> BUS_MASK_32BIT, /* Busses mask */
> MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
> + NOT_COMBINED, /* ddr twin-die combined */
> { {0} }, /* raw spd data */
> {0} /* timing parameters */
> };
> diff --git a/board/Marvell/db-88f6820-gp/db-88f6820-gp.c b/board/Marvell/db-88f6820-gp/db-88f6820-gp.c
> index 2bdd55329d..a1d0104526 100644
> --- a/board/Marvell/db-88f6820-gp/db-88f6820-gp.c
> +++ b/board/Marvell/db-88f6820-gp/db-88f6820-gp.c
> @@ -93,6 +93,7 @@ static struct mv_ddr_topology_map board_topology_map = {
> MV_DDR_TIM_DEFAULT} }, /* timing */
> BUS_MASK_32BIT, /* Busses mask */
> MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
> + NOT_COMBINED, /* ddr twin-die combined */
> { {0} }, /* raw spd data */
> {0} /* timing parameters */
> };
> diff --git a/board/alliedtelesis/x530/x530.c b/board/alliedtelesis/x530/x530.c
> index c7438aeaf1..6caba24196 100644
> --- a/board/alliedtelesis/x530/x530.c
> +++ b/board/alliedtelesis/x530/x530.c
> @@ -67,6 +67,7 @@ static struct mv_ddr_topology_map board_topology_map = {
> MV_DDR_TIM_2T} }, /* timing */
> BUS_MASK_32BIT_ECC, /* subphys mask */
> MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
> + NOT_COMBINED, /* ddr twin-die combined */
> { {0} }, /* raw spd data */
> {0}, /* timing parameters */
> { {0} }, /* electrical configuration */
> diff --git a/board/gdsys/a38x/controlcenterdc.c b/board/gdsys/a38x/controlcenterdc.c
> index a2287f9deb..66a0d769ce 100644
> --- a/board/gdsys/a38x/controlcenterdc.c
> +++ b/board/gdsys/a38x/controlcenterdc.c
> @@ -70,6 +70,7 @@ static struct mv_ddr_topology_map ddr_topology_map = {
> MV_DDR_TIM_DEFAULT} }, /* timing */
> BUS_MASK_32BIT, /* Busses mask */
> MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
> + NOT_COMBINED, /* ddr twin-die combined */
> { {0} }, /* raw spd data */
> {0} /* timing parameters */
>
> diff --git a/board/kobol/helios4/helios4.c b/board/kobol/helios4/helios4.c
> index 17d2489415..5007194a52 100644
> --- a/board/kobol/helios4/helios4.c
> +++ b/board/kobol/helios4/helios4.c
> @@ -70,6 +70,7 @@ static struct mv_ddr_topology_map board_topology_map = {
> MV_DDR_TIM_DEFAULT} }, /* timing */
> BUS_MASK_32BIT_ECC, /* Busses mask */
> MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
> + NOT_COMBINED, /* ddr twin-die combined */
> { {0} }, /* raw spd data */
> {0} /* timing parameters */
> };
> diff --git a/board/solidrun/clearfog/clearfog.c b/board/solidrun/clearfog/clearfog.c
> index 92443d5177..3166f0abe0 100644
> --- a/board/solidrun/clearfog/clearfog.c
> +++ b/board/solidrun/clearfog/clearfog.c
> @@ -141,6 +141,7 @@ static struct mv_ddr_topology_map board_topology_map = {
> MV_DDR_TIM_DEFAULT} }, /* timing */
> BUS_MASK_32BIT, /* Busses mask */
> MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
> + NOT_COMBINED, /* ddr twin-die combined */
> { {0} }, /* raw spd data */
> {0}, /* timing parameters */
> { {0} }, /* electrical configuration */
> diff --git a/drivers/ddr/marvell/a38x/ddr3_init.c b/drivers/ddr/marvell/a38x/ddr3_init.c
> index a971cc155a..7488770268 100644
> --- a/drivers/ddr/marvell/a38x/ddr3_init.c
> +++ b/drivers/ddr/marvell/a38x/ddr3_init.c
> @@ -104,6 +104,7 @@ int ddr3_init(void)
> static int mv_ddr_training_params_set(u8 dev_num)
> {
> struct tune_train_params params;
> + struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
> int status;
> u32 cs_num;
> int ck_delay;
> @@ -136,6 +137,10 @@ static int mv_ddr_training_params_set(u8 dev_num)
> if (ck_delay > 0)
> params.ck_delay = ck_delay;
>
> + /* Use platform specific override ODT value */
> + if (tm->odt_config)
> + params.g_odt_config = tm->odt_config;
> +
> status = ddr3_tip_tune_training_params(dev_num, ¶ms);
> if (MV_OK != status) {
> printf("%s Training Sequence - FAILED\n", ddr_type);
> diff --git a/drivers/ddr/marvell/a38x/ddr3_training.c b/drivers/ddr/marvell/a38x/ddr3_training.c
> index 34cc170910..2b3af23202 100644
> --- a/drivers/ddr/marvell/a38x/ddr3_training.c
> +++ b/drivers/ddr/marvell/a38x/ddr3_training.c
> @@ -143,6 +143,7 @@ static struct reg_data odpg_default_value[] = {
> {0x15a4, 0x0, MASK_ALL_BITS},
> {0x15a8, 0x0, MASK_ALL_BITS},
> {0x15ac, 0x0, MASK_ALL_BITS},
> + {0x1600, 0x0, MASK_ALL_BITS},
> {0x1604, 0x0, MASK_ALL_BITS},
> {0x1608, 0x0, MASK_ALL_BITS},
> {0x160c, 0x0, MASK_ALL_BITS},
> @@ -218,7 +219,7 @@ static int ddr3_tip_pad_inv(void)
> DDR_PHY_CONTROL,
> PHY_CTRL_PHY_REG,
> data, data);
> -#else /* !CONFIG_ARMADA_38X && !CONFIG_ARMADA_39X && !A70X0 && !A80X0 && !A3900 */
> +#else /* !CONFIG_ARMADA_38X && !CONFIG_ARMADA_39X */
> #pragma message "unknown platform to configure ddr clock swap"
> #endif
> }
> @@ -1569,6 +1570,8 @@ int ddr3_tip_freq_set(u32 dev_num, enum hws_access_type access_type,
> val = ((cl_mask_table[cl_value] & 0x1) << 2) |
> ((cl_mask_table[cl_value] & 0xe) << 3);
>
> + cs_mask[0] = 0xc;
> +
> CHECK_STATUS(ddr3_tip_write_mrs_cmd(dev_num, cs_mask, MR_CMD0,
> val, (0x7 << 4) | (0x1 << 2)));
>
> diff --git a/drivers/ddr/marvell/a38x/ddr3_training_db.c b/drivers/ddr/marvell/a38x/ddr3_training_db.c
> index b2f11a8399..6aa7b6069e 100644
> --- a/drivers/ddr/marvell/a38x/ddr3_training_db.c
> +++ b/drivers/ddr/marvell/a38x/ddr3_training_db.c
> @@ -833,6 +833,9 @@ u32 pattern_table_get_word(u32 dev_num, enum hws_pattern type, u8 index)
> pattern = pattern_table_get_isi_word16(index);
> break;
> default:
> + if (((int)type == 29) || ((int)type == 30))
> + break;
> +
> printf("error: %s: unsupported pattern type [%d] found\n",
> __func__, (int)type);
> pattern = 0;
> diff --git a/drivers/ddr/marvell/a38x/ddr3_training_ip_def.h b/drivers/ddr/marvell/a38x/ddr3_training_ip_def.h
> index 2a68669f36..8765df7cfb 100644
> --- a/drivers/ddr/marvell/a38x/ddr3_training_ip_def.h
> +++ b/drivers/ddr/marvell/a38x/ddr3_training_ip_def.h
> @@ -80,6 +80,8 @@
> #define ADDR_SIZE_2GB 0x10000000
> #define ADDR_SIZE_4GB 0x20000000
> #define ADDR_SIZE_8GB 0x40000000
> +#define ADDR_SIZE_16GB 0x80000000
> +
>
> enum hws_edge_compare {
> EDGE_PF,
> diff --git a/drivers/ddr/marvell/a38x/ddr3_training_ip_engine.c b/drivers/ddr/marvell/a38x/ddr3_training_ip_engine.c
> index 979f3530b7..5fd9a052fa 100644
> --- a/drivers/ddr/marvell/a38x/ddr3_training_ip_engine.c
> +++ b/drivers/ddr/marvell/a38x/ddr3_training_ip_engine.c
> @@ -864,8 +864,11 @@ int ddr3_tip_load_all_pattern_to_mem(u32 dev_num)
> DUAL_DUNIT_CFG_REG, (1 << 3), (1 << 3)));
> }
>
> - for (pattern = 0; pattern < PATTERN_LAST; pattern++)
> + for (pattern = 0; pattern < PATTERN_LAST; pattern++) {
> + if (pattern == PATTERN_TEST)
> + continue;
> ddr3_tip_load_pattern_to_mem(dev_num, pattern);
> + }
>
> return MV_OK;
> }
> diff --git a/drivers/ddr/marvell/a38x/ddr_topology_def.h b/drivers/ddr/marvell/a38x/ddr_topology_def.h
> index 34196b1662..2cca5676a0 100644
> --- a/drivers/ddr/marvell/a38x/ddr_topology_def.h
> +++ b/drivers/ddr/marvell/a38x/ddr_topology_def.h
> @@ -14,6 +14,11 @@
> #define MV_DDR_MAX_BUS_NUM 9
> #define MV_DDR_MAX_IFACE_NUM 1
>
> +enum mv_ddr_twin_die {
> + NOT_COMBINED,
> + COMBINED,
> +};
> +
> struct bus_params {
> /* Chip Select (CS) bitmask (bits 0-CS0, bit 1- CS1 ...) */
> u8 cs_bitmask;
> @@ -113,6 +118,9 @@ struct mv_ddr_topology_map {
> /* source of ddr configuration data */
> enum mv_ddr_cfg_src cfg_src;
>
> + /* ddr twin-die */
> + enum mv_ddr_twin_die twin_die_combined;
> +
> /* raw spd data */
> union mv_ddr_spd_data spd_data;
>
> @@ -125,6 +133,9 @@ struct mv_ddr_topology_map {
> /* electrical parameters */
> unsigned int electrical_data[MV_DDR_EDATA_LAST];
>
> + /* ODT configuration */
> + u32 odt_config;
> +
> /* Clock enable mask */
> u32 clk_enable;
>
> @@ -148,7 +159,13 @@ enum mv_ddr_validation {
> MV_DDR_VAL_DIS,
> MV_DDR_VAL_RX,
> MV_DDR_VAL_TX,
> - MV_DDR_VAL_RX_TX
> + MV_DDR_VAL_RX_TX,
> + MV_DDR_MEMORY_CHECK
> +};
> +
> +enum mv_ddr_sscg {
> + SSCG_EN,
> + SSCG_DIS,
> };
>
> struct mv_ddr_iface {
> @@ -179,8 +196,12 @@ struct mv_ddr_iface {
> /* ddr interface validation mode */
> enum mv_ddr_validation validation;
>
> + /* ddr interface validation mode */
> + enum mv_ddr_sscg sscg;
> +
> /* ddr interface topology map */
> struct mv_ddr_topology_map tm;
> +
> };
>
> struct mv_ddr_iface *mv_ddr_iface_get(void);
> diff --git a/drivers/ddr/marvell/a38x/mv_ddr_build_message.c b/drivers/ddr/marvell/a38x/mv_ddr_build_message.c
> index cc6234fd40..a2bb8a96a6 100644
> --- a/drivers/ddr/marvell/a38x/mv_ddr_build_message.c
> +++ b/drivers/ddr/marvell/a38x/mv_ddr_build_message.c
> @@ -1,3 +1,3 @@
> // SPDX-License-Identifier: GPL-2.0
> const char mv_ddr_build_message[] = "";
> -const char mv_ddr_version_string[] = "mv_ddr: mv_ddr-armada-18.09.2";
> +const char mv_ddr_version_string[] = "mv_ddr: 14.0.0";
> diff --git a/drivers/ddr/marvell/a38x/mv_ddr_plat.c b/drivers/ddr/marvell/a38x/mv_ddr_plat.c
> index 72f0dfbbbb..0d1df189e8 100644
> --- a/drivers/ddr/marvell/a38x/mv_ddr_plat.c
> +++ b/drivers/ddr/marvell/a38x/mv_ddr_plat.c
> @@ -4,6 +4,7 @@
> */
>
> #include "ddr3_init.h"
> +#include "mv_ddr_common.h"
> #include "mv_ddr_training_db.h"
> #include "mv_ddr_regs.h"
> #include "mv_ddr_sys_env_lib.h"
> @@ -1016,7 +1017,7 @@ int ddr3_calc_mem_cs_size(u32 cs, uint64_t *cs_size)
> return MV_BAD_VALUE;
> }
>
> - *cs_size = cs_mem_size << 20; /* write cs size in bytes */
> + *cs_size = cs_mem_size;
>
> return MV_OK;
> }
> @@ -1025,9 +1026,11 @@ static int ddr3_fast_path_dynamic_cs_size_config(u32 cs_ena)
> {
> u32 reg, cs;
> uint64_t mem_total_size = 0;
> + uint64_t cs_mem_size_mb = 0;
> uint64_t cs_mem_size = 0;
> uint64_t mem_total_size_c, cs_mem_size_c;
>
> +
> #ifdef DEVICE_MAX_DRAM_ADDRESS_SIZE
> u32 physical_mem_size;
> u32 max_mem_size = DEVICE_MAX_DRAM_ADDRESS_SIZE;
> @@ -1038,8 +1041,9 @@ static int ddr3_fast_path_dynamic_cs_size_config(u32 cs_ena)
> for (cs = 0; cs < MAX_CS_NUM; cs++) {
> if (cs_ena & (1 << cs)) {
> /* get CS size */
> - if (ddr3_calc_mem_cs_size(cs, &cs_mem_size) != MV_OK)
> + if (ddr3_calc_mem_cs_size(cs, &cs_mem_size_mb) != MV_OK)
> return MV_FAIL;
> + cs_mem_size = cs_mem_size_mb * _1M;
>
> #ifdef DEVICE_MAX_DRAM_ADDRESS_SIZE
> /*
> @@ -1088,6 +1092,7 @@ static int ddr3_fast_path_dynamic_cs_size_config(u32 cs_ena)
> */
> mem_total_size_c = (mem_total_size >> 16) & 0xffffffffffff;
> cs_mem_size_c = (cs_mem_size >> 16) & 0xffffffffffff;
> +
> /* if the sum less than 2 G - calculate the value */
> if (mem_total_size_c + cs_mem_size_c < 0x10000)
> mem_total_size += cs_mem_size;
> diff --git a/drivers/ddr/marvell/a38x/mv_ddr_topology.c b/drivers/ddr/marvell/a38x/mv_ddr_topology.c
> index 09840b1e70..2db6283c23 100644
> --- a/drivers/ddr/marvell/a38x/mv_ddr_topology.c
> +++ b/drivers/ddr/marvell/a38x/mv_ddr_topology.c
> @@ -127,6 +127,11 @@ int mv_ddr_topology_map_update(void)
> speed_bin_index = iface_params->speed_bin_index;
> freq = iface_params->memory_freq;
>
> + if (tm->twin_die_combined == COMBINED) {
> + iface_params->bus_width = MV_DDR_DEV_WIDTH_8BIT;
> + iface_params->memory_size -= 1;
> + }
> +
> if (iface_params->cas_l == 0)
> iface_params->cas_l = mv_ddr_cl_val_get(speed_bin_index, freq);
>
> @@ -144,6 +149,9 @@ unsigned short mv_ddr_bus_bit_mask_get(void)
> unsigned int octets_per_if_num = ddr3_tip_dev_attr_get(0, MV_ATTR_OCTET_PER_INTERFACE);
>
> if (tm->cfg_src == MV_DDR_CFG_SPD) {
> + if (tm->bus_act_mask == MV_DDR_32BIT_ECC_PUP8_BUS_MASK)
> + tm->spd_data.byte_fields.byte_13.bit_fields.primary_bus_width = MV_DDR_PRI_BUS_WIDTH_32;
> +
> enum mv_ddr_pri_bus_width pri_bus_width = mv_ddr_spd_pri_bus_width_get(&tm->spd_data);
> enum mv_ddr_bus_width_ext bus_width_ext = mv_ddr_spd_bus_width_ext_get(&tm->spd_data);
>
> @@ -151,7 +159,7 @@ unsigned short mv_ddr_bus_bit_mask_get(void)
> case MV_DDR_PRI_BUS_WIDTH_16:
> pri_and_ext_bus_width = BUS_MASK_16BIT;
> break;
> - case MV_DDR_PRI_BUS_WIDTH_32:
> + case MV_DDR_PRI_BUS_WIDTH_32: /*each bit represents byte, so 0xf-is means 4 bytes-32 bit*/
> pri_and_ext_bus_width = BUS_MASK_32BIT;
> break;
> case MV_DDR_PRI_BUS_WIDTH_64:
> @@ -245,7 +253,8 @@ static unsigned int mem_size[] = {
> ADDR_SIZE_1GB,
> ADDR_SIZE_2GB,
> ADDR_SIZE_4GB,
> - ADDR_SIZE_8GB
> + ADDR_SIZE_8GB,
> + ADDR_SIZE_16GB
> /* TODO: add capacity up to 256GB */
> };
>
> @@ -277,7 +286,6 @@ unsigned long long mv_ddr_mem_sz_per_cs_get(void)
> mem_sz_per_cs = (unsigned long long)mem_size[iface_params->memory_size] *
> (unsigned long long)sphys /
> (unsigned long long)sphys_per_dunit;
> -
> return mem_sz_per_cs;
> }
>
> diff --git a/drivers/ddr/marvell/a38x/mv_ddr_topology.h b/drivers/ddr/marvell/a38x/mv_ddr_topology.h
> index 4fca47689f..1cb69ad085 100644
> --- a/drivers/ddr/marvell/a38x/mv_ddr_topology.h
> +++ b/drivers/ddr/marvell/a38x/mv_ddr_topology.h
> @@ -179,7 +179,9 @@ enum mv_ddr_dic_evalue {
>
> /* phy electrical configuration values */
> enum mv_ddr_ohm_evalue {
> + MV_DDR_OHM_20 = 20,/*relevant for Synopsys C/A Drive strength only*/
> MV_DDR_OHM_30 = 30,
> + MV_DDR_OHM_40 = 40,/*relevant for Synopsys C/A Drive strength only*/
> MV_DDR_OHM_48 = 48,
> MV_DDR_OHM_60 = 60,
> MV_DDR_OHM_80 = 80,
> diff --git a/drivers/ddr/marvell/a38x/xor.c b/drivers/ddr/marvell/a38x/xor.c
> index 5fb9e216d3..98fb39eaf0 100644
> --- a/drivers/ddr/marvell/a38x/xor.c
> +++ b/drivers/ddr/marvell/a38x/xor.c
> @@ -340,7 +340,7 @@ void ddr3_new_tip_ecc_scrub(void)
> {
> u32 cs_c, max_cs;
> u32 cs_ena = 0;
> - uint64_t total_mem_size, cs_mem_size = 0;
> + uint64_t total_mem_size, cs_mem_size_mb = 0, cs_mem_size = 0;
>
> printf("DDR Training Sequence - Start scrubbing\n");
> max_cs = mv_ddr_cs_num_get();
> @@ -349,9 +349,9 @@ void ddr3_new_tip_ecc_scrub(void)
>
> #if defined(CONFIG_ARMADA_38X) || defined(CONFIG_ARMADA_39X)
> /* all chip-selects are of same size */
> - ddr3_calc_mem_cs_size(0, &cs_mem_size);
> + ddr3_calc_mem_cs_size(0, &cs_mem_size_mb);
> #endif
> -
> + cs_mem_size = cs_mem_size_mb * _1M;
> mv_sys_xor_init(max_cs, cs_ena, cs_mem_size, 0);
> total_mem_size = max_cs * cs_mem_size;
> mv_xor_mem_init(0, 0, total_mem_size, 0xdeadbeef, 0xdeadbeef);
>
Viele Gr??e,
Stefan
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-51 Fax: (+49)-8142-66989-80 Email: sr at denx.de
^ permalink raw reply [flat|nested] 3+ messages in thread
* [PATCH u-boot-marvell] ARM: mvebu: a38x: sync ddr training code with mv_ddr-armada-14.0.0
2021-02-08 16:24 ` Stefan Roese
@ 2021-02-08 16:31 ` Marek Behun
0 siblings, 0 replies; 3+ messages in thread
From: Marek Behun @ 2021-02-08 16:31 UTC (permalink / raw
To: u-boot
On Mon, 8 Feb 2021 17:24:16 +0100
Stefan Roese <sr@denx.de> wrote:
> Hi Marek,
>
> On 08.02.21 17:04, Marek Beh?n wrote:
> > This syncs drivers/ddr/marvell/a38x/ with the mv-ddr-devel branch
> > of https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git.
> > Specifically this syncs with commit fae3f6c98230 ("Bump mv_ddr to
> > release 14.0.0").
> >
> > There is a new version numbering system, where after 18.12.0 came
> > 1.0.0, 2.0.0, and so on until 14.0.0. So 14.0.0 is newer than 18.12.0.
> >
> > There are some commits regarding DDR3 on top of version 14.0.0 in the
> > mv-ddr-marvell repository (from Chris Packham), but these changes
> > already are in U-Boot.
> >
> > The complete log of changes is best obtained from the mv-ddr-marvell.git
> > repository but some relevant highlights are:
> >
> > ddr3: allow board specific ODT configuration
> > mv_ddr: add 16Gbit memory devices support
> > mv_ddr: add support for twin-die combined memory device
> > mv_ddr: a38x: disable WL phase correction stage in case of bus_width=16bit
> > mv_ddr: a38x : fix memory cs size function
>
> Great, thanks for working on this. But can't you instead of sending this
> one big patch not send a list of separate patches (list above etc)? This
> would make it easier to see and review the changes and also would
> preserve the authorship of the patches.
Very well, I shall try to do it that way. BTW I forgot to change the
author (original author is Pali, I just updated the patch a little and
rewrote the commit message).
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2021-02-08 16:31 UTC | newest]
Thread overview: 3+ messages (download: mbox.gz follow: Atom feed
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2021-02-08 16:04 [PATCH u-boot-marvell] ARM: mvebu: a38x: sync ddr training code with mv_ddr-armada-14.0.0 Marek Behún
2021-02-08 16:24 ` Stefan Roese
2021-02-08 16:31 ` Marek Behun
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