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Wed, 04 Aug 2021 11:36:43 -0700 (PDT) Received: from [192.168.8.102] ([86.32.43.172]) by smtp.gmail.com with ESMTPSA id cm1sm1248761edb.68.2021.08.04.11.36.41 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 04 Aug 2021 11:36:42 -0700 (PDT) To: Sam Protsenko , Marc Zyngier Cc: Sylwester Nawrocki , Chanwoo Choi , Linus Walleij , Tomasz Figa , Rob Herring , Stephen Boyd , Michael Turquette , Jiri Slaby , Greg Kroah-Hartman , Charles Keepax , Ryu Euiyoul , Tom Gall , Sumit Semwal , John Stultz , Amit Pundir , devicetree , linux-arm Mailing List , linux-clk , "open list:GPIO SUBSYSTEM" , Linux Kernel Mailing List , Linux Samsung SOC , "open list:SERIAL DRIVERS" References: <20210730144922.29111-1-semen.protsenko@linaro.org> <20210730144922.29111-13-semen.protsenko@linaro.org> <15871f8ced3c757fad1ab3b6e62c4e64@misterjones.org> From: Krzysztof Kozlowski Subject: Re: [PATCH 12/12] arm64: dts: exynos: Add Exynos850 SoC support Message-ID: Date: Wed, 4 Aug 2021 20:36:40 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.11.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 04/08/2021 16:39, Sam Protsenko wrote: > Hi Marc, > > On Fri, 30 Jul 2021 at 19:50, Marc Zyngier wrote: >> >> On 2021-07-30 15:49, Sam Protsenko wrote: >>> Samsung Exynos850 is ARMv8-based mobile-oriented SoC. >>> >>> Features: >>> * CPU: Cortex-A55 Octa (8 cores), up to 2 GHz >>> * Memory interface: LPDDR4/4x 2 channels (12.8 GB/s) >>> * SD/MMC: SD 3.0, eMMC5.1 DDR 8-bit >>> * Modem: 4G LTE, 3G, GSM/GPRS/EDGE >>> * RF: Quad GNSS, WiFi 5 (802.11ac), Bluetooth 5.0 >>> * GPU: Mali-G52 MP1 >>> * Codec: 1080p 60fps H64, HEVC, JPEG HW Codec >>> * Display: Full HD+ (2520x1080)@60fps LCD >>> * Camera: 16+5MP/13+8MP ISP, MIPI CSI 4/4/2, FD, DRC >>> * Connectivity: USB 2.0 DRD, USI (SPI/UART/I2C), HSI2C, I3C, ADC, >>> Audio >>> >>> This patch adds minimal SoC support. Particular board device tree files >>> can include exynos850.dtsi file to get SoC related nodes, and then >>> reference those nodes further as needed. >>> >>> Signed-off-by: Sam Protsenko >>> --- >>> .../boot/dts/exynos/exynos850-pinctrl.dtsi | 782 ++++++++++++++++++ >>> arch/arm64/boot/dts/exynos/exynos850-usi.dtsi | 30 + >>> arch/arm64/boot/dts/exynos/exynos850.dtsi | 245 ++++++ >>> 3 files changed, 1057 insertions(+) >>> create mode 100644 arch/arm64/boot/dts/exynos/exynos850-pinctrl.dtsi >>> create mode 100644 arch/arm64/boot/dts/exynos/exynos850-usi.dtsi >>> create mode 100644 arch/arm64/boot/dts/exynos/exynos850.dtsi >>> >>> diff --git a/arch/arm64/boot/dts/exynos/exynos850-pinctrl.dtsi >>> b/arch/arm64/boot/dts/exynos/exynos850-pinctrl.dtsi >>> new file mode 100644 >>> index 000000000000..4cf0a22cc6db >> >> [...] >> >>> + gic: interrupt-controller@12a00000 { >>> + compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; >> >> One thing for sure, it cannot be both. And given that it is >> an A55-based SoC, it isn't either. It is more likely a GIC400. >> > > Yes, it's GIC-400, thanks for pointing that out. Will fix that in v2. > >>> + #interrupt-cells = <3>; >>> + #address-cells = <0>; >>> + interrupt-controller; >>> + reg = <0x0 0x12a01000 0x1000>, >>> + <0x0 0x12a02000 0x1000>, >> >> This is wrong. It is architecturally set to 8kB. >> > > Nice catch! Actually there is an error (typo?) in SoC's TRM, saying > that Virtual Interface Control Register starts at 0x3000 offset (from > 0x12a00000), where it obviously should be 0x4000, that's probably > where this dts error originates from. Btw, I'm also seeing the same > error in exynos7.dtsi. What's the error exactly? The "Virtual interface control register" offset (3rd region) is set properly to 0x4000 on Exynos7. Also one for the Exynos5433 looks correct. > Though I don't have a TRM for Exynos7 SoCs, so > not sure if I should go ahead and fix that too. Anyway, for Exynos850, > I'll fix that in v2 series. However while we are at addresses - why are you using address-cells 2? It adds everywhere additional 0x0 before actual address. Best regards, Krzysztof From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id F1244C4338F for ; Wed, 4 Aug 2021 18:38:31 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C06D561002 for ; Wed, 4 Aug 2021 18:38:31 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org C06D561002 Authentication-Results: mail.kernel.org; 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Wed, 04 Aug 2021 11:36:43 -0700 (PDT) Received: from [192.168.8.102] ([86.32.43.172]) by smtp.gmail.com with ESMTPSA id cm1sm1248761edb.68.2021.08.04.11.36.41 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 04 Aug 2021 11:36:42 -0700 (PDT) To: Sam Protsenko , Marc Zyngier Cc: Sylwester Nawrocki , Chanwoo Choi , Linus Walleij , Tomasz Figa , Rob Herring , Stephen Boyd , Michael Turquette , Jiri Slaby , Greg Kroah-Hartman , Charles Keepax , Ryu Euiyoul , Tom Gall , Sumit Semwal , John Stultz , Amit Pundir , devicetree , linux-arm Mailing List , linux-clk , "open list:GPIO SUBSYSTEM" , Linux Kernel Mailing List , Linux Samsung SOC , "open list:SERIAL DRIVERS" References: <20210730144922.29111-1-semen.protsenko@linaro.org> <20210730144922.29111-13-semen.protsenko@linaro.org> <15871f8ced3c757fad1ab3b6e62c4e64@misterjones.org> From: Krzysztof Kozlowski Subject: Re: [PATCH 12/12] arm64: dts: exynos: Add Exynos850 SoC support Message-ID: Date: Wed, 4 Aug 2021 20:36:40 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.11.0 MIME-Version: 1.0 In-Reply-To: Content-Language: en-US X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210804_113652_459335_D820E60D X-CRM114-Status: GOOD ( 26.70 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 04/08/2021 16:39, Sam Protsenko wrote: > Hi Marc, > > On Fri, 30 Jul 2021 at 19:50, Marc Zyngier wrote: >> >> On 2021-07-30 15:49, Sam Protsenko wrote: >>> Samsung Exynos850 is ARMv8-based mobile-oriented SoC. >>> >>> Features: >>> * CPU: Cortex-A55 Octa (8 cores), up to 2 GHz >>> * Memory interface: LPDDR4/4x 2 channels (12.8 GB/s) >>> * SD/MMC: SD 3.0, eMMC5.1 DDR 8-bit >>> * Modem: 4G LTE, 3G, GSM/GPRS/EDGE >>> * RF: Quad GNSS, WiFi 5 (802.11ac), Bluetooth 5.0 >>> * GPU: Mali-G52 MP1 >>> * Codec: 1080p 60fps H64, HEVC, JPEG HW Codec >>> * Display: Full HD+ (2520x1080)@60fps LCD >>> * Camera: 16+5MP/13+8MP ISP, MIPI CSI 4/4/2, FD, DRC >>> * Connectivity: USB 2.0 DRD, USI (SPI/UART/I2C), HSI2C, I3C, ADC, >>> Audio >>> >>> This patch adds minimal SoC support. Particular board device tree files >>> can include exynos850.dtsi file to get SoC related nodes, and then >>> reference those nodes further as needed. >>> >>> Signed-off-by: Sam Protsenko >>> --- >>> .../boot/dts/exynos/exynos850-pinctrl.dtsi | 782 ++++++++++++++++++ >>> arch/arm64/boot/dts/exynos/exynos850-usi.dtsi | 30 + >>> arch/arm64/boot/dts/exynos/exynos850.dtsi | 245 ++++++ >>> 3 files changed, 1057 insertions(+) >>> create mode 100644 arch/arm64/boot/dts/exynos/exynos850-pinctrl.dtsi >>> create mode 100644 arch/arm64/boot/dts/exynos/exynos850-usi.dtsi >>> create mode 100644 arch/arm64/boot/dts/exynos/exynos850.dtsi >>> >>> diff --git a/arch/arm64/boot/dts/exynos/exynos850-pinctrl.dtsi >>> b/arch/arm64/boot/dts/exynos/exynos850-pinctrl.dtsi >>> new file mode 100644 >>> index 000000000000..4cf0a22cc6db >> >> [...] >> >>> + gic: interrupt-controller@12a00000 { >>> + compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; >> >> One thing for sure, it cannot be both. And given that it is >> an A55-based SoC, it isn't either. It is more likely a GIC400. >> > > Yes, it's GIC-400, thanks for pointing that out. Will fix that in v2. > >>> + #interrupt-cells = <3>; >>> + #address-cells = <0>; >>> + interrupt-controller; >>> + reg = <0x0 0x12a01000 0x1000>, >>> + <0x0 0x12a02000 0x1000>, >> >> This is wrong. It is architecturally set to 8kB. >> > > Nice catch! Actually there is an error (typo?) in SoC's TRM, saying > that Virtual Interface Control Register starts at 0x3000 offset (from > 0x12a00000), where it obviously should be 0x4000, that's probably > where this dts error originates from. Btw, I'm also seeing the same > error in exynos7.dtsi. What's the error exactly? The "Virtual interface control register" offset (3rd region) is set properly to 0x4000 on Exynos7. Also one for the Exynos5433 looks correct. > Though I don't have a TRM for Exynos7 SoCs, so > not sure if I should go ahead and fix that too. Anyway, for Exynos850, > I'll fix that in v2 series. However while we are at addresses - why are you using address-cells 2? It adds everywhere additional 0x0 before actual address. Best regards, Krzysztof _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel