From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 19957C43334 for ; Fri, 1 Jul 2022 12:05:30 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 62697844A6; Fri, 1 Jul 2022 14:05:22 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=rock-chips.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 4AE3084496; Fri, 1 Jul 2022 14:05:20 +0200 (CEST) Received: from mail-m118111.qiye.163.com (mail-m118111.qiye.163.com [115.236.118.111]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 1B5A484490 for ; Fri, 1 Jul 2022 14:05:16 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=rock-chips.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=kever.yang@rock-chips.com Received: from [172.16.12.93] (unknown [58.22.7.114]) by mail-m118111.qiye.163.com (Hmail) with ESMTPA id D51675801EA; Fri, 1 Jul 2022 20:05:02 +0800 (CST) Message-ID: Date: Fri, 1 Jul 2022 20:05:02 +0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.9.1 Subject: Re: [PATCH 3/3] ram: rk3399: Conduct memory training at 400MHz Content-Language: en-US To: Lee Jones , sjg@chromium.org, philipp.tomsich@vrull.eu Cc: cym@rock-chips.com, u-boot@lists.denx.de References: <20220621100729.979275-1-lee.jones@linaro.org> <20220621100729.979275-3-lee.jones@linaro.org> From: Kever Yang In-Reply-To: <20220621100729.979275-3-lee.jones@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-HM-Spam-Status: e1kfGhgUHx5ZQUtXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFJSktLSjdXWS1ZQUlXWQ8JGhUIEh9ZQVkaTB5KVklKSElMShoYGktCQlUTARMWGhIXJB QOD1lXWRgSC1lBWU5DVUlJVUxVSkpPWVdZFhoPEhUdFFlBWU9LSFVKSktISkxVS1kG X-HM-Sender-Digest: e1kMHhlZQR0aFwgeV1kSHx4VD1lBWUc6Pkk6Chw4Qj08HikBHjwPAyE0 MysaFAhVSlVKTU5NTUxMSktISEhCVTMWGhIXVRAeDR4JVQIaFRw7CRQYEFYYExILCFUYFBZFWVdZ EgtZQVlOQ1VJSVVMVUpKT1lXWQgBWUFOSEtDNwY+ X-HM-Tid: 0a81b9a675932eb7kusnd51675801ea X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean On 2022/6/21 18:07, Lee Jones wrote: > Currently the default initialisation frequency is 50MHz. Although > this does appear to be suitable for some LPDDR4 RAM chips, training at > this low frequency has been seen to cause Column errors, leading to > Capacity check errors on others. > > Here we force RAM initialisation to happen at 400MHz before ramping up > to the final value running value of 800MHz after everything has been > successfully configured. > > Link: https://lore.kernel.org/u-boot/Yo4v3jUeHXTovjOH@google.com/ > Suggested-by: YouMin Chen > Signed-off-by: Lee Jones Reviewed-by: Kever Yang Thanks, - Kever > --- > drivers/ram/rockchip/sdram_rk3399.c | 36 +++++++++++++++++------------ > 1 file changed, 21 insertions(+), 15 deletions(-) > > diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c > index 34d6c93f95..b05c5925d5 100644 > --- a/drivers/ram/rockchip/sdram_rk3399.c > +++ b/drivers/ram/rockchip/sdram_rk3399.c > @@ -85,7 +85,7 @@ struct sdram_rk3399_ops { > int (*data_training_first)(struct dram_info *dram, u32 channel, u8 rank, > struct rk3399_sdram_params *sdram); > int (*set_rate_index)(struct dram_info *dram, > - struct rk3399_sdram_params *params); > + struct rk3399_sdram_params *params, u32 ctl_fn); > void (*modify_param)(const struct chan_info *chan, > struct rk3399_sdram_params *params); > struct rk3399_sdram_params * > @@ -1644,7 +1644,8 @@ static int data_training_first(struct dram_info *dram, u32 channel, u8 rank, > } > > static int switch_to_phy_index1(struct dram_info *dram, > - struct rk3399_sdram_params *params) > + struct rk3399_sdram_params *params, > + u32 unused) > { > u32 channel; > u32 *denali_phy; > @@ -2539,26 +2540,25 @@ static int lpddr4_set_ctl(struct dram_info *dram, > } > > static int lpddr4_set_rate(struct dram_info *dram, > - struct rk3399_sdram_params *params) > + struct rk3399_sdram_params *params, > + u32 ctl_fn) > { > - u32 ctl_fn; > u32 phy_fn; > > - for (ctl_fn = 0; ctl_fn < 2; ctl_fn++) { > - phy_fn = lpddr4_get_phy_fn(params, ctl_fn); > + phy_fn = lpddr4_get_phy_fn(params, ctl_fn); > > - lpddr4_set_phy(dram, params, phy_fn, &dfs_cfgs_lpddr4[ctl_fn]); > - lpddr4_set_ctl(dram, params, ctl_fn, > - dfs_cfgs_lpddr4[ctl_fn].base.ddr_freq); > + lpddr4_set_phy(dram, params, phy_fn, &dfs_cfgs_lpddr4[ctl_fn]); > + lpddr4_set_ctl(dram, params, ctl_fn, > + dfs_cfgs_lpddr4[ctl_fn].base.ddr_freq); > > - if (IS_ENABLED(CONFIG_RAM_ROCKCHIP_DEBUG)) > - printf("%s: change freq to %dMHz %d, %d\n", __func__, > - dfs_cfgs_lpddr4[ctl_fn].base.ddr_freq / MHz, > - ctl_fn, phy_fn); > - } > + if (IS_ENABLED(CONFIG_RAM_ROCKCHIP_DEBUG)) > + printf("%s: change freq to %dMHz %d, %d\n", __func__, > + dfs_cfgs_lpddr4[ctl_fn].base.ddr_freq / MHz, > + ctl_fn, phy_fn); > > return 0; > } > + > #endif /* CONFIG_RAM_RK3399_LPDDR4 */ > > /* CS0,n=1 > @@ -2955,6 +2955,12 @@ static int sdram_init(struct dram_info *dram, > params->ch[ch].cap_info.rank = rank; > } > > +#if defined(CONFIG_RAM_RK3399_LPDDR4) > + /* LPDDR4 needs to be trained at 400MHz */ > + lpddr4_set_rate(dram, params, 0); > + params->base.ddr_freq = dfs_cfgs_lpddr4[0].base.ddr_freq / MHz; > +#endif > + > params->base.num_channels = 0; > for (channel = 0; channel < 2; channel++) { > const struct chan_info *chan = &dram->chan[channel]; > @@ -3005,7 +3011,7 @@ static int sdram_init(struct dram_info *dram, > params->base.stride = calculate_stride(params); > dram_all_config(dram, params); > > - ret = dram->ops->set_rate_index(dram, params); > + ret = dram->ops->set_rate_index(dram, params, 1); > if (ret) > return ret; >