* [PATCH v2 00/15] Enable Power Modes Support for SAMA7D65 SoC
@ 2025-02-10 21:13 Ryan.Wanner
2025-02-10 21:13 ` [PATCH v2 01/15] dt-bindings: mfd: syscon: add microchip,sama7d65-ddr3phy Ryan.Wanner
` (14 more replies)
0 siblings, 15 replies; 43+ messages in thread
From: Ryan.Wanner @ 2025-02-10 21:13 UTC (permalink / raw)
To: lee, robh, krzk+dt, conor+dt, claudiu.beznea, sre, nicolas.ferre,
alexandre.belloni, p.zabel
Cc: linux, devicetree, linux-kernel, linux-pm, linux-arm-kernel,
linux-rtc, Ryan Wanner
From: Ryan Wanner <Ryan.Wanner@microchip.com>
This patch set adds support for low power modes for the SAMA7D65 SoC and
the required components and changes for low power modes.
The series includes changes in the asm code to account for the addtional
clocks that are in this SoC.
The Device tree additions are to enable all the components needed to
keep the SoC in low power mode.
There are some DTB check warnings but that is due to the dt-binding not
in the correct .yaml file format.
Changes v1 -> v2:
- Add missing compatible for ddr3phy, it is now in both syscon sets.
- Fix alphabetical ordering for sama7d65.
- Remove the incorrect reorganizing patch.
- Remove sama7g5-rtt as a compatible for sama7d65-rtt and add
sama7d65-rtt as a compatible wake up source in the pm driver.
Li Bin (1):
ARM: at91: pm: fix at91_suspend_finish for ZQ calibration
Ryan Wanner (14):
dt-bindings: mfd: syscon: add microchip,sama7d65-ddr3phy
dt-bindings: mfd: syscon: add microchip,sama7d65-sfrbu
dt-bindings: sram: Add microchip,sama7d65-sram
dt-bindings: power: reset: atmel,sama5d2-shdwc: Add
microchip,sama7d65-shdwc
dt-bindings: reset: atmel,at91sam9260-reset: add
microchip,sama7d65-rstc
dt-bindings: rtc: at91rm9200: add microchip,sama7d65-rtc
dt-bindings: at91rm9260-rtt: add microchip,sama7d65-rtt
ARM: at91: Add PM support to sama7d65
ARM: at91: pm: add DT compatible support for sama7d65
ARM: at91: PM: Add Backup mode for SAMA7D65
ARM: at91: pm: Enable ULP0 for SAMA7D65
power: reset: at91-sama5d2_shdwc: Add sama7d65 PMC
ARM: dts: microchip: sama7d65: Add Reset and Shutdown and PM support
ARM: dts: microchip: add shutdown controller and rtt timer
.../devicetree/bindings/mfd/syscon.yaml | 3 +
.../power/reset/atmel,sama5d2-shdwc.yaml | 5 +
.../reset/atmel,at91sam9260-reset.yaml | 5 +
.../bindings/rtc/atmel,at91rm9200-rtc.yaml | 3 +
.../bindings/rtc/atmel,at91sam9260-rtt.yaml | 3 +
.../devicetree/bindings/sram/sram.yaml | 1 +
.../dts/microchip/at91-sama7d65_curiosity.dts | 14 +++
arch/arm/boot/dts/microchip/sama7d65.dtsi | 77 +++++++++++++++
arch/arm/mach-at91/Kconfig | 1 +
arch/arm/mach-at91/pm.c | 54 ++++++++---
arch/arm/mach-at91/pm.h | 1 +
arch/arm/mach-at91/pm_data-offsets.c | 2 +
arch/arm/mach-at91/pm_suspend.S | 97 +++++++++++++++++--
drivers/power/reset/at91-sama5d2_shdwc.c | 1 +
14 files changed, 245 insertions(+), 22 deletions(-)
--
2.43.0
^ permalink raw reply [flat|nested] 43+ messages in thread
* [PATCH v2 01/15] dt-bindings: mfd: syscon: add microchip,sama7d65-ddr3phy
2025-02-10 21:13 [PATCH v2 00/15] Enable Power Modes Support for SAMA7D65 SoC Ryan.Wanner
@ 2025-02-10 21:13 ` Ryan.Wanner
2025-02-11 8:12 ` Krzysztof Kozlowski
2025-02-10 21:13 ` [PATCH v2 02/15] dt-bindings: mfd: syscon: add microchip,sama7d65-sfrbu Ryan.Wanner
` (13 subsequent siblings)
14 siblings, 1 reply; 43+ messages in thread
From: Ryan.Wanner @ 2025-02-10 21:13 UTC (permalink / raw)
To: lee, robh, krzk+dt, conor+dt, claudiu.beznea, sre, nicolas.ferre,
alexandre.belloni, p.zabel
Cc: linux, devicetree, linux-kernel, linux-pm, linux-arm-kernel,
linux-rtc, Ryan Wanner
From: Ryan Wanner <Ryan.Wanner@microchip.com>
Add SAMA7D65 DDR3phy compatible to DT bindings documentation
Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com>
---
Documentation/devicetree/bindings/mfd/syscon.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/mfd/syscon.yaml b/Documentation/devicetree/bindings/mfd/syscon.yaml
index b414de4fa779b..51d896c88dafa 100644
--- a/Documentation/devicetree/bindings/mfd/syscon.yaml
+++ b/Documentation/devicetree/bindings/mfd/syscon.yaml
@@ -90,6 +90,7 @@ select:
- microchip,lan966x-cpu-syscon
- microchip,mpfs-sysreg-scb
- microchip,sam9x60-sfr
+ - microchip,sama7d65-ddr3phy
- microchip,sama7g5-ddr3phy
- mscc,ocelot-cpu-syscon
- mstar,msc313-pmsleep
@@ -188,6 +189,7 @@ properties:
- microchip,lan966x-cpu-syscon
- microchip,mpfs-sysreg-scb
- microchip,sam9x60-sfr
+ - microchip,sama7d65-ddr3phy
- microchip,sama7g5-ddr3phy
- mscc,ocelot-cpu-syscon
- mstar,msc313-pmsleep
--
2.43.0
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [PATCH v2 02/15] dt-bindings: mfd: syscon: add microchip,sama7d65-sfrbu
2025-02-10 21:13 [PATCH v2 00/15] Enable Power Modes Support for SAMA7D65 SoC Ryan.Wanner
2025-02-10 21:13 ` [PATCH v2 01/15] dt-bindings: mfd: syscon: add microchip,sama7d65-ddr3phy Ryan.Wanner
@ 2025-02-10 21:13 ` Ryan.Wanner
2025-02-11 8:14 ` Krzysztof Kozlowski
2025-02-10 21:13 ` [PATCH v2 03/15] dt-bindings: sram: Add microchip,sama7d65-sram Ryan.Wanner
` (12 subsequent siblings)
14 siblings, 1 reply; 43+ messages in thread
From: Ryan.Wanner @ 2025-02-10 21:13 UTC (permalink / raw)
To: lee, robh, krzk+dt, conor+dt, claudiu.beznea, sre, nicolas.ferre,
alexandre.belloni, p.zabel
Cc: linux, devicetree, linux-kernel, linux-pm, linux-arm-kernel,
linux-rtc, Ryan Wanner
From: Ryan Wanner <Ryan.Wanner@microchip.com>
Add SAMA7D65 SFRBU compatible string to DT bindings documentation
Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com>
---
Documentation/devicetree/bindings/mfd/syscon.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/mfd/syscon.yaml b/Documentation/devicetree/bindings/mfd/syscon.yaml
index 51d896c88dafa..727292ffe092e 100644
--- a/Documentation/devicetree/bindings/mfd/syscon.yaml
+++ b/Documentation/devicetree/bindings/mfd/syscon.yaml
@@ -91,6 +91,7 @@ select:
- microchip,mpfs-sysreg-scb
- microchip,sam9x60-sfr
- microchip,sama7d65-ddr3phy
+ - microchip,sama7d65-sfrbu
- microchip,sama7g5-ddr3phy
- mscc,ocelot-cpu-syscon
- mstar,msc313-pmsleep
--
2.43.0
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [PATCH v2 03/15] dt-bindings: sram: Add microchip,sama7d65-sram
2025-02-10 21:13 [PATCH v2 00/15] Enable Power Modes Support for SAMA7D65 SoC Ryan.Wanner
2025-02-10 21:13 ` [PATCH v2 01/15] dt-bindings: mfd: syscon: add microchip,sama7d65-ddr3phy Ryan.Wanner
2025-02-10 21:13 ` [PATCH v2 02/15] dt-bindings: mfd: syscon: add microchip,sama7d65-sfrbu Ryan.Wanner
@ 2025-02-10 21:13 ` Ryan.Wanner
2025-02-10 21:13 ` [PATCH v2 04/15] dt-bindings: power: reset: atmel,sama5d2-shdwc: Add microchip,sama7d65-shdwc Ryan.Wanner
` (11 subsequent siblings)
14 siblings, 0 replies; 43+ messages in thread
From: Ryan.Wanner @ 2025-02-10 21:13 UTC (permalink / raw)
To: lee, robh, krzk+dt, conor+dt, claudiu.beznea, sre, nicolas.ferre,
alexandre.belloni, p.zabel
Cc: linux, devicetree, linux-kernel, linux-pm, linux-arm-kernel,
linux-rtc, Ryan Wanner
From: Ryan Wanner <Ryan.Wanner@microchip.com>
Add microchip,sama7d65-sram compatibility to DT binding documentation.
Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
---
Documentation/devicetree/bindings/sram/sram.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/sram/sram.yaml b/Documentation/devicetree/bindings/sram/sram.yaml
index 7c1337e159f23..3071c5075ee48 100644
--- a/Documentation/devicetree/bindings/sram/sram.yaml
+++ b/Documentation/devicetree/bindings/sram/sram.yaml
@@ -31,6 +31,7 @@ properties:
- amlogic,meson-gxbb-sram
- arm,juno-sram-ns
- atmel,sama5d2-securam
+ - microchip,sama7d65-securam
- nvidia,tegra186-sysram
- nvidia,tegra194-sysram
- nvidia,tegra234-sysram
--
2.43.0
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [PATCH v2 04/15] dt-bindings: power: reset: atmel,sama5d2-shdwc: Add microchip,sama7d65-shdwc
2025-02-10 21:13 [PATCH v2 00/15] Enable Power Modes Support for SAMA7D65 SoC Ryan.Wanner
` (2 preceding siblings ...)
2025-02-10 21:13 ` [PATCH v2 03/15] dt-bindings: sram: Add microchip,sama7d65-sram Ryan.Wanner
@ 2025-02-10 21:13 ` Ryan.Wanner
2025-02-10 21:13 ` [PATCH v2 05/15] dt-bindings: reset: atmel,at91sam9260-reset: add microchip,sama7d65-rstc Ryan.Wanner
` (10 subsequent siblings)
14 siblings, 0 replies; 43+ messages in thread
From: Ryan.Wanner @ 2025-02-10 21:13 UTC (permalink / raw)
To: lee, robh, krzk+dt, conor+dt, claudiu.beznea, sre, nicolas.ferre,
alexandre.belloni, p.zabel
Cc: linux, devicetree, linux-kernel, linux-pm, linux-arm-kernel,
linux-rtc, Ryan Wanner
From: Ryan Wanner <Ryan.Wanner@microchip.com>
Add SAMA7D65 SHDWC compatible to DT bindings documentation
Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
---
.../devicetree/bindings/power/reset/atmel,sama5d2-shdwc.yaml | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/power/reset/atmel,sama5d2-shdwc.yaml b/Documentation/devicetree/bindings/power/reset/atmel,sama5d2-shdwc.yaml
index 8c58e12cdb600..2930607480ea2 100644
--- a/Documentation/devicetree/bindings/power/reset/atmel,sama5d2-shdwc.yaml
+++ b/Documentation/devicetree/bindings/power/reset/atmel,sama5d2-shdwc.yaml
@@ -16,6 +16,11 @@ description: |
properties:
compatible:
oneOf:
+ - items:
+ - enum:
+ - microchip,sama7d65-shdwc
+ - const: microchip,sama7g5-shdwc
+ - const: syscon
- items:
- const: microchip,sama7g5-shdwc
- const: syscon
--
2.43.0
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [PATCH v2 05/15] dt-bindings: reset: atmel,at91sam9260-reset: add microchip,sama7d65-rstc
2025-02-10 21:13 [PATCH v2 00/15] Enable Power Modes Support for SAMA7D65 SoC Ryan.Wanner
` (3 preceding siblings ...)
2025-02-10 21:13 ` [PATCH v2 04/15] dt-bindings: power: reset: atmel,sama5d2-shdwc: Add microchip,sama7d65-shdwc Ryan.Wanner
@ 2025-02-10 21:13 ` Ryan.Wanner
2025-02-14 8:27 ` Krzysztof Kozlowski
2025-02-10 21:13 ` [PATCH v2 06/15] dt-bindings: rtc: at91rm9200: add microchip,sama7d65-rtc Ryan.Wanner
` (9 subsequent siblings)
14 siblings, 1 reply; 43+ messages in thread
From: Ryan.Wanner @ 2025-02-10 21:13 UTC (permalink / raw)
To: lee, robh, krzk+dt, conor+dt, claudiu.beznea, sre, nicolas.ferre,
alexandre.belloni, p.zabel
Cc: linux, devicetree, linux-kernel, linux-pm, linux-arm-kernel,
linux-rtc, Ryan Wanner
From: Ryan Wanner <Ryan.Wanner@microchip.com>
Add SAMA7D65 RSTC compatible to DT bindings documentation. The
sama7d65-rstc is compatible with the sama7g5-rstc.
Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com>
---
.../devicetree/bindings/reset/atmel,at91sam9260-reset.yaml | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/reset/atmel,at91sam9260-reset.yaml b/Documentation/devicetree/bindings/reset/atmel,at91sam9260-reset.yaml
index 98465d26949ee..a1c21c3880f9d 100644
--- a/Documentation/devicetree/bindings/reset/atmel,at91sam9260-reset.yaml
+++ b/Documentation/devicetree/bindings/reset/atmel,at91sam9260-reset.yaml
@@ -23,6 +23,11 @@ properties:
- atmel,sama5d3-rstc
- microchip,sam9x60-rstc
- microchip,sama7g5-rstc
+
+ - items:
+ - const: microchip,sama7d65-rstc
+ - const: microchip,sama7g5-rstc
+
- items:
- const: atmel,sama5d3-rstc
- const: atmel,at91sam9g45-rstc
--
2.43.0
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [PATCH v2 06/15] dt-bindings: rtc: at91rm9200: add microchip,sama7d65-rtc
2025-02-10 21:13 [PATCH v2 00/15] Enable Power Modes Support for SAMA7D65 SoC Ryan.Wanner
` (4 preceding siblings ...)
2025-02-10 21:13 ` [PATCH v2 05/15] dt-bindings: reset: atmel,at91sam9260-reset: add microchip,sama7d65-rstc Ryan.Wanner
@ 2025-02-10 21:13 ` Ryan.Wanner
2025-02-12 8:18 ` Claudiu Beznea
2025-02-14 8:27 ` Krzysztof Kozlowski
2025-02-10 21:13 ` [PATCH v2 07/15] dt-bindings: at91rm9260-rtt: add microchip,sama7d65-rtt Ryan.Wanner
` (8 subsequent siblings)
14 siblings, 2 replies; 43+ messages in thread
From: Ryan.Wanner @ 2025-02-10 21:13 UTC (permalink / raw)
To: lee, robh, krzk+dt, conor+dt, claudiu.beznea, sre, nicolas.ferre,
alexandre.belloni, p.zabel
Cc: linux, devicetree, linux-kernel, linux-pm, linux-arm-kernel,
linux-rtc, Ryan Wanner
From: Ryan Wanner <Ryan.Wanner@microchip.com>
Add SAMA7D65 RTC compatible to DT bindings documentation.
Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com>
---
.../devicetree/bindings/rtc/atmel,at91rm9200-rtc.yaml | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.yaml b/Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.yaml
index c8bb2eef442dd..0c878331170b4 100644
--- a/Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.yaml
+++ b/Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.yaml
@@ -25,6 +25,9 @@ properties:
- items:
- const: microchip,sam9x7-rtc
- const: microchip,sam9x60-rtc
+ - items:
+ - const: microchip,sama7d65-rtc
+ - const: microchip,sam9x60-rtc
reg:
maxItems: 1
--
2.43.0
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [PATCH v2 07/15] dt-bindings: at91rm9260-rtt: add microchip,sama7d65-rtt
2025-02-10 21:13 [PATCH v2 00/15] Enable Power Modes Support for SAMA7D65 SoC Ryan.Wanner
` (5 preceding siblings ...)
2025-02-10 21:13 ` [PATCH v2 06/15] dt-bindings: rtc: at91rm9200: add microchip,sama7d65-rtc Ryan.Wanner
@ 2025-02-10 21:13 ` Ryan.Wanner
2025-02-12 8:18 ` Claudiu Beznea
2025-02-14 8:28 ` Krzysztof Kozlowski
2025-02-10 21:13 ` [PATCH v2 08/15] ARM: at91: Add PM support to sama7d65 Ryan.Wanner
` (7 subsequent siblings)
14 siblings, 2 replies; 43+ messages in thread
From: Ryan.Wanner @ 2025-02-10 21:13 UTC (permalink / raw)
To: lee, robh, krzk+dt, conor+dt, claudiu.beznea, sre, nicolas.ferre,
alexandre.belloni, p.zabel
Cc: linux, devicetree, linux-kernel, linux-pm, linux-arm-kernel,
linux-rtc, Ryan Wanner
From: Ryan Wanner <Ryan.Wanner@microchip.com>
Add SAMA7D65 RTT compatible to DT bindings documentation.
Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com>
---
.../devicetree/bindings/rtc/atmel,at91sam9260-rtt.yaml | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/rtc/atmel,at91sam9260-rtt.yaml b/Documentation/devicetree/bindings/rtc/atmel,at91sam9260-rtt.yaml
index a7f6c1d1a08ab..48a2e013a6b24 100644
--- a/Documentation/devicetree/bindings/rtc/atmel,at91sam9260-rtt.yaml
+++ b/Documentation/devicetree/bindings/rtc/atmel,at91sam9260-rtt.yaml
@@ -23,6 +23,9 @@ properties:
- microchip,sam9x60-rtt
- microchip,sam9x7-rtt
- const: atmel,at91sam9260-rtt
+ - items:
+ - const: microchip,sama7d65-rtt
+ - const: atmel,at91sam9260-rtt
- items:
- const: microchip,sama7g5-rtt
- const: microchip,sam9x60-rtt
--
2.43.0
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [PATCH v2 08/15] ARM: at91: Add PM support to sama7d65
2025-02-10 21:13 [PATCH v2 00/15] Enable Power Modes Support for SAMA7D65 SoC Ryan.Wanner
` (6 preceding siblings ...)
2025-02-10 21:13 ` [PATCH v2 07/15] dt-bindings: at91rm9260-rtt: add microchip,sama7d65-rtt Ryan.Wanner
@ 2025-02-10 21:13 ` Ryan.Wanner
2025-02-10 21:13 ` [PATCH v2 09/15] ARM: at91: pm: fix at91_suspend_finish for ZQ calibration Ryan.Wanner
` (6 subsequent siblings)
14 siblings, 0 replies; 43+ messages in thread
From: Ryan.Wanner @ 2025-02-10 21:13 UTC (permalink / raw)
To: lee, robh, krzk+dt, conor+dt, claudiu.beznea, sre, nicolas.ferre,
alexandre.belloni, p.zabel
Cc: linux, devicetree, linux-kernel, linux-pm, linux-arm-kernel,
linux-rtc, Ryan Wanner
From: Ryan Wanner <Ryan.Wanner@microchip.com>
Add PM support to SAMA7D65 SoC.
Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com>
---
arch/arm/mach-at91/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 04bd91c72521c..f3ff1220c0fb0 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -65,6 +65,7 @@ config SOC_SAMA7D65
select HAVE_AT91_SAM9X60_PLL
select HAVE_AT91_USB_CLK
select HAVE_AT91_UTMI
+ select PM_OPP
select SOC_SAMA7
help
Select this if you are using one of Microchip's SAMA7D65 family SoC.
--
2.43.0
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [PATCH v2 09/15] ARM: at91: pm: fix at91_suspend_finish for ZQ calibration
2025-02-10 21:13 [PATCH v2 00/15] Enable Power Modes Support for SAMA7D65 SoC Ryan.Wanner
` (7 preceding siblings ...)
2025-02-10 21:13 ` [PATCH v2 08/15] ARM: at91: Add PM support to sama7d65 Ryan.Wanner
@ 2025-02-10 21:13 ` Ryan.Wanner
2025-02-12 8:17 ` Claudiu Beznea
2025-02-10 21:13 ` [PATCH v2 10/15] ARM: at91: pm: add DT compatible support for sama7d65 Ryan.Wanner
` (5 subsequent siblings)
14 siblings, 1 reply; 43+ messages in thread
From: Ryan.Wanner @ 2025-02-10 21:13 UTC (permalink / raw)
To: lee, robh, krzk+dt, conor+dt, claudiu.beznea, sre, nicolas.ferre,
alexandre.belloni, p.zabel
Cc: linux, devicetree, linux-kernel, linux-pm, linux-arm-kernel,
linux-rtc, Li Bin, Ryan Wanner, Durai Manickam KR, Andrei Simion
From: Li Bin <bin.li@microchip.com>
For sama7g5 and sama7d65 backup mode, we encountered a "ZQ calibrate error"
during recalibrating the impedance in BootStrap.
We found that the impedance value saved in at91_suspend_finish() before
the DDR entered self-refresh mode did not match the resistor values. The
ZDATA field in the DDR3PHY_ZQ0CR0 register uses a modified gray code to
select the different impedance setting.
But these gray code are incorrect, a workaournd from design team fixed the
bug in the calibration logic. The ZDATA contains four independent impedance
elements, but the algorithm combined the four elements into one. The elements
were fixed using properly shifted offsets.
Signed-off-by: Li Bin <bin.li@microchip.com>
[nicolas.ferre@microchip.com: fix indentation and combine 2 patches]
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Tested-by: Ryan Wanner <Ryan.Wanner@microchip.com>
Tested-by: Durai Manickam KR <durai.manickamkr@microchip.com>
Tested-by: Andrei Simion <andrei.simion@microchip.com>
---
arch/arm/mach-at91/pm.c | 21 +++++++++++----------
1 file changed, 11 insertions(+), 10 deletions(-)
diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
index 05a1547642b60..6c3e6aa22606f 100644
--- a/arch/arm/mach-at91/pm.c
+++ b/arch/arm/mach-at91/pm.c
@@ -545,11 +545,12 @@ extern u32 at91_pm_suspend_in_sram_sz;
static int at91_suspend_finish(unsigned long val)
{
- unsigned char modified_gray_code[] = {
- 0x00, 0x01, 0x02, 0x03, 0x06, 0x07, 0x04, 0x05, 0x0c, 0x0d,
- 0x0e, 0x0f, 0x0a, 0x0b, 0x08, 0x09, 0x18, 0x19, 0x1a, 0x1b,
- 0x1e, 0x1f, 0x1c, 0x1d, 0x14, 0x15, 0x16, 0x17, 0x12, 0x13,
- 0x10, 0x11,
+ /* SYNOPSYS workaround to fix a bug in the calibration logic */
+ unsigned char modified_fix_code[] = {
+ 0x00, 0x01, 0x01, 0x06, 0x07, 0x0c, 0x06, 0x07, 0x0b, 0x18,
+ 0x0a, 0x0b, 0x0c, 0x0d, 0x0d, 0x0a, 0x13, 0x13, 0x12, 0x13,
+ 0x14, 0x15, 0x15, 0x12, 0x18, 0x19, 0x19, 0x1e, 0x1f, 0x14,
+ 0x1e, 0x1f,
};
unsigned int tmp, index;
int i;
@@ -560,25 +561,25 @@ static int at91_suspend_finish(unsigned long val)
* restore the ZQ0SR0 with the value saved here. But the
* calibration is buggy and restoring some values from ZQ0SR0
* is forbidden and risky thus we need to provide processed
- * values for these (modified gray code values).
+ * values for these.
*/
tmp = readl(soc_pm.data.ramc_phy + DDR3PHY_ZQ0SR0);
/* Store pull-down output impedance select. */
index = (tmp >> DDR3PHY_ZQ0SR0_PDO_OFF) & 0x1f;
- soc_pm.bu->ddr_phy_calibration[0] = modified_gray_code[index];
+ soc_pm.bu->ddr_phy_calibration[0] = modified_fix_code[index] << DDR3PHY_ZQ0SR0_PDO_OFF;
/* Store pull-up output impedance select. */
index = (tmp >> DDR3PHY_ZQ0SR0_PUO_OFF) & 0x1f;
- soc_pm.bu->ddr_phy_calibration[0] |= modified_gray_code[index];
+ soc_pm.bu->ddr_phy_calibration[0] |= modified_fix_code[index] << DDR3PHY_ZQ0SR0_PUO_OFF;
/* Store pull-down on-die termination impedance select. */
index = (tmp >> DDR3PHY_ZQ0SR0_PDODT_OFF) & 0x1f;
- soc_pm.bu->ddr_phy_calibration[0] |= modified_gray_code[index];
+ soc_pm.bu->ddr_phy_calibration[0] |= modified_fix_code[index] << DDR3PHY_ZQ0SR0_PDODT_OFF;
/* Store pull-up on-die termination impedance select. */
index = (tmp >> DDR3PHY_ZQ0SRO_PUODT_OFF) & 0x1f;
- soc_pm.bu->ddr_phy_calibration[0] |= modified_gray_code[index];
+ soc_pm.bu->ddr_phy_calibration[0] |= modified_fix_code[index] << DDR3PHY_ZQ0SRO_PUODT_OFF;
/*
* The 1st 8 words of memory might get corrupted in the process
--
2.43.0
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [PATCH v2 10/15] ARM: at91: pm: add DT compatible support for sama7d65
2025-02-10 21:13 [PATCH v2 00/15] Enable Power Modes Support for SAMA7D65 SoC Ryan.Wanner
` (8 preceding siblings ...)
2025-02-10 21:13 ` [PATCH v2 09/15] ARM: at91: pm: fix at91_suspend_finish for ZQ calibration Ryan.Wanner
@ 2025-02-10 21:13 ` Ryan.Wanner
2025-02-12 8:20 ` Claudiu Beznea
2025-02-10 21:13 ` [PATCH v2 11/15] ARM: at91: PM: Add Backup mode for SAMA7D65 Ryan.Wanner
` (4 subsequent siblings)
14 siblings, 1 reply; 43+ messages in thread
From: Ryan.Wanner @ 2025-02-10 21:13 UTC (permalink / raw)
To: lee, robh, krzk+dt, conor+dt, claudiu.beznea, sre, nicolas.ferre,
alexandre.belloni, p.zabel
Cc: linux, devicetree, linux-kernel, linux-pm, linux-arm-kernel,
linux-rtc, Ryan Wanner
From: Ryan Wanner <Ryan.Wanner@microchip.com>
Add support for SAMA7D65 new compatible strings in pm.c file for wakeup source
IDs and PMC.
This is the first bits of PM for this new SoC. PM depends on other patches.
Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com>
[nicolas.ferre@microchip.com: split patch and address only the pm.c changes]
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
---
arch/arm/mach-at91/pm.c | 10 +++++++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
index 6c3e6aa22606f..1eec68e92f8d8 100644
--- a/arch/arm/mach-at91/pm.c
+++ b/arch/arm/mach-at91/pm.c
@@ -222,13 +222,16 @@ static const struct of_device_id sam9x60_ws_ids[] = {
{ /* sentinel */ }
};
-static const struct of_device_id sama7g5_ws_ids[] = {
- { .compatible = "microchip,sama7g5-rtc", .data = &ws_info[1] },
+static const struct of_device_id sama7_ws_ids[] = {
+ { .compatible = "microchip,sama7d65-rtc", .data = &ws_info[1] },
+ { .compatible = "microchip,sama7g5-rtc", .data = &ws_info[1] },
{ .compatible = "microchip,sama7g5-ohci", .data = &ws_info[2] },
{ .compatible = "usb-ohci", .data = &ws_info[2] },
{ .compatible = "atmel,at91sam9g45-ehci", .data = &ws_info[2] },
{ .compatible = "usb-ehci", .data = &ws_info[2] },
+ { .compatible = "microchip,sama7d65-sdhci", .data = &ws_info[3] },
{ .compatible = "microchip,sama7g5-sdhci", .data = &ws_info[3] },
+ { .compatible = "microchip,sama7d65-rtt", .data = &ws_info[4] },
{ .compatible = "microchip,sama7g5-rtt", .data = &ws_info[4] },
{ /* sentinel */ }
};
@@ -1379,6 +1382,7 @@ static const struct of_device_id atmel_pmc_ids[] __initconst = {
{ .compatible = "atmel,sama5d2-pmc", .data = &pmc_infos[1] },
{ .compatible = "microchip,sam9x60-pmc", .data = &pmc_infos[4] },
{ .compatible = "microchip,sam9x7-pmc", .data = &pmc_infos[4] },
+ { .compatible = "microchip,sama7d65-pmc", .data = &pmc_infos[4] },
{ .compatible = "microchip,sama7g5-pmc", .data = &pmc_infos[5] },
{ /* sentinel */ },
};
@@ -1672,7 +1676,7 @@ void __init sama7_pm_init(void)
at91_pm_modes_init(iomaps, ARRAY_SIZE(iomaps));
at91_pm_init(NULL);
- soc_pm.ws_ids = sama7g5_ws_ids;
+ soc_pm.ws_ids = sama7_ws_ids;
soc_pm.config_pmc_ws = at91_sam9x60_config_pmc_ws;
soc_pm.sfrbu_regs.pswbu.key = (0x4BD20C << 8);
--
2.43.0
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [PATCH v2 11/15] ARM: at91: PM: Add Backup mode for SAMA7D65
2025-02-10 21:13 [PATCH v2 00/15] Enable Power Modes Support for SAMA7D65 SoC Ryan.Wanner
` (9 preceding siblings ...)
2025-02-10 21:13 ` [PATCH v2 10/15] ARM: at91: pm: add DT compatible support for sama7d65 Ryan.Wanner
@ 2025-02-10 21:13 ` Ryan.Wanner
2025-02-12 8:15 ` Claudiu Beznea
2025-02-10 21:13 ` [PATCH v2 12/15] ARM: at91: pm: Enable ULP0 " Ryan.Wanner
` (3 subsequent siblings)
14 siblings, 1 reply; 43+ messages in thread
From: Ryan.Wanner @ 2025-02-10 21:13 UTC (permalink / raw)
To: lee, robh, krzk+dt, conor+dt, claudiu.beznea, sre, nicolas.ferre,
alexandre.belloni, p.zabel
Cc: linux, devicetree, linux-kernel, linux-pm, linux-arm-kernel,
linux-rtc, Ryan Wanner
From: Ryan Wanner <Ryan.Wanner@microchip.com>
Add config check that enables Backup mode for SAMA7D65 SoC.
Add SHDWC_SR read to clear the status bits once finished exiting low
power modes. This is only for SAMA7D65 SoCs.
Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com>
---
arch/arm/mach-at91/pm.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
index 1eec68e92f8d8..55cab31ce1ecb 100644
--- a/arch/arm/mach-at91/pm.c
+++ b/arch/arm/mach-at91/pm.c
@@ -707,6 +707,9 @@ static int at91_pm_enter(suspend_state_t state)
static void at91_pm_end(void)
{
at91_pm_config_ws(soc_pm.data.mode, false);
+
+ if (IS_ENABLED(CONFIG_SOC_SAMA7D65))
+ readl(soc_pm.data.shdwc + 0x08);
}
@@ -1065,7 +1068,8 @@ static int __init at91_pm_backup_init(void)
int ret = -ENODEV, located = 0;
if (!IS_ENABLED(CONFIG_SOC_SAMA5D2) &&
- !IS_ENABLED(CONFIG_SOC_SAMA7G5))
+ !IS_ENABLED(CONFIG_SOC_SAMA7G5) &&
+ !IS_ENABLED(CONFIG_SOC_SAMA7D65))
return -EPERM;
if (!at91_is_pm_mode_active(AT91_PM_BACKUP))
--
2.43.0
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [PATCH v2 12/15] ARM: at91: pm: Enable ULP0 for SAMA7D65
2025-02-10 21:13 [PATCH v2 00/15] Enable Power Modes Support for SAMA7D65 SoC Ryan.Wanner
` (10 preceding siblings ...)
2025-02-10 21:13 ` [PATCH v2 11/15] ARM: at91: PM: Add Backup mode for SAMA7D65 Ryan.Wanner
@ 2025-02-10 21:13 ` Ryan.Wanner
2025-02-13 8:20 ` Claudiu Beznea
2025-02-10 21:13 ` [PATCH v2 13/15] power: reset: at91-sama5d2_shdwc: Add sama7d65 PMC Ryan.Wanner
` (2 subsequent siblings)
14 siblings, 1 reply; 43+ messages in thread
From: Ryan.Wanner @ 2025-02-10 21:13 UTC (permalink / raw)
To: lee, robh, krzk+dt, conor+dt, claudiu.beznea, sre, nicolas.ferre,
alexandre.belloni, p.zabel
Cc: linux, devicetree, linux-kernel, linux-pm, linux-arm-kernel,
linux-rtc, Ryan Wanner
From: Ryan Wanner <Ryan.Wanner@microchip.com>
New clocks are saved to enable ULP0 for SAMA7D65 because this SoC has a
total of 10 main clocks that need to be saved for ULP0 mode.
Add mck_count member to at91_pm_data, this will be used to determine
how many mcks need to be saved. In the mck_count member will also make
sure that no unnecessary clock settings are written during
mck_ps_restore.
Add SHDWC to ULP0 mapping to clear the SHDWC status after exiting low
power modes.
Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com>
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
---
arch/arm/mach-at91/pm.c | 19 +++++-
arch/arm/mach-at91/pm.h | 1 +
arch/arm/mach-at91/pm_data-offsets.c | 2 +
arch/arm/mach-at91/pm_suspend.S | 97 ++++++++++++++++++++++++++--
4 files changed, 110 insertions(+), 9 deletions(-)
diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
index 55cab31ce1ecb..50bada544eede 100644
--- a/arch/arm/mach-at91/pm.c
+++ b/arch/arm/mach-at91/pm.c
@@ -1337,6 +1337,7 @@ struct pmc_info {
unsigned long uhp_udp_mask;
unsigned long mckr;
unsigned long version;
+ unsigned long mck_count;
};
static const struct pmc_info pmc_infos[] __initconst = {
@@ -1344,30 +1345,42 @@ static const struct pmc_info pmc_infos[] __initconst = {
.uhp_udp_mask = AT91RM9200_PMC_UHP | AT91RM9200_PMC_UDP,
.mckr = 0x30,
.version = AT91_PMC_V1,
+ .mck_count = 1,
},
{
.uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP,
.mckr = 0x30,
.version = AT91_PMC_V1,
+ .mck_count = 1,
},
{
.uhp_udp_mask = AT91SAM926x_PMC_UHP,
.mckr = 0x30,
.version = AT91_PMC_V1,
+ .mck_count = 1,
},
{ .uhp_udp_mask = 0,
.mckr = 0x30,
.version = AT91_PMC_V1,
+ .mck_count = 1,
},
{
.uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP,
.mckr = 0x28,
.version = AT91_PMC_V2,
+ .mck_count = 1,
},
{
.mckr = 0x28,
.version = AT91_PMC_V2,
+ .mck_count = 5,
+ },
+ {
+ .uhp_udp_mask = AT91SAM926x_PMC_UHP,
+ .mckr = 0x28,
+ .version = AT91_PMC_V2,
+ .mck_count = 10,
},
};
@@ -1386,7 +1399,7 @@ static const struct of_device_id atmel_pmc_ids[] __initconst = {
{ .compatible = "atmel,sama5d2-pmc", .data = &pmc_infos[1] },
{ .compatible = "microchip,sam9x60-pmc", .data = &pmc_infos[4] },
{ .compatible = "microchip,sam9x7-pmc", .data = &pmc_infos[4] },
- { .compatible = "microchip,sama7d65-pmc", .data = &pmc_infos[4] },
+ { .compatible = "microchip,sama7d65-pmc", .data = &pmc_infos[6] },
{ .compatible = "microchip,sama7g5-pmc", .data = &pmc_infos[5] },
{ /* sentinel */ },
};
@@ -1457,6 +1470,7 @@ static void __init at91_pm_init(void (*pm_idle)(void))
soc_pm.data.uhp_udp_mask = pmc->uhp_udp_mask;
soc_pm.data.pmc_mckr_offset = pmc->mckr;
soc_pm.data.pmc_version = pmc->version;
+ soc_pm.data.pmc_mck_count = pmc->mck_count;
if (pm_idle)
arm_pm_idle = pm_idle;
@@ -1659,7 +1673,8 @@ void __init sama7_pm_init(void)
AT91_PM_STANDBY, AT91_PM_ULP0, AT91_PM_ULP1, AT91_PM_BACKUP,
};
static const u32 iomaps[] __initconst = {
- [AT91_PM_ULP0] = AT91_PM_IOMAP(SFRBU),
+ [AT91_PM_ULP0] = AT91_PM_IOMAP(SFRBU) |
+ AT91_PM_IOMAP(SHDWC),
[AT91_PM_ULP1] = AT91_PM_IOMAP(SFRBU) |
AT91_PM_IOMAP(SHDWC) |
AT91_PM_IOMAP(ETHC),
diff --git a/arch/arm/mach-at91/pm.h b/arch/arm/mach-at91/pm.h
index 53bdc9000e447..ccde9c8728c27 100644
--- a/arch/arm/mach-at91/pm.h
+++ b/arch/arm/mach-at91/pm.h
@@ -39,6 +39,7 @@ struct at91_pm_data {
unsigned int suspend_mode;
unsigned int pmc_mckr_offset;
unsigned int pmc_version;
+ unsigned int pmc_mck_count;
};
#endif
diff --git a/arch/arm/mach-at91/pm_data-offsets.c b/arch/arm/mach-at91/pm_data-offsets.c
index 40bd4e8fe40a5..59a4838038381 100644
--- a/arch/arm/mach-at91/pm_data-offsets.c
+++ b/arch/arm/mach-at91/pm_data-offsets.c
@@ -18,6 +18,8 @@ int main(void)
pmc_mckr_offset));
DEFINE(PM_DATA_PMC_VERSION, offsetof(struct at91_pm_data,
pmc_version));
+ DEFINE(PM_DATA_PMC_MCK_COUNT, offsetof(struct at91_pm_data,
+ pmc_mck_count));
return 0;
}
diff --git a/arch/arm/mach-at91/pm_suspend.S b/arch/arm/mach-at91/pm_suspend.S
index e5869cca5e791..2bbcbb26adb28 100644
--- a/arch/arm/mach-at91/pm_suspend.S
+++ b/arch/arm/mach-at91/pm_suspend.S
@@ -814,17 +814,19 @@ sr_dis_exit:
.endm
/**
- * at91_mckx_ps_enable: save MCK1..4 settings and switch it to main clock
+ * at91_mckx_ps_enable: save MCK settings and switch it to main clock
*
- * Side effects: overwrites tmp1, tmp2
+ * Side effects: overwrites tmp1, tmp2, tmp3
*/
.macro at91_mckx_ps_enable
#ifdef CONFIG_SOC_SAMA7
ldr pmc, .pmc_base
+ ldr tmp3, .mck_count
- /* There are 4 MCKs we need to handle: MCK1..4 */
+ /* Start at MCK1 and go until MCK_count */
mov tmp1, #1
-e_loop: cmp tmp1, #5
+e_loop:
+ cmp tmp1, tmp3
beq e_done
/* Write MCK ID to retrieve the settings. */
@@ -850,7 +852,37 @@ e_save_mck3:
b e_ps
e_save_mck4:
+ cmp tmp1, #4
+ bne e_save_mck5
str tmp2, .saved_mck4
+ b e_ps
+
+e_save_mck5:
+ cmp tmp1, #5
+ bne e_save_mck6
+ str tmp2, .saved_mck5
+ b e_ps
+
+e_save_mck6:
+ cmp tmp1, #6
+ bne e_save_mck7
+ str tmp2, .saved_mck6
+ b e_ps
+
+e_save_mck7:
+ cmp tmp1, #7
+ bne e_save_mck8
+ str tmp2, .saved_mck7
+ b e_ps
+
+e_save_mck8:
+ cmp tmp1, #8
+ bne e_save_mck9
+ str tmp2, .saved_mck8
+ b e_ps
+
+e_save_mck9:
+ str tmp2, .saved_mck9
e_ps:
/* Use CSS=MAINCK and DIV=1. */
@@ -870,17 +902,19 @@ e_done:
.endm
/**
- * at91_mckx_ps_restore: restore MCK1..4 settings
+ * at91_mckx_ps_restore: restore MCKx settings
*
* Side effects: overwrites tmp1, tmp2
*/
.macro at91_mckx_ps_restore
#ifdef CONFIG_SOC_SAMA7
ldr pmc, .pmc_base
+ ldr tmp2, .mck_count
- /* There are 4 MCKs we need to handle: MCK1..4 */
+ /* Start from MCK1 and go up to MCK_count */
mov tmp1, #1
-r_loop: cmp tmp1, #5
+r_loop:
+ cmp tmp1, tmp2
beq r_done
r_save_mck1:
@@ -902,7 +936,37 @@ r_save_mck3:
b r_ps
r_save_mck4:
+ cmp tmp1, #4
+ bne r_save_mck5
ldr tmp2, .saved_mck4
+ b r_ps
+
+r_save_mck5:
+ cmp tmp1, #5
+ bne r_save_mck6
+ ldr tmp2, .saved_mck5
+ b r_ps
+
+r_save_mck6:
+ cmp tmp1, #6
+ bne r_save_mck7
+ ldr tmp2, .saved_mck6
+ b r_ps
+
+r_save_mck7:
+ cmp tmp1, #7
+ bne r_save_mck8
+ ldr tmp2, .saved_mck7
+ b r_ps
+
+r_save_mck8:
+ cmp tmp1, #8
+ bne r_save_mck9
+ ldr tmp2, .saved_mck8
+ b r_ps
+
+r_save_mck9:
+ ldr tmp2, .saved_mck9
r_ps:
/* Write MCK ID to retrieve the settings. */
@@ -921,6 +985,7 @@ r_ps:
wait_mckrdy tmp1
add tmp1, tmp1, #1
+ ldr tmp2, .mck_count
b r_loop
r_done:
#endif
@@ -1045,6 +1110,10 @@ ENTRY(at91_pm_suspend_in_sram)
str tmp1, .memtype
ldr tmp1, [r0, #PM_DATA_MODE]
str tmp1, .pm_mode
+#ifdef CONFIG_SOC_SAMA7
+ ldr tmp1, [r0, #PM_DATA_PMC_MCK_COUNT]
+ str tmp1, .mck_count
+#endif
/*
* ldrne below are here to preload their address in the TLB as access
@@ -1132,6 +1201,10 @@ ENDPROC(at91_pm_suspend_in_sram)
.word 0
.pmc_version:
.word 0
+#ifdef CONFIG_SOC_SAMA7
+.mck_count:
+ .word 0
+#endif
.saved_mckr:
.word 0
.saved_pllar:
@@ -1155,6 +1228,16 @@ ENDPROC(at91_pm_suspend_in_sram)
.word 0
.saved_mck4:
.word 0
+.saved_mck5:
+ .word 0
+.saved_mck6:
+ .word 0
+.saved_mck7:
+ .word 0
+.saved_mck8:
+ .word 0
+.saved_mck9:
+ .word 0
#endif
ENTRY(at91_pm_suspend_in_sram_sz)
--
2.43.0
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [PATCH v2 13/15] power: reset: at91-sama5d2_shdwc: Add sama7d65 PMC
2025-02-10 21:13 [PATCH v2 00/15] Enable Power Modes Support for SAMA7D65 SoC Ryan.Wanner
` (11 preceding siblings ...)
2025-02-10 21:13 ` [PATCH v2 12/15] ARM: at91: pm: Enable ULP0 " Ryan.Wanner
@ 2025-02-10 21:13 ` Ryan.Wanner
2025-02-12 8:20 ` Claudiu Beznea
2025-02-10 21:13 ` [PATCH v2 14/15] ARM: dts: microchip: sama7d65: Add Reset and Shutdown and PM support Ryan.Wanner
2025-02-10 21:13 ` [PATCH v2 15/15] ARM: dts: microchip: add shutdown controller and rtt timer Ryan.Wanner
14 siblings, 1 reply; 43+ messages in thread
From: Ryan.Wanner @ 2025-02-10 21:13 UTC (permalink / raw)
To: lee, robh, krzk+dt, conor+dt, claudiu.beznea, sre, nicolas.ferre,
alexandre.belloni, p.zabel
Cc: linux, devicetree, linux-kernel, linux-pm, linux-arm-kernel,
linux-rtc, Ryan Wanner
From: Ryan Wanner <Ryan.Wanner@microchip.com>
Add sama7d65-pmc compatible string to the list of valid PMC IDs.
Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com>
---
drivers/power/reset/at91-sama5d2_shdwc.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/power/reset/at91-sama5d2_shdwc.c b/drivers/power/reset/at91-sama5d2_shdwc.c
index edb0df86aff45..0cb7fe9f25a07 100644
--- a/drivers/power/reset/at91-sama5d2_shdwc.c
+++ b/drivers/power/reset/at91-sama5d2_shdwc.c
@@ -326,6 +326,7 @@ static const struct of_device_id at91_pmc_ids[] = {
{ .compatible = "atmel,sama5d2-pmc" },
{ .compatible = "microchip,sam9x60-pmc" },
{ .compatible = "microchip,sama7g5-pmc" },
+ { .compatible = "microchip,sama7d65-pmc" },
{ /* Sentinel. */ }
};
--
2.43.0
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [PATCH v2 14/15] ARM: dts: microchip: sama7d65: Add Reset and Shutdown and PM support
2025-02-10 21:13 [PATCH v2 00/15] Enable Power Modes Support for SAMA7D65 SoC Ryan.Wanner
` (12 preceding siblings ...)
2025-02-10 21:13 ` [PATCH v2 13/15] power: reset: at91-sama5d2_shdwc: Add sama7d65 PMC Ryan.Wanner
@ 2025-02-10 21:13 ` Ryan.Wanner
2025-02-13 8:28 ` Claudiu Beznea
2025-02-10 21:13 ` [PATCH v2 15/15] ARM: dts: microchip: add shutdown controller and rtt timer Ryan.Wanner
14 siblings, 1 reply; 43+ messages in thread
From: Ryan.Wanner @ 2025-02-10 21:13 UTC (permalink / raw)
To: lee, robh, krzk+dt, conor+dt, claudiu.beznea, sre, nicolas.ferre,
alexandre.belloni, p.zabel
Cc: linux, devicetree, linux-kernel, linux-pm, linux-arm-kernel,
linux-rtc, Ryan Wanner
From: Ryan Wanner <Ryan.Wanner@microchip.com>
Add support for reset controller, wake up alarm timers, and shutdown
controller.
Add SRAM, SFR, secumod, UDDRC, and DDR3phy to enable support for low power modes.
Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com>
---
arch/arm/boot/dts/microchip/sama7d65.dtsi | 77 +++++++++++++++++++++++
1 file changed, 77 insertions(+)
diff --git a/arch/arm/boot/dts/microchip/sama7d65.dtsi b/arch/arm/boot/dts/microchip/sama7d65.dtsi
index 854b30d15dcd4..1d40235bdab0a 100644
--- a/arch/arm/boot/dts/microchip/sama7d65.dtsi
+++ b/arch/arm/boot/dts/microchip/sama7d65.dtsi
@@ -46,12 +46,42 @@ slow_xtal: clock-slowxtal {
};
};
+ ns_sram: sram@100000 {
+ compatible = "mmio-sram";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x100000 0x20000>;
+ ranges;
+ };
+
soc {
compatible = "simple-bus";
ranges;
#address-cells = <1>;
#size-cells = <1>;
+ securam: sram@e0000800 {
+ compatible = "microchip,sama7d65-securam", "atmel,sama5d2-securam", "mmio-sram";
+ reg = <0xe0000800 0x4000>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 17>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0xe0000800 0x4000>;
+ no-memory-wc;
+ };
+
+ secumod: secumod@e0004000 {
+ compatible = "microchip,sama7d65-secumod", "atmel,sama5d2-secumod", "syscon";
+ reg = <0xe0004000 0x4000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ sfrbu: sfr@e0008000 {
+ compatible ="microchip,sama7d65-sfrbu", "atmel,sama5d2-sfrbu", "syscon";
+ reg = <0xe0008000 0x20>;
+ };
+
pioa: pinctrl@e0014000 {
compatible = "microchip,sama7d65-pinctrl", "microchip,sama7g5-pinctrl";
reg = <0xe0014000 0x800>;
@@ -76,6 +106,31 @@ pmc: clock-controller@e0018000 {
clock-names = "td_slck", "md_slck", "main_xtal";
};
+ reset_controller: reset-controller@e001d100 {
+ compatible = "microchip,sama7d65-rstc", "microchip,sama7g5-rstc";
+ reg = <0xe001d100 0xc>, <0xe001d1e4 0x4>;
+ #reset-cells = <1>;
+ clocks = <&clk32k 0>;
+ };
+
+ shdwc: poweroff@e001d200 {
+ compatible = "microchip,sama7d65-shdwc", "microchip,sama7g5-shdwc", "syscon";
+ reg = <0xe001d200 0x20>;
+ clocks = <&clk32k 0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ atmel,wakeup-rtc-timer;
+ atmel,wakeup-rtt-timer;
+ status = "disabled";
+ };
+
+ rtt: rtc@e001d300 {
+ compatible = "microchip,sama7d65-rtt", "atmel,at91sam9260-rtt";
+ reg = <0xe001d300 0x30>;
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk32k 0>;
+ };
+
clk32k: clock-controller@e001d500 {
compatible = "microchip,sama7d65-sckc", "microchip,sam9x60-sckc";
reg = <0xe001d500 0x4>;
@@ -83,6 +138,18 @@ clk32k: clock-controller@e001d500 {
#clock-cells = <1>;
};
+ gpbr: gpbr@e001d700 {
+ compatible = "microchip,sama7d65-gpbr", "syscon";
+ reg = <0xe001d700 0x48>;
+ };
+
+ rtc: rtc@e001d800 {
+ compatible = "microchip,sama7d65-rtc", "microchip,sam9x60-rtc";
+ reg = <0xe001d800 0x30>;
+ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk32k 1>;
+ };
+
sdmmc1: mmc@e1208000 {
compatible = "microchip,sama7d65-sdhci", "microchip,sam9x60-sdhci";
reg = <0xe1208000 0x400>;
@@ -132,6 +199,16 @@ uart6: serial@200 {
};
};
+ uddrc: uddrc@e3800000 {
+ compatible = "microchip,sama7d65-uddrc", "microchip,sama7g5-uddrc";
+ reg = <0xe3800000 0x4000>;
+ };
+
+ ddr3phy: ddr3phy@e3804000 {
+ compatible = "microchip,sama7d65-ddr3phy", "microchip,sama7g5-ddr3phy";
+ reg = <0xe3804000 0x1000>;
+ };
+
gic: interrupt-controller@e8c11000 {
compatible = "arm,cortex-a7-gic";
reg = <0xe8c11000 0x1000>,
--
2.43.0
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [PATCH v2 15/15] ARM: dts: microchip: add shutdown controller and rtt timer
2025-02-10 21:13 [PATCH v2 00/15] Enable Power Modes Support for SAMA7D65 SoC Ryan.Wanner
` (13 preceding siblings ...)
2025-02-10 21:13 ` [PATCH v2 14/15] ARM: dts: microchip: sama7d65: Add Reset and Shutdown and PM support Ryan.Wanner
@ 2025-02-10 21:13 ` Ryan.Wanner
2025-02-13 8:30 ` Claudiu Beznea
14 siblings, 1 reply; 43+ messages in thread
From: Ryan.Wanner @ 2025-02-10 21:13 UTC (permalink / raw)
To: lee, robh, krzk+dt, conor+dt, claudiu.beznea, sre, nicolas.ferre,
alexandre.belloni, p.zabel
Cc: linux, devicetree, linux-kernel, linux-pm, linux-arm-kernel,
linux-rtc, Ryan Wanner
From: Ryan Wanner <Ryan.Wanner@microchip.com>
Add shutdown controller and rtt timer to support shutdown and wake up.
Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com>
---
.../boot/dts/microchip/at91-sama7d65_curiosity.dts | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dts b/arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dts
index 0f86360fb733a..d1d0b06fbfc43 100644
--- a/arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dts
+++ b/arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dts
@@ -77,6 +77,11 @@ pinctrl_uart6_default: uart6-default {
};
};
+&rtt {
+ atmel,rtt-rtc-time-reg = <&gpbr 0x0>;
+ status = "disabled";
+};
+
&sdmmc1 {
bus-width = <4>;
pinctrl-names = "default";
@@ -84,6 +89,15 @@ &sdmmc1 {
status = "okay";
};
+&shdwc {
+ debounce-delay-us = <976>;
+ status = "okay";
+
+ input@0 {
+ reg = <0>;
+ };
+};
+
&slow_xtal {
clock-frequency = <32768>;
};
--
2.43.0
^ permalink raw reply related [flat|nested] 43+ messages in thread
* Re: [PATCH v2 01/15] dt-bindings: mfd: syscon: add microchip,sama7d65-ddr3phy
2025-02-10 21:13 ` [PATCH v2 01/15] dt-bindings: mfd: syscon: add microchip,sama7d65-ddr3phy Ryan.Wanner
@ 2025-02-11 8:12 ` Krzysztof Kozlowski
0 siblings, 0 replies; 43+ messages in thread
From: Krzysztof Kozlowski @ 2025-02-11 8:12 UTC (permalink / raw)
To: Ryan.Wanner
Cc: lee, robh, krzk+dt, conor+dt, claudiu.beznea, sre, nicolas.ferre,
alexandre.belloni, p.zabel, linux, devicetree, linux-kernel,
linux-pm, linux-arm-kernel, linux-rtc
On Mon, Feb 10, 2025 at 02:13:01PM -0700, Ryan.Wanner@microchip.com wrote:
> From: Ryan Wanner <Ryan.Wanner@microchip.com>
>
> Add SAMA7D65 DDR3phy compatible to DT bindings documentation
>
> Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com>
> ---
> Documentation/devicetree/bindings/mfd/syscon.yaml | 2 ++
> 1 file changed, 2 insertions(+)
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH v2 01/15] dt-bindings: mfd: syscon: add microchip,sama7d65-ddr3phy
@ 2025-02-11 8:12 ` Krzysztof Kozlowski
0 siblings, 0 replies; 43+ messages in thread
From: Krzysztof Kozlowski @ 2025-02-11 8:12 UTC (permalink / raw)
To: Ryan.Wanner
Cc: linux-rtc, robh, conor+dt, alexandre.belloni, devicetree,
linux-kernel, linux-pm, lee, sre, claudiu.beznea, p.zabel, linux,
krzk+dt, linux-arm-kernel
On Mon, Feb 10, 2025 at 02:13:01PM -0700, Ryan.Wanner@microchip.com wrote:
> From: Ryan Wanner <Ryan.Wanner@microchip.com>
>
> Add SAMA7D65 DDR3phy compatible to DT bindings documentation
>
> Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com>
> ---
> Documentation/devicetree/bindings/mfd/syscon.yaml | 2 ++
> 1 file changed, 2 insertions(+)
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH v2 02/15] dt-bindings: mfd: syscon: add microchip,sama7d65-sfrbu
2025-02-10 21:13 ` [PATCH v2 02/15] dt-bindings: mfd: syscon: add microchip,sama7d65-sfrbu Ryan.Wanner
@ 2025-02-11 8:14 ` Krzysztof Kozlowski
0 siblings, 0 replies; 43+ messages in thread
From: Krzysztof Kozlowski @ 2025-02-11 8:14 UTC (permalink / raw)
To: Ryan.Wanner
Cc: lee, robh, krzk+dt, conor+dt, claudiu.beznea, sre, nicolas.ferre,
alexandre.belloni, p.zabel, linux, devicetree, linux-kernel,
linux-pm, linux-arm-kernel, linux-rtc
On Mon, Feb 10, 2025 at 02:13:02PM -0700, Ryan.Wanner@microchip.com wrote:
> From: Ryan Wanner <Ryan.Wanner@microchip.com>
>
> Add SAMA7D65 SFRBU compatible string to DT bindings documentation
>
> Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com>
> ---
> Documentation/devicetree/bindings/mfd/syscon.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/mfd/syscon.yaml b/Documentation/devicetree/bindings/mfd/syscon.yaml
> index 51d896c88dafa..727292ffe092e 100644
> --- a/Documentation/devicetree/bindings/mfd/syscon.yaml
> +++ b/Documentation/devicetree/bindings/mfd/syscon.yaml
> @@ -91,6 +91,7 @@ select:
> - microchip,mpfs-sysreg-scb
> - microchip,sam9x60-sfr
> - microchip,sama7d65-ddr3phy
> + - microchip,sama7d65-sfrbu
You got comment on #1 of your v1, so if you make exactly the same
mistake in other patches then fix it there as well.
Apply v1 Rob's comments to all your patches.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH v2 02/15] dt-bindings: mfd: syscon: add microchip,sama7d65-sfrbu
@ 2025-02-11 8:14 ` Krzysztof Kozlowski
0 siblings, 0 replies; 43+ messages in thread
From: Krzysztof Kozlowski @ 2025-02-11 8:14 UTC (permalink / raw)
To: Ryan.Wanner
Cc: linux-rtc, robh, conor+dt, alexandre.belloni, devicetree,
linux-kernel, linux-pm, lee, sre, claudiu.beznea, p.zabel, linux,
krzk+dt, linux-arm-kernel
On Mon, Feb 10, 2025 at 02:13:02PM -0700, Ryan.Wanner@microchip.com wrote:
> From: Ryan Wanner <Ryan.Wanner@microchip.com>
>
> Add SAMA7D65 SFRBU compatible string to DT bindings documentation
>
> Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com>
> ---
> Documentation/devicetree/bindings/mfd/syscon.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/mfd/syscon.yaml b/Documentation/devicetree/bindings/mfd/syscon.yaml
> index 51d896c88dafa..727292ffe092e 100644
> --- a/Documentation/devicetree/bindings/mfd/syscon.yaml
> +++ b/Documentation/devicetree/bindings/mfd/syscon.yaml
> @@ -91,6 +91,7 @@ select:
> - microchip,mpfs-sysreg-scb
> - microchip,sam9x60-sfr
> - microchip,sama7d65-ddr3phy
> + - microchip,sama7d65-sfrbu
You got comment on #1 of your v1, so if you make exactly the same
mistake in other patches then fix it there as well.
Apply v1 Rob's comments to all your patches.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH v2 11/15] ARM: at91: PM: Add Backup mode for SAMA7D65
2025-02-10 21:13 ` [PATCH v2 11/15] ARM: at91: PM: Add Backup mode for SAMA7D65 Ryan.Wanner
@ 2025-02-12 8:15 ` Claudiu Beznea
0 siblings, 0 replies; 43+ messages in thread
From: Claudiu Beznea @ 2025-02-12 8:15 UTC (permalink / raw)
To: Ryan.Wanner, lee, robh, krzk+dt, conor+dt, sre, nicolas.ferre,
alexandre.belloni, p.zabel
Cc: linux, devicetree, linux-kernel, linux-pm, linux-arm-kernel,
linux-rtc
Hi, Ryan,
On 10.02.2025 23:13, Ryan.Wanner@microchip.com wrote:
> From: Ryan Wanner <Ryan.Wanner@microchip.com>
>
> Add config check that enables Backup mode for SAMA7D65 SoC.
>
> Add SHDWC_SR read to clear the status bits once finished exiting low
> power modes.
Can you please also explain why? From [1]:
"The text should be written in such detail so that when read weeks, months
or even years later, it can give the reader the needed details to grasp the
reasoning for **why** the patch was created."
[1] https://www.kernel.org/doc/html/v6.13/process/submitting-patches.html
> This is only for SAMA7D65 SoCs.
>
> Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com>
> ---
> arch/arm/mach-at91/pm.c | 6 +++++-
> 1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
> index 1eec68e92f8d8..55cab31ce1ecb 100644
> --- a/arch/arm/mach-at91/pm.c
> +++ b/arch/arm/mach-at91/pm.c
> @@ -707,6 +707,9 @@ static int at91_pm_enter(suspend_state_t state)
> static void at91_pm_end(void)
> {
> at91_pm_config_ws(soc_pm.data.mode, false);
> +
> + if (IS_ENABLED(CONFIG_SOC_SAMA7D65))
> + readl(soc_pm.data.shdwc + 0x08);
Can you please add a comment near explaining what 0x08 offset means (search
for "SHDWC.MR" in this file for an example)?
Is this cleanup needed only for backup mode or for all of them. If only for
backup you can move it in at91_pm_suspend() after fncpy().
Thank you,
Claudiu
> }
>
>
> @@ -1065,7 +1068,8 @@ static int __init at91_pm_backup_init(void)
> int ret = -ENODEV, located = 0;
>
> if (!IS_ENABLED(CONFIG_SOC_SAMA5D2) &&
> - !IS_ENABLED(CONFIG_SOC_SAMA7G5))
> + !IS_ENABLED(CONFIG_SOC_SAMA7G5) &&
> + !IS_ENABLED(CONFIG_SOC_SAMA7D65))
> return -EPERM;
>
> if (!at91_is_pm_mode_active(AT91_PM_BACKUP))
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH v2 09/15] ARM: at91: pm: fix at91_suspend_finish for ZQ calibration
2025-02-10 21:13 ` [PATCH v2 09/15] ARM: at91: pm: fix at91_suspend_finish for ZQ calibration Ryan.Wanner
@ 2025-02-12 8:17 ` Claudiu Beznea
0 siblings, 0 replies; 43+ messages in thread
From: Claudiu Beznea @ 2025-02-12 8:17 UTC (permalink / raw)
To: Ryan.Wanner, lee, robh, krzk+dt, conor+dt, sre, nicolas.ferre,
alexandre.belloni, p.zabel
Cc: linux, devicetree, linux-kernel, linux-pm, linux-arm-kernel,
linux-rtc, Li Bin, Durai Manickam KR, Andrei Simion
Hi, Ryan,
On 10.02.2025 23:13, Ryan.Wanner@microchip.com wrote:
> From: Li Bin <bin.li@microchip.com>
>
> For sama7g5 and sama7d65 backup mode, we encountered a "ZQ calibrate error"
> during recalibrating the impedance in BootStrap.
> We found that the impedance value saved in at91_suspend_finish() before
> the DDR entered self-refresh mode did not match the resistor values. The
> ZDATA field in the DDR3PHY_ZQ0CR0 register uses a modified gray code to
> select the different impedance setting.
> But these gray code are incorrect, a workaournd from design team fixed the
> bug in the calibration logic. The ZDATA contains four independent impedance
> elements, but the algorithm combined the four elements into one. The elements
> were fixed using properly shifted offsets.
>
> Signed-off-by: Li Bin <bin.li@microchip.com>
> [nicolas.ferre@microchip.com: fix indentation and combine 2 patches]
> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
> Tested-by: Ryan Wanner <Ryan.Wanner@microchip.com>
> Tested-by: Durai Manickam KR <durai.manickamkr@microchip.com>
> Tested-by: Andrei Simion <andrei.simion@microchip.com>
Missing your SoB tag.
> ---
> arch/arm/mach-at91/pm.c | 21 +++++++++++----------
> 1 file changed, 11 insertions(+), 10 deletions(-)
>
> diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
> index 05a1547642b60..6c3e6aa22606f 100644
> --- a/arch/arm/mach-at91/pm.c
> +++ b/arch/arm/mach-at91/pm.c
> @@ -545,11 +545,12 @@ extern u32 at91_pm_suspend_in_sram_sz;
>
> static int at91_suspend_finish(unsigned long val)
> {
> - unsigned char modified_gray_code[] = {
> - 0x00, 0x01, 0x02, 0x03, 0x06, 0x07, 0x04, 0x05, 0x0c, 0x0d,
> - 0x0e, 0x0f, 0x0a, 0x0b, 0x08, 0x09, 0x18, 0x19, 0x1a, 0x1b,
> - 0x1e, 0x1f, 0x1c, 0x1d, 0x14, 0x15, 0x16, 0x17, 0x12, 0x13,
> - 0x10, 0x11,
> + /* SYNOPSYS workaround to fix a bug in the calibration logic */
> + unsigned char modified_fix_code[] = {
> + 0x00, 0x01, 0x01, 0x06, 0x07, 0x0c, 0x06, 0x07, 0x0b, 0x18,
> + 0x0a, 0x0b, 0x0c, 0x0d, 0x0d, 0x0a, 0x13, 0x13, 0x12, 0x13,
> + 0x14, 0x15, 0x15, 0x12, 0x18, 0x19, 0x19, 0x1e, 0x1f, 0x14,
> + 0x1e, 0x1f,
> };
> unsigned int tmp, index;
> int i;
> @@ -560,25 +561,25 @@ static int at91_suspend_finish(unsigned long val)
> * restore the ZQ0SR0 with the value saved here. But the
> * calibration is buggy and restoring some values from ZQ0SR0
> * is forbidden and risky thus we need to provide processed
> - * values for these (modified gray code values).
> + * values for these.
> */
> tmp = readl(soc_pm.data.ramc_phy + DDR3PHY_ZQ0SR0);
>
> /* Store pull-down output impedance select. */
> index = (tmp >> DDR3PHY_ZQ0SR0_PDO_OFF) & 0x1f;
> - soc_pm.bu->ddr_phy_calibration[0] = modified_gray_code[index];
> + soc_pm.bu->ddr_phy_calibration[0] = modified_fix_code[index] << DDR3PHY_ZQ0SR0_PDO_OFF;
>
> /* Store pull-up output impedance select. */
> index = (tmp >> DDR3PHY_ZQ0SR0_PUO_OFF) & 0x1f;
> - soc_pm.bu->ddr_phy_calibration[0] |= modified_gray_code[index];
> + soc_pm.bu->ddr_phy_calibration[0] |= modified_fix_code[index] << DDR3PHY_ZQ0SR0_PUO_OFF;
>
> /* Store pull-down on-die termination impedance select. */
> index = (tmp >> DDR3PHY_ZQ0SR0_PDODT_OFF) & 0x1f;
> - soc_pm.bu->ddr_phy_calibration[0] |= modified_gray_code[index];
> + soc_pm.bu->ddr_phy_calibration[0] |= modified_fix_code[index] << DDR3PHY_ZQ0SR0_PDODT_OFF;
>
> /* Store pull-up on-die termination impedance select. */
> index = (tmp >> DDR3PHY_ZQ0SRO_PUODT_OFF) & 0x1f;
> - soc_pm.bu->ddr_phy_calibration[0] |= modified_gray_code[index];
> + soc_pm.bu->ddr_phy_calibration[0] |= modified_fix_code[index] << DDR3PHY_ZQ0SRO_PUODT_OFF;
>
> /*
> * The 1st 8 words of memory might get corrupted in the process
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH v2 07/15] dt-bindings: at91rm9260-rtt: add microchip,sama7d65-rtt
2025-02-10 21:13 ` [PATCH v2 07/15] dt-bindings: at91rm9260-rtt: add microchip,sama7d65-rtt Ryan.Wanner
@ 2025-02-12 8:18 ` Claudiu Beznea
2025-02-14 8:28 ` Krzysztof Kozlowski
1 sibling, 0 replies; 43+ messages in thread
From: Claudiu Beznea @ 2025-02-12 8:18 UTC (permalink / raw)
To: Ryan.Wanner, lee, robh, krzk+dt, conor+dt, sre, nicolas.ferre,
alexandre.belloni, p.zabel
Cc: linux, devicetree, linux-kernel, linux-pm, linux-arm-kernel,
linux-rtc
On 10.02.2025 23:13, Ryan.Wanner@microchip.com wrote:
> From: Ryan Wanner <Ryan.Wanner@microchip.com>
>
> Add SAMA7D65 RTT compatible to DT bindings documentation.
>
> Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com>
> ---
> .../devicetree/bindings/rtc/atmel,at91sam9260-rtt.yaml | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/rtc/atmel,at91sam9260-rtt.yaml b/Documentation/devicetree/bindings/rtc/atmel,at91sam9260-rtt.yaml
> index a7f6c1d1a08ab..48a2e013a6b24 100644
> --- a/Documentation/devicetree/bindings/rtc/atmel,at91sam9260-rtt.yaml
> +++ b/Documentation/devicetree/bindings/rtc/atmel,at91sam9260-rtt.yaml
> @@ -23,6 +23,9 @@ properties:
> - microchip,sam9x60-rtt
> - microchip,sam9x7-rtt
> - const: atmel,at91sam9260-rtt
> + - items:
> + - const: microchip,sama7d65-rtt
Can't this be added in the above enum?
> + - const: atmel,at91sam9260-rtt
> - items:
> - const: microchip,sama7g5-rtt
> - const: microchip,sam9x60-rtt
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH v2 06/15] dt-bindings: rtc: at91rm9200: add microchip,sama7d65-rtc
2025-02-10 21:13 ` [PATCH v2 06/15] dt-bindings: rtc: at91rm9200: add microchip,sama7d65-rtc Ryan.Wanner
@ 2025-02-12 8:18 ` Claudiu Beznea
2025-02-14 8:27 ` Krzysztof Kozlowski
1 sibling, 0 replies; 43+ messages in thread
From: Claudiu Beznea @ 2025-02-12 8:18 UTC (permalink / raw)
To: Ryan.Wanner, lee, robh, krzk+dt, conor+dt, sre, nicolas.ferre,
alexandre.belloni, p.zabel
Cc: linux, devicetree, linux-kernel, linux-pm, linux-arm-kernel,
linux-rtc
On 10.02.2025 23:13, Ryan.Wanner@microchip.com wrote:
> From: Ryan Wanner <Ryan.Wanner@microchip.com>
>
> Add SAMA7D65 RTC compatible to DT bindings documentation.
>
> Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com>
> ---
> .../devicetree/bindings/rtc/atmel,at91rm9200-rtc.yaml | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.yaml b/Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.yaml
> index c8bb2eef442dd..0c878331170b4 100644
> --- a/Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.yaml
> +++ b/Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.yaml
> @@ -25,6 +25,9 @@ properties:
> - items:
> - const: microchip,sam9x7-rtc
> - const: microchip,sam9x60-rtc
> + - items:
> + - const: microchip,sama7d65-rtc
> + - const: microchip,sam9x60-rtc
Can't these be merged like below?
- items:
- enum:
- microchip,sam9x7-rtc
- microchip,sama7d65-rtc
- const: microchip,sam9x60-rtc
>
> reg:
> maxItems: 1
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH v2 10/15] ARM: at91: pm: add DT compatible support for sama7d65
2025-02-10 21:13 ` [PATCH v2 10/15] ARM: at91: pm: add DT compatible support for sama7d65 Ryan.Wanner
@ 2025-02-12 8:20 ` Claudiu Beznea
0 siblings, 0 replies; 43+ messages in thread
From: Claudiu Beznea @ 2025-02-12 8:20 UTC (permalink / raw)
To: Ryan.Wanner, lee, robh, krzk+dt, conor+dt, sre, nicolas.ferre,
alexandre.belloni, p.zabel
Cc: linux, devicetree, linux-kernel, linux-pm, linux-arm-kernel,
linux-rtc
On 10.02.2025 23:13, Ryan.Wanner@microchip.com wrote:
> From: Ryan Wanner <Ryan.Wanner@microchip.com>
>
> Add support for SAMA7D65 new compatible strings in pm.c file for wakeup source
> IDs and PMC.
> This is the first bits of PM for this new SoC. PM depends on other patches.
>
> Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com>
> [nicolas.ferre@microchip.com: split patch and address only the pm.c changes]
> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
> ---
> arch/arm/mach-at91/pm.c | 10 +++++++---
> 1 file changed, 7 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
> index 6c3e6aa22606f..1eec68e92f8d8 100644
> --- a/arch/arm/mach-at91/pm.c
> +++ b/arch/arm/mach-at91/pm.c
> @@ -222,13 +222,16 @@ static const struct of_device_id sam9x60_ws_ids[] = {
> { /* sentinel */ }
> };
>
> -static const struct of_device_id sama7g5_ws_ids[] = {
> - { .compatible = "microchip,sama7g5-rtc", .data = &ws_info[1] },
> +static const struct of_device_id sama7_ws_ids[] = {
> + { .compatible = "microchip,sama7d65-rtc", .data = &ws_info[1] },
> + { .compatible = "microchip,sama7g5-rtc", .data = &ws_info[1] },
There are spaces b/w , and .data
> { .compatible = "microchip,sama7g5-ohci", .data = &ws_info[2] },
> { .compatible = "usb-ohci", .data = &ws_info[2] },
> { .compatible = "atmel,at91sam9g45-ehci", .data = &ws_info[2] },
> { .compatible = "usb-ehci", .data = &ws_info[2] },
> + { .compatible = "microchip,sama7d65-sdhci", .data = &ws_info[3] },
> { .compatible = "microchip,sama7g5-sdhci", .data = &ws_info[3] },
> + { .compatible = "microchip,sama7d65-rtt", .data = &ws_info[4] },
There are spaces b/w , and .data
> { .compatible = "microchip,sama7g5-rtt", .data = &ws_info[4] },
> { /* sentinel */ }
> };
> @@ -1379,6 +1382,7 @@ static const struct of_device_id atmel_pmc_ids[] __initconst = {
> { .compatible = "atmel,sama5d2-pmc", .data = &pmc_infos[1] },
> { .compatible = "microchip,sam9x60-pmc", .data = &pmc_infos[4] },
> { .compatible = "microchip,sam9x7-pmc", .data = &pmc_infos[4] },
> + { .compatible = "microchip,sama7d65-pmc", .data = &pmc_infos[4] },
> { .compatible = "microchip,sama7g5-pmc", .data = &pmc_infos[5] },
> { /* sentinel */ },
> };
> @@ -1672,7 +1676,7 @@ void __init sama7_pm_init(void)
> at91_pm_modes_init(iomaps, ARRAY_SIZE(iomaps));
> at91_pm_init(NULL);
>
> - soc_pm.ws_ids = sama7g5_ws_ids;
> + soc_pm.ws_ids = sama7_ws_ids;
> soc_pm.config_pmc_ws = at91_sam9x60_config_pmc_ws;
>
> soc_pm.sfrbu_regs.pswbu.key = (0x4BD20C << 8);
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH v2 13/15] power: reset: at91-sama5d2_shdwc: Add sama7d65 PMC
2025-02-10 21:13 ` [PATCH v2 13/15] power: reset: at91-sama5d2_shdwc: Add sama7d65 PMC Ryan.Wanner
@ 2025-02-12 8:20 ` Claudiu Beznea
0 siblings, 0 replies; 43+ messages in thread
From: Claudiu Beznea @ 2025-02-12 8:20 UTC (permalink / raw)
To: Ryan.Wanner, lee, robh, krzk+dt, conor+dt, sre, nicolas.ferre,
alexandre.belloni, p.zabel
Cc: linux, devicetree, linux-kernel, linux-pm, linux-arm-kernel,
linux-rtc
On 10.02.2025 23:13, Ryan.Wanner@microchip.com wrote:
> From: Ryan Wanner <Ryan.Wanner@microchip.com>
>
> Add sama7d65-pmc compatible string to the list of valid PMC IDs.
>
> Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com>
> ---
> drivers/power/reset/at91-sama5d2_shdwc.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/power/reset/at91-sama5d2_shdwc.c b/drivers/power/reset/at91-sama5d2_shdwc.c
> index edb0df86aff45..0cb7fe9f25a07 100644
> --- a/drivers/power/reset/at91-sama5d2_shdwc.c
> +++ b/drivers/power/reset/at91-sama5d2_shdwc.c
> @@ -326,6 +326,7 @@ static const struct of_device_id at91_pmc_ids[] = {
> { .compatible = "atmel,sama5d2-pmc" },
> { .compatible = "microchip,sam9x60-pmc" },
> { .compatible = "microchip,sama7g5-pmc" },
> + { .compatible = "microchip,sama7d65-pmc" },
This does not apply cleanly on top of v6.14-rc1. The conflict is on sam9x7
compatible which is missing from this diff.
> { /* Sentinel. */ }
> };
>
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH v2 12/15] ARM: at91: pm: Enable ULP0 for SAMA7D65
2025-02-10 21:13 ` [PATCH v2 12/15] ARM: at91: pm: Enable ULP0 " Ryan.Wanner
@ 2025-02-13 8:20 ` Claudiu Beznea
2025-02-14 18:09 ` Ryan.Wanner
0 siblings, 1 reply; 43+ messages in thread
From: Claudiu Beznea @ 2025-02-13 8:20 UTC (permalink / raw)
To: Ryan.Wanner, lee, robh, krzk+dt, conor+dt, sre, nicolas.ferre,
alexandre.belloni, p.zabel
Cc: linux, devicetree, linux-kernel, linux-pm, linux-arm-kernel,
linux-rtc
Hi, Ryan,
On 10.02.2025 23:13, Ryan.Wanner@microchip.com wrote:
> From: Ryan Wanner <Ryan.Wanner@microchip.com>
>
> New clocks are saved to enable ULP0 for SAMA7D65 because this SoC has a
> total of 10 main clocks that need to be saved for ULP0 mode.
Isn't 9 the total number of MCKs that are handled in the last/first phase
of suspend/resume?
Also, the state of MCKs are saved/restored for ULP0 and ULP1 as well.
>
> Add mck_count member to at91_pm_data, this will be used to determine
> how many mcks need to be saved. In the mck_count member will also make
> sure that no unnecessary clock settings are written during
> mck_ps_restore.
>
> Add SHDWC to ULP0 mapping to clear the SHDWC status after exiting low
> power modes.
Can you explain why this clear need to be done? The commit message should
answer to the "what?" and "why?" questions.
>
> Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com>
> Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
> ---
> arch/arm/mach-at91/pm.c | 19 +++++-
> arch/arm/mach-at91/pm.h | 1 +
> arch/arm/mach-at91/pm_data-offsets.c | 2 +
> arch/arm/mach-at91/pm_suspend.S | 97 ++++++++++++++++++++++++++--
> 4 files changed, 110 insertions(+), 9 deletions(-)
>
> diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
> index 55cab31ce1ecb..50bada544eede 100644
> --- a/arch/arm/mach-at91/pm.c
> +++ b/arch/arm/mach-at91/pm.c
> @@ -1337,6 +1337,7 @@ struct pmc_info {
> unsigned long uhp_udp_mask;
> unsigned long mckr;
> unsigned long version;
> + unsigned long mck_count;> };
>
> static const struct pmc_info pmc_infos[] __initconst = {
> @@ -1344,30 +1345,42 @@ static const struct pmc_info pmc_infos[] __initconst = {
> .uhp_udp_mask = AT91RM9200_PMC_UHP | AT91RM9200_PMC_UDP,
> .mckr = 0x30,
> .version = AT91_PMC_V1,
> + .mck_count = 1,
As this member is used only for SAMA7 SoCs I would drop it here and above
(where initialized with 1).
> },
>
> {
> .uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP,
> .mckr = 0x30,
> .version = AT91_PMC_V1,
> + .mck_count = 1,
> },
> {
> .uhp_udp_mask = AT91SAM926x_PMC_UHP,
> .mckr = 0x30,
> .version = AT91_PMC_V1,
> + .mck_count = 1,
> },
> { .uhp_udp_mask = 0,
> .mckr = 0x30,
> .version = AT91_PMC_V1,
> + .mck_count = 1,
> },
> {
> .uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP,
> .mckr = 0x28,
> .version = AT91_PMC_V2,
> + .mck_count = 1,
> },
> {
> .mckr = 0x28,
> .version = AT91_PMC_V2,
> + .mck_count = 5,
I'm not sure mck_count is a good name when used like proposed in this
patch. We know that only 4 MCKs need to be handled for SAMA7G5 and 9 for
SAMA7D65.
Maybe, better change it here to 4 (.mck_count = 4) and to 9 above
(.mck_count = 9) and adjust properly the assembly macros (see below)? What
do you think?
> + },
> + {
> + .uhp_udp_mask = AT91SAM926x_PMC_UHP,
> + .mckr = 0x28,
> + .version = AT91_PMC_V2,
> + .mck_count = 10,
> },
>
> };
> @@ -1386,7 +1399,7 @@ static const struct of_device_id atmel_pmc_ids[] __initconst = {
> { .compatible = "atmel,sama5d2-pmc", .data = &pmc_infos[1] },
> { .compatible = "microchip,sam9x60-pmc", .data = &pmc_infos[4] },
> { .compatible = "microchip,sam9x7-pmc", .data = &pmc_infos[4] },
> - { .compatible = "microchip,sama7d65-pmc", .data = &pmc_infos[4] },
> + { .compatible = "microchip,sama7d65-pmc", .data = &pmc_infos[6] },
> { .compatible = "microchip,sama7g5-pmc", .data = &pmc_infos[5] },
> { /* sentinel */ },
> };
> @@ -1457,6 +1470,7 @@ static void __init at91_pm_init(void (*pm_idle)(void))
> soc_pm.data.uhp_udp_mask = pmc->uhp_udp_mask;
> soc_pm.data.pmc_mckr_offset = pmc->mckr;
> soc_pm.data.pmc_version = pmc->version;
> + soc_pm.data.pmc_mck_count = pmc->mck_count;
>
> if (pm_idle)
> arm_pm_idle = pm_idle;
> @@ -1659,7 +1673,8 @@ void __init sama7_pm_init(void)
> AT91_PM_STANDBY, AT91_PM_ULP0, AT91_PM_ULP1, AT91_PM_BACKUP,
> };
> static const u32 iomaps[] __initconst = {
> - [AT91_PM_ULP0] = AT91_PM_IOMAP(SFRBU),
> + [AT91_PM_ULP0] = AT91_PM_IOMAP(SFRBU) |
> + AT91_PM_IOMAP(SHDWC),
In theory, as the wakeup sources can also resumes the system from standby
(WFI), the shdwc should be mapped for standby, too. Unless I'm wrong and
the wakeup sources covered by the SHDWC_SR register don't apply to standby
(WFI).
> [AT91_PM_ULP1] = AT91_PM_IOMAP(SFRBU) |
> AT91_PM_IOMAP(SHDWC) |
> AT91_PM_IOMAP(ETHC),
> diff --git a/arch/arm/mach-at91/pm.h b/arch/arm/mach-at91/pm.h
> index 53bdc9000e447..ccde9c8728c27 100644
> --- a/arch/arm/mach-at91/pm.h
> +++ b/arch/arm/mach-at91/pm.h
> @@ -39,6 +39,7 @@ struct at91_pm_data {
> unsigned int suspend_mode;
> unsigned int pmc_mckr_offset;
> unsigned int pmc_version;
> + unsigned int pmc_mck_count;
> };
> #endif
>
> diff --git a/arch/arm/mach-at91/pm_data-offsets.c b/arch/arm/mach-at91/pm_data-offsets.c
> index 40bd4e8fe40a5..59a4838038381 100644
> --- a/arch/arm/mach-at91/pm_data-offsets.c
> +++ b/arch/arm/mach-at91/pm_data-offsets.c
> @@ -18,6 +18,8 @@ int main(void)
> pmc_mckr_offset));
> DEFINE(PM_DATA_PMC_VERSION, offsetof(struct at91_pm_data,
> pmc_version));
> + DEFINE(PM_DATA_PMC_MCK_COUNT, offsetof(struct at91_pm_data,
> + pmc_mck_count));
>
> return 0;
> }
> diff --git a/arch/arm/mach-at91/pm_suspend.S b/arch/arm/mach-at91/pm_suspend.S
> index e5869cca5e791..2bbcbb26adb28 100644
> --- a/arch/arm/mach-at91/pm_suspend.S
> +++ b/arch/arm/mach-at91/pm_suspend.S
> @@ -814,17 +814,19 @@ sr_dis_exit:
> .endm
>
> /**
> - * at91_mckx_ps_enable: save MCK1..4 settings and switch it to main clock
> + * at91_mckx_ps_enable: save MCK settings and switch it to main clock
> *
> - * Side effects: overwrites tmp1, tmp2
> + * Side effects: overwrites tmp1, tmp2, tmp3
> */
> .macro at91_mckx_ps_enable
> #ifdef CONFIG_SOC_SAMA7
> ldr pmc, .pmc_base
> + ldr tmp3, .mck_count
>
> - /* There are 4 MCKs we need to handle: MCK1..4 */
> + /* Start at MCK1 and go until MCK_count */
s/MCK_count/mck_count to align with the mck_count above.
> mov tmp1, #1
> -e_loop: cmp tmp1, #5
> +e_loop:
> + cmp tmp1, tmp3
> beq e_done
If providing mck_count = 4 (for SAMA7G5) and mck_count = 9 (for SAMA7D65)
you can change this to:
bqt e_done
>
> /* Write MCK ID to retrieve the settings. */
> @@ -850,7 +852,37 @@ e_save_mck3:
> b e_ps
>
> e_save_mck4:
> + cmp tmp1, #4
> + bne e_save_mck5
> str tmp2, .saved_mck4
> + b e_ps
> +
> +e_save_mck5:
> + cmp tmp1, #5
> + bne e_save_mck6
> + str tmp2, .saved_mck5
> + b e_ps
> +
> +e_save_mck6:
> + cmp tmp1, #6
> + bne e_save_mck7
> + str tmp2, .saved_mck6
> + b e_ps
> +
> +e_save_mck7:
> + cmp tmp1, #7
> + bne e_save_mck8
> + str tmp2, .saved_mck7
> + b e_ps
> +
> +e_save_mck8:
> + cmp tmp1, #8
> + bne e_save_mck9
> + str tmp2, .saved_mck8
> + b e_ps
> +
> +e_save_mck9:
> + str tmp2, .saved_mck9
>
> e_ps:
> /* Use CSS=MAINCK and DIV=1. */
> @@ -870,17 +902,19 @@ e_done:
> .endm
>
> /**
> - * at91_mckx_ps_restore: restore MCK1..4 settings
> + * at91_mckx_ps_restore: restore MCKx settings
s/MCKx/MCK to align with the description from at91_mckx_ps_enable
> *
> * Side effects: overwrites tmp1, tmp2
> */
> .macro at91_mckx_ps_restore
> #ifdef CONFIG_SOC_SAMA7
> ldr pmc, .pmc_base
> + ldr tmp2, .mck_count
>
> - /* There are 4 MCKs we need to handle: MCK1..4 */
> + /* Start from MCK1 and go up to MCK_count */
> mov tmp1, #1
> -r_loop: cmp tmp1, #5
> +r_loop:
> + cmp tmp1, tmp2
> beq r_done
Same here:
bgt r_done
should be enough if providing mck_count = 4 or 9
>
> r_save_mck1:
> @@ -902,7 +936,37 @@ r_save_mck3:
> b r_ps
>
> r_save_mck4:
> + cmp tmp1, #4
> + bne r_save_mck5
> ldr tmp2, .saved_mck4
> + b r_ps
> +
> +r_save_mck5:
> + cmp tmp1, #5
> + bne r_save_mck6
> + ldr tmp2, .saved_mck5
> + b r_ps
> +
> +r_save_mck6:
> + cmp tmp1, #6
> + bne r_save_mck7
> + ldr tmp2, .saved_mck6
> + b r_ps
> +
> +r_save_mck7:
> + cmp tmp1, #7
> + bne r_save_mck8
> + ldr tmp2, .saved_mck7
> + b r_ps
> +
> +r_save_mck8:
> + cmp tmp1, #8
> + bne r_save_mck9
> + ldr tmp2, .saved_mck8
> + b r_ps
> +
> +r_save_mck9:
> + ldr tmp2, .saved_mck9
>
> r_ps:
> /* Write MCK ID to retrieve the settings. */
> @@ -921,6 +985,7 @@ r_ps:
> wait_mckrdy tmp1
>
> add tmp1, tmp1, #1
> + ldr tmp2, .mck_count
Or you can add tmp4 for this
> b r_loop
> r_done:
> #endif
> @@ -1045,6 +1110,10 @@ ENTRY(at91_pm_suspend_in_sram)
> str tmp1, .memtype
> ldr tmp1, [r0, #PM_DATA_MODE]
> str tmp1, .pm_mode
> +#ifdef CONFIG_SOC_SAMA7
> + ldr tmp1, [r0, #PM_DATA_PMC_MCK_COUNT]
> + str tmp1, .mck_count
> +#endif
>
> /*
> * ldrne below are here to preload their address in the TLB as access
> @@ -1132,6 +1201,10 @@ ENDPROC(at91_pm_suspend_in_sram)
> .word 0
> .pmc_version:
> .word 0
> +#ifdef CONFIG_SOC_SAMA7
> +.mck_count:
> + .word 0
> +#endif
> .saved_mckr:
> .word 0
> .saved_pllar:
> @@ -1155,6 +1228,16 @@ ENDPROC(at91_pm_suspend_in_sram)
> .word 0
> .saved_mck4:
> .word 0
> +.saved_mck5:
> + .word 0
> +.saved_mck6:
> + .word 0
> +.saved_mck7:
> + .word 0
> +.saved_mck8:
> + .word 0
> +.saved_mck9:
> + .word 0
> #endif
>
> ENTRY(at91_pm_suspend_in_sram_sz)
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH v2 14/15] ARM: dts: microchip: sama7d65: Add Reset and Shutdown and PM support
2025-02-10 21:13 ` [PATCH v2 14/15] ARM: dts: microchip: sama7d65: Add Reset and Shutdown and PM support Ryan.Wanner
@ 2025-02-13 8:28 ` Claudiu Beznea
0 siblings, 0 replies; 43+ messages in thread
From: Claudiu Beznea @ 2025-02-13 8:28 UTC (permalink / raw)
To: Ryan.Wanner, lee, robh, krzk+dt, conor+dt, sre, nicolas.ferre,
alexandre.belloni, p.zabel
Cc: linux, devicetree, linux-kernel, linux-pm, linux-arm-kernel,
linux-rtc
Hi, Ryan,
On 10.02.2025 23:13, Ryan.Wanner@microchip.com wrote:
> From: Ryan Wanner <Ryan.Wanner@microchip.com>
>
> Add support for reset controller, wake up alarm timers, and shutdown
> controller.
>
> Add SRAM, SFR, secumod, UDDRC, and DDR3phy to enable support for low power modes.
Can you split it in individual patches? E.g.
1/ add reset controller
2/ add shutdown controller
3/ add rtc support
4/ add rtt support
5/ add PM support
>
> Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com>
> ---
> arch/arm/boot/dts/microchip/sama7d65.dtsi | 77 +++++++++++++++++++++++
> 1 file changed, 77 insertions(+)
>
> diff --git a/arch/arm/boot/dts/microchip/sama7d65.dtsi b/arch/arm/boot/dts/microchip/sama7d65.dtsi
> index 854b30d15dcd4..1d40235bdab0a 100644
> --- a/arch/arm/boot/dts/microchip/sama7d65.dtsi
> +++ b/arch/arm/boot/dts/microchip/sama7d65.dtsi
> @@ -46,12 +46,42 @@ slow_xtal: clock-slowxtal {
> };
> };
>
> + ns_sram: sram@100000 {
> + compatible = "mmio-sram";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + reg = <0x100000 0x20000>;
> + ranges;
Please follow order proposed here:
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/Documentation/devicetree/bindings/dts-coding-style.rst#n112
That would be (for this node):
- compatible
- reg
- ranges
- everything else
> + };
> +
> soc {
> compatible = "simple-bus";
> ranges;
> #address-cells = <1>;
> #size-cells = <1>;
>
> + securam: sram@e0000800 {
> + compatible = "microchip,sama7d65-securam", "atmel,sama5d2-securam", "mmio-sram";
> + reg = <0xe0000800 0x4000>;
> + clocks = <&pmc PMC_TYPE_PERIPHERAL 17>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0 0xe0000800 0x4000>;
> + no-memory-wc;
Same here with regards to order and dts coding style.
> + };
> +
> + secumod: secumod@e0004000 {
> + compatible = "microchip,sama7d65-secumod", "atmel,sama5d2-secumod", "syscon";
> + reg = <0xe0004000 0x4000>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + };
> +
> + sfrbu: sfr@e0008000 {
> + compatible ="microchip,sama7d65-sfrbu", "atmel,sama5d2-sfrbu", "syscon";
> + reg = <0xe0008000 0x20>;
> + };
> +
> pioa: pinctrl@e0014000 {
> compatible = "microchip,sama7d65-pinctrl", "microchip,sama7g5-pinctrl";
> reg = <0xe0014000 0x800>;
> @@ -76,6 +106,31 @@ pmc: clock-controller@e0018000 {
> clock-names = "td_slck", "md_slck", "main_xtal";
> };
>
> + reset_controller: reset-controller@e001d100 {
> + compatible = "microchip,sama7d65-rstc", "microchip,sama7g5-rstc";
> + reg = <0xe001d100 0xc>, <0xe001d1e4 0x4>;
> + #reset-cells = <1>;
> + clocks = <&clk32k 0>;
> + };
> +
> + shdwc: poweroff@e001d200 {
> + compatible = "microchip,sama7d65-shdwc", "microchip,sama7g5-shdwc", "syscon";
> + reg = <0xe001d200 0x20>;
> + clocks = <&clk32k 0>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + atmel,wakeup-rtc-timer;
> + atmel,wakeup-rtt-timer;
> + status = "disabled";
> + };
> +
> + rtt: rtc@e001d300 {
> + compatible = "microchip,sama7d65-rtt", "atmel,at91sam9260-rtt";
> + reg = <0xe001d300 0x30>;
> + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk32k 0>;
> + };
> +
> clk32k: clock-controller@e001d500 {
> compatible = "microchip,sama7d65-sckc", "microchip,sam9x60-sckc";
> reg = <0xe001d500 0x4>;
> @@ -83,6 +138,18 @@ clk32k: clock-controller@e001d500 {
> #clock-cells = <1>;
> };
>
> + gpbr: gpbr@e001d700 {
> + compatible = "microchip,sama7d65-gpbr", "syscon";
> + reg = <0xe001d700 0x48>;
> + };
> +
> + rtc: rtc@e001d800 {
> + compatible = "microchip,sama7d65-rtc", "microchip,sam9x60-rtc";
> + reg = <0xe001d800 0x30>;
> + interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk32k 1>;
> + };
> +
> sdmmc1: mmc@e1208000 {
> compatible = "microchip,sama7d65-sdhci", "microchip,sam9x60-sdhci";
> reg = <0xe1208000 0x400>;
> @@ -132,6 +199,16 @@ uart6: serial@200 {
> };
> };
>
> + uddrc: uddrc@e3800000 {
> + compatible = "microchip,sama7d65-uddrc", "microchip,sama7g5-uddrc";
> + reg = <0xe3800000 0x4000>;
> + };
> +
> + ddr3phy: ddr3phy@e3804000 {
> + compatible = "microchip,sama7d65-ddr3phy", "microchip,sama7g5-ddr3phy";
> + reg = <0xe3804000 0x1000>;
> + };
> +
> gic: interrupt-controller@e8c11000 {
> compatible = "arm,cortex-a7-gic";
> reg = <0xe8c11000 0x1000>,
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH v2 15/15] ARM: dts: microchip: add shutdown controller and rtt timer
2025-02-10 21:13 ` [PATCH v2 15/15] ARM: dts: microchip: add shutdown controller and rtt timer Ryan.Wanner
@ 2025-02-13 8:30 ` Claudiu Beznea
0 siblings, 0 replies; 43+ messages in thread
From: Claudiu Beznea @ 2025-02-13 8:30 UTC (permalink / raw)
To: Ryan.Wanner, lee, robh, krzk+dt, conor+dt, sre, nicolas.ferre,
alexandre.belloni, p.zabel
Cc: linux, devicetree, linux-kernel, linux-pm, linux-arm-kernel,
linux-rtc
Hi, Ryan,
On 10.02.2025 23:13, Ryan.Wanner@microchip.com wrote:
> From: Ryan Wanner <Ryan.Wanner@microchip.com>
>
> Add shutdown controller and rtt timer to support shutdown and wake up.
Also, split it in 2 patches:
1/ add rtt timer
2/ Enable shdwc
>
> Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com>
> ---
> .../boot/dts/microchip/at91-sama7d65_curiosity.dts | 14 ++++++++++++++
> 1 file changed, 14 insertions(+)
>
> diff --git a/arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dts b/arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dts
> index 0f86360fb733a..d1d0b06fbfc43 100644
> --- a/arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dts
> +++ b/arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dts
> @@ -77,6 +77,11 @@ pinctrl_uart6_default: uart6-default {
> };
> };
>
> +&rtt {
> + atmel,rtt-rtc-time-reg = <&gpbr 0x0>;
> + status = "disabled";
Any reason for keeping this node disabled?
> +};
> +
> &sdmmc1 {
> bus-width = <4>;
> pinctrl-names = "default";
> @@ -84,6 +89,15 @@ &sdmmc1 {
> status = "okay";
> };
>
> +&shdwc {
> + debounce-delay-us = <976>;
> + status = "okay";
> +
> + input@0 {
> + reg = <0>;
> + };
> +};
> +
> &slow_xtal {
> clock-frequency = <32768>;
> };
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH v2 02/15] dt-bindings: mfd: syscon: add microchip,sama7d65-sfrbu
2025-02-11 8:14 ` Krzysztof Kozlowski
@ 2025-02-13 20:30 ` Conor Dooley
-1 siblings, 0 replies; 43+ messages in thread
From: Conor Dooley @ 2025-02-13 20:30 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Ryan.Wanner, lee, robh, krzk+dt, conor+dt, claudiu.beznea, sre,
nicolas.ferre, alexandre.belloni, p.zabel, linux, devicetree,
linux-kernel, linux-pm, linux-arm-kernel, linux-rtc
[-- Attachment #1: Type: text/plain, Size: 1299 bytes --]
On Tue, Feb 11, 2025 at 09:14:05AM +0100, Krzysztof Kozlowski wrote:
> On Mon, Feb 10, 2025 at 02:13:02PM -0700, Ryan.Wanner@microchip.com wrote:
> > From: Ryan Wanner <Ryan.Wanner@microchip.com>
> >
> > Add SAMA7D65 SFRBU compatible string to DT bindings documentation
> >
> > Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com>
> > ---
> > Documentation/devicetree/bindings/mfd/syscon.yaml | 1 +
> > 1 file changed, 1 insertion(+)
> >
> > diff --git a/Documentation/devicetree/bindings/mfd/syscon.yaml b/Documentation/devicetree/bindings/mfd/syscon.yaml
> > index 51d896c88dafa..727292ffe092e 100644
> > --- a/Documentation/devicetree/bindings/mfd/syscon.yaml
> > +++ b/Documentation/devicetree/bindings/mfd/syscon.yaml
> > @@ -91,6 +91,7 @@ select:
> > - microchip,mpfs-sysreg-scb
> > - microchip,sam9x60-sfr
> > - microchip,sama7d65-ddr3phy
> > + - microchip,sama7d65-sfrbu
>
> You got comment on #1 of your v1, so if you make exactly the same
> mistake in other patches then fix it there as well.
>
> Apply v1 Rob's comments to all your patches.
Actually, this patch v1 did put it in both lists, but here it got
dropped from the second list:
https://lore.kernel.org/all/20250130233431.GB1868322-robh@kernel.org/
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^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH v2 02/15] dt-bindings: mfd: syscon: add microchip,sama7d65-sfrbu
@ 2025-02-13 20:30 ` Conor Dooley
0 siblings, 0 replies; 43+ messages in thread
From: Conor Dooley @ 2025-02-13 20:30 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: linux-rtc, robh, conor+dt, Ryan.Wanner, alexandre.belloni,
devicetree, linux-kernel, linux-pm, lee, claudiu.beznea, sre,
p.zabel, linux, krzk+dt, linux-arm-kernel
[-- Attachment #1: Type: text/plain, Size: 1299 bytes --]
On Tue, Feb 11, 2025 at 09:14:05AM +0100, Krzysztof Kozlowski wrote:
> On Mon, Feb 10, 2025 at 02:13:02PM -0700, Ryan.Wanner@microchip.com wrote:
> > From: Ryan Wanner <Ryan.Wanner@microchip.com>
> >
> > Add SAMA7D65 SFRBU compatible string to DT bindings documentation
> >
> > Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com>
> > ---
> > Documentation/devicetree/bindings/mfd/syscon.yaml | 1 +
> > 1 file changed, 1 insertion(+)
> >
> > diff --git a/Documentation/devicetree/bindings/mfd/syscon.yaml b/Documentation/devicetree/bindings/mfd/syscon.yaml
> > index 51d896c88dafa..727292ffe092e 100644
> > --- a/Documentation/devicetree/bindings/mfd/syscon.yaml
> > +++ b/Documentation/devicetree/bindings/mfd/syscon.yaml
> > @@ -91,6 +91,7 @@ select:
> > - microchip,mpfs-sysreg-scb
> > - microchip,sam9x60-sfr
> > - microchip,sama7d65-ddr3phy
> > + - microchip,sama7d65-sfrbu
>
> You got comment on #1 of your v1, so if you make exactly the same
> mistake in other patches then fix it there as well.
>
> Apply v1 Rob's comments to all your patches.
Actually, this patch v1 did put it in both lists, but here it got
dropped from the second list:
https://lore.kernel.org/all/20250130233431.GB1868322-robh@kernel.org/
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^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH v2 02/15] dt-bindings: mfd: syscon: add microchip,sama7d65-sfrbu
2025-02-13 20:30 ` Conor Dooley
@ 2025-02-14 7:20 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 43+ messages in thread
From: Krzysztof Kozlowski @ 2025-02-14 7:20 UTC (permalink / raw)
To: Conor Dooley
Cc: Ryan.Wanner, lee, robh, krzk+dt, conor+dt, claudiu.beznea, sre,
nicolas.ferre, alexandre.belloni, p.zabel, linux, devicetree,
linux-kernel, linux-pm, linux-arm-kernel, linux-rtc
On 13/02/2025 21:30, Conor Dooley wrote:
>>> diff --git a/Documentation/devicetree/bindings/mfd/syscon.yaml b/Documentation/devicetree/bindings/mfd/syscon.yaml
>>> index 51d896c88dafa..727292ffe092e 100644
>>> --- a/Documentation/devicetree/bindings/mfd/syscon.yaml
>>> +++ b/Documentation/devicetree/bindings/mfd/syscon.yaml
>>> @@ -91,6 +91,7 @@ select:
>>> - microchip,mpfs-sysreg-scb
>>> - microchip,sam9x60-sfr
>>> - microchip,sama7d65-ddr3phy
>>> + - microchip,sama7d65-sfrbu
>>
>> You got comment on #1 of your v1, so if you make exactly the same
>> mistake in other patches then fix it there as well.
>>
>> Apply v1 Rob's comments to all your patches.
>
> Actually, this patch v1 did put it in both lists, but here it got
> dropped from the second list:
> https://lore.kernel.org/all/20250130233431.GB1868322-robh@kernel.org/
That's even weirder...
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH v2 02/15] dt-bindings: mfd: syscon: add microchip,sama7d65-sfrbu
@ 2025-02-14 7:20 ` Krzysztof Kozlowski
0 siblings, 0 replies; 43+ messages in thread
From: Krzysztof Kozlowski @ 2025-02-14 7:20 UTC (permalink / raw)
To: Conor Dooley
Cc: linux-rtc, robh, conor+dt, Ryan.Wanner, alexandre.belloni,
devicetree, linux-kernel, linux-pm, lee, claudiu.beznea, sre,
p.zabel, linux, krzk+dt, linux-arm-kernel
On 13/02/2025 21:30, Conor Dooley wrote:
>>> diff --git a/Documentation/devicetree/bindings/mfd/syscon.yaml b/Documentation/devicetree/bindings/mfd/syscon.yaml
>>> index 51d896c88dafa..727292ffe092e 100644
>>> --- a/Documentation/devicetree/bindings/mfd/syscon.yaml
>>> +++ b/Documentation/devicetree/bindings/mfd/syscon.yaml
>>> @@ -91,6 +91,7 @@ select:
>>> - microchip,mpfs-sysreg-scb
>>> - microchip,sam9x60-sfr
>>> - microchip,sama7d65-ddr3phy
>>> + - microchip,sama7d65-sfrbu
>>
>> You got comment on #1 of your v1, so if you make exactly the same
>> mistake in other patches then fix it there as well.
>>
>> Apply v1 Rob's comments to all your patches.
>
> Actually, this patch v1 did put it in both lists, but here it got
> dropped from the second list:
> https://lore.kernel.org/all/20250130233431.GB1868322-robh@kernel.org/
That's even weirder...
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH v2 05/15] dt-bindings: reset: atmel,at91sam9260-reset: add microchip,sama7d65-rstc
2025-02-10 21:13 ` [PATCH v2 05/15] dt-bindings: reset: atmel,at91sam9260-reset: add microchip,sama7d65-rstc Ryan.Wanner
@ 2025-02-14 8:27 ` Krzysztof Kozlowski
0 siblings, 0 replies; 43+ messages in thread
From: Krzysztof Kozlowski @ 2025-02-14 8:27 UTC (permalink / raw)
To: Ryan.Wanner
Cc: lee, robh, krzk+dt, conor+dt, claudiu.beznea, sre, nicolas.ferre,
alexandre.belloni, p.zabel, linux, devicetree, linux-kernel,
linux-pm, linux-arm-kernel, linux-rtc
On Mon, Feb 10, 2025 at 02:13:05PM -0700, Ryan.Wanner@microchip.com wrote:
> From: Ryan Wanner <Ryan.Wanner@microchip.com>
>
> Add SAMA7D65 RSTC compatible to DT bindings documentation. The
> sama7d65-rstc is compatible with the sama7g5-rstc.
>
> Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com>
> ---
> .../devicetree/bindings/reset/atmel,at91sam9260-reset.yaml | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/reset/atmel,at91sam9260-reset.yaml b/Documentation/devicetree/bindings/reset/atmel,at91sam9260-reset.yaml
> index 98465d26949ee..a1c21c3880f9d 100644
> --- a/Documentation/devicetree/bindings/reset/atmel,at91sam9260-reset.yaml
> +++ b/Documentation/devicetree/bindings/reset/atmel,at91sam9260-reset.yaml
> @@ -23,6 +23,11 @@ properties:
> - atmel,sama5d3-rstc
> - microchip,sam9x60-rstc
> - microchip,sama7g5-rstc
> +
> + - items:
> + - const: microchip,sama7d65-rstc
> + - const: microchip,sama7g5-rstc
> +
No need for blank lines around. It's making it unnecessary long.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH v2 05/15] dt-bindings: reset: atmel,at91sam9260-reset: add microchip,sama7d65-rstc
@ 2025-02-14 8:27 ` Krzysztof Kozlowski
0 siblings, 0 replies; 43+ messages in thread
From: Krzysztof Kozlowski @ 2025-02-14 8:27 UTC (permalink / raw)
To: Ryan.Wanner
Cc: linux-rtc, robh, conor+dt, alexandre.belloni, devicetree,
linux-kernel, linux-pm, lee, sre, claudiu.beznea, p.zabel, linux,
krzk+dt, linux-arm-kernel
On Mon, Feb 10, 2025 at 02:13:05PM -0700, Ryan.Wanner@microchip.com wrote:
> From: Ryan Wanner <Ryan.Wanner@microchip.com>
>
> Add SAMA7D65 RSTC compatible to DT bindings documentation. The
> sama7d65-rstc is compatible with the sama7g5-rstc.
>
> Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com>
> ---
> .../devicetree/bindings/reset/atmel,at91sam9260-reset.yaml | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/reset/atmel,at91sam9260-reset.yaml b/Documentation/devicetree/bindings/reset/atmel,at91sam9260-reset.yaml
> index 98465d26949ee..a1c21c3880f9d 100644
> --- a/Documentation/devicetree/bindings/reset/atmel,at91sam9260-reset.yaml
> +++ b/Documentation/devicetree/bindings/reset/atmel,at91sam9260-reset.yaml
> @@ -23,6 +23,11 @@ properties:
> - atmel,sama5d3-rstc
> - microchip,sam9x60-rstc
> - microchip,sama7g5-rstc
> +
> + - items:
> + - const: microchip,sama7d65-rstc
> + - const: microchip,sama7g5-rstc
> +
No need for blank lines around. It's making it unnecessary long.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH v2 06/15] dt-bindings: rtc: at91rm9200: add microchip,sama7d65-rtc
2025-02-10 21:13 ` [PATCH v2 06/15] dt-bindings: rtc: at91rm9200: add microchip,sama7d65-rtc Ryan.Wanner
@ 2025-02-14 8:27 ` Krzysztof Kozlowski
2025-02-14 8:27 ` Krzysztof Kozlowski
1 sibling, 0 replies; 43+ messages in thread
From: Krzysztof Kozlowski @ 2025-02-14 8:27 UTC (permalink / raw)
To: Ryan.Wanner
Cc: lee, robh, krzk+dt, conor+dt, claudiu.beznea, sre, nicolas.ferre,
alexandre.belloni, p.zabel, linux, devicetree, linux-kernel,
linux-pm, linux-arm-kernel, linux-rtc
On Mon, Feb 10, 2025 at 02:13:06PM -0700, Ryan.Wanner@microchip.com wrote:
> From: Ryan Wanner <Ryan.Wanner@microchip.com>
>
> Add SAMA7D65 RTC compatible to DT bindings documentation.
>
> Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com>
> ---
> .../devicetree/bindings/rtc/atmel,at91rm9200-rtc.yaml | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.yaml b/Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.yaml
> index c8bb2eef442dd..0c878331170b4 100644
> --- a/Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.yaml
> +++ b/Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.yaml
> @@ -25,6 +25,9 @@ properties:
> - items:
> - const: microchip,sam9x7-rtc
> - const: microchip,sam9x60-rtc
> + - items:
> + - const: microchip,sama7d65-rtc
So that's enum with earlier entry?
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH v2 06/15] dt-bindings: rtc: at91rm9200: add microchip,sama7d65-rtc
@ 2025-02-14 8:27 ` Krzysztof Kozlowski
0 siblings, 0 replies; 43+ messages in thread
From: Krzysztof Kozlowski @ 2025-02-14 8:27 UTC (permalink / raw)
To: Ryan.Wanner
Cc: linux-rtc, robh, conor+dt, alexandre.belloni, devicetree,
linux-kernel, linux-pm, lee, sre, claudiu.beznea, p.zabel, linux,
krzk+dt, linux-arm-kernel
On Mon, Feb 10, 2025 at 02:13:06PM -0700, Ryan.Wanner@microchip.com wrote:
> From: Ryan Wanner <Ryan.Wanner@microchip.com>
>
> Add SAMA7D65 RTC compatible to DT bindings documentation.
>
> Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com>
> ---
> .../devicetree/bindings/rtc/atmel,at91rm9200-rtc.yaml | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.yaml b/Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.yaml
> index c8bb2eef442dd..0c878331170b4 100644
> --- a/Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.yaml
> +++ b/Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.yaml
> @@ -25,6 +25,9 @@ properties:
> - items:
> - const: microchip,sam9x7-rtc
> - const: microchip,sam9x60-rtc
> + - items:
> + - const: microchip,sama7d65-rtc
So that's enum with earlier entry?
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH v2 07/15] dt-bindings: at91rm9260-rtt: add microchip,sama7d65-rtt
2025-02-10 21:13 ` [PATCH v2 07/15] dt-bindings: at91rm9260-rtt: add microchip,sama7d65-rtt Ryan.Wanner
@ 2025-02-14 8:28 ` Krzysztof Kozlowski
2025-02-14 8:28 ` Krzysztof Kozlowski
1 sibling, 0 replies; 43+ messages in thread
From: Krzysztof Kozlowski @ 2025-02-14 8:28 UTC (permalink / raw)
To: Ryan.Wanner
Cc: lee, robh, krzk+dt, conor+dt, claudiu.beznea, sre, nicolas.ferre,
alexandre.belloni, p.zabel, linux, devicetree, linux-kernel,
linux-pm, linux-arm-kernel, linux-rtc
On Mon, Feb 10, 2025 at 02:13:07PM -0700, Ryan.Wanner@microchip.com wrote:
> From: Ryan Wanner <Ryan.Wanner@microchip.com>
>
> Add SAMA7D65 RTT compatible to DT bindings documentation.
>
> Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com>
> ---
> .../devicetree/bindings/rtc/atmel,at91sam9260-rtt.yaml | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/rtc/atmel,at91sam9260-rtt.yaml b/Documentation/devicetree/bindings/rtc/atmel,at91sam9260-rtt.yaml
> index a7f6c1d1a08ab..48a2e013a6b24 100644
> --- a/Documentation/devicetree/bindings/rtc/atmel,at91sam9260-rtt.yaml
> +++ b/Documentation/devicetree/bindings/rtc/atmel,at91sam9260-rtt.yaml
> @@ -23,6 +23,9 @@ properties:
> - microchip,sam9x60-rtt
> - microchip,sam9x7-rtt
> - const: atmel,at91sam9260-rtt
> + - items:
> + - const: microchip,sama7d65-rtt
I don't think you tried to even read this binding before extending :/.
Look earlier - there is an entry with enum for this.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH v2 07/15] dt-bindings: at91rm9260-rtt: add microchip,sama7d65-rtt
@ 2025-02-14 8:28 ` Krzysztof Kozlowski
0 siblings, 0 replies; 43+ messages in thread
From: Krzysztof Kozlowski @ 2025-02-14 8:28 UTC (permalink / raw)
To: Ryan.Wanner
Cc: linux-rtc, robh, conor+dt, alexandre.belloni, devicetree,
linux-kernel, linux-pm, lee, sre, claudiu.beznea, p.zabel, linux,
krzk+dt, linux-arm-kernel
On Mon, Feb 10, 2025 at 02:13:07PM -0700, Ryan.Wanner@microchip.com wrote:
> From: Ryan Wanner <Ryan.Wanner@microchip.com>
>
> Add SAMA7D65 RTT compatible to DT bindings documentation.
>
> Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com>
> ---
> .../devicetree/bindings/rtc/atmel,at91sam9260-rtt.yaml | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/rtc/atmel,at91sam9260-rtt.yaml b/Documentation/devicetree/bindings/rtc/atmel,at91sam9260-rtt.yaml
> index a7f6c1d1a08ab..48a2e013a6b24 100644
> --- a/Documentation/devicetree/bindings/rtc/atmel,at91sam9260-rtt.yaml
> +++ b/Documentation/devicetree/bindings/rtc/atmel,at91sam9260-rtt.yaml
> @@ -23,6 +23,9 @@ properties:
> - microchip,sam9x60-rtt
> - microchip,sam9x7-rtt
> - const: atmel,at91sam9260-rtt
> + - items:
> + - const: microchip,sama7d65-rtt
I don't think you tried to even read this binding before extending :/.
Look earlier - there is an entry with enum for this.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH v2 12/15] ARM: at91: pm: Enable ULP0 for SAMA7D65
2025-02-13 8:20 ` Claudiu Beznea
@ 2025-02-14 18:09 ` Ryan.Wanner
2025-02-17 7:18 ` Claudiu Beznea
0 siblings, 1 reply; 43+ messages in thread
From: Ryan.Wanner @ 2025-02-14 18:09 UTC (permalink / raw)
To: claudiu.beznea, lee, robh, krzk+dt, conor+dt, sre, Nicolas.Ferre,
alexandre.belloni, p.zabel
Cc: linux, devicetree, linux-kernel, linux-pm, linux-arm-kernel,
linux-rtc
On 2/13/25 01:20, Claudiu Beznea wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> Hi, Ryan,
>
>
> On 10.02.2025 23:13, Ryan.Wanner@microchip.com wrote:
>> From: Ryan Wanner <Ryan.Wanner@microchip.com>
>>
>> New clocks are saved to enable ULP0 for SAMA7D65 because this SoC has a
>> total of 10 main clocks that need to be saved for ULP0 mode.
>
> Isn't 9 the total number of MCKs that are handled in the last/first phase
> of suspend/resume?
Yes I was including 10 to match the indexing in the mck_count variable.
Since bgt instruction was suggested I will correct this to reflect the
true behavior of the change.
>
> Also, the state of MCKs are saved/restored for ULP0 and ULP1 as well.
>
>>
>> Add mck_count member to at91_pm_data, this will be used to determine
>> how many mcks need to be saved. In the mck_count member will also make
>> sure that no unnecessary clock settings are written during
>> mck_ps_restore.
>>
>> Add SHDWC to ULP0 mapping to clear the SHDWC status after exiting low
>> power modes.
>
> Can you explain why this clear need to be done? The commit message should
> answer to the "what?" and "why?" questions.
>
>>
>> Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com>
>> Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
>> ---
>> arch/arm/mach-at91/pm.c | 19 +++++-
>> arch/arm/mach-at91/pm.h | 1 +
>> arch/arm/mach-at91/pm_data-offsets.c | 2 +
>> arch/arm/mach-at91/pm_suspend.S | 97 ++++++++++++++++++++++++++--
>> 4 files changed, 110 insertions(+), 9 deletions(-)
>>
>> diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
>> index 55cab31ce1ecb..50bada544eede 100644
>> --- a/arch/arm/mach-at91/pm.c
>> +++ b/arch/arm/mach-at91/pm.c
>> @@ -1337,6 +1337,7 @@ struct pmc_info {
>> unsigned long uhp_udp_mask;
>> unsigned long mckr;
>> unsigned long version;
>> + unsigned long mck_count;> };
>>
>> static const struct pmc_info pmc_infos[] __initconst = {
>> @@ -1344,30 +1345,42 @@ static const struct pmc_info pmc_infos[] __initconst = {
>> .uhp_udp_mask = AT91RM9200_PMC_UHP | AT91RM9200_PMC_UDP,
>> .mckr = 0x30,
>> .version = AT91_PMC_V1,
>> + .mck_count = 1,
>
> As this member is used only for SAMA7 SoCs I would drop it here and above
> (where initialized with 1).
>
>> },
>>
>> {
>> .uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP,
>> .mckr = 0x30,
>> .version = AT91_PMC_V1,
>> + .mck_count = 1,
>> },
>> {
>> .uhp_udp_mask = AT91SAM926x_PMC_UHP,
>> .mckr = 0x30,
>> .version = AT91_PMC_V1,
>> + .mck_count = 1,
>> },
>> { .uhp_udp_mask = 0,
>> .mckr = 0x30,
>> .version = AT91_PMC_V1,
>> + .mck_count = 1,
>> },
>> {
>> .uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP,
>> .mckr = 0x28,
>> .version = AT91_PMC_V2,
>> + .mck_count = 1,
>> },
>> {
>> .mckr = 0x28,
>> .version = AT91_PMC_V2,
>> + .mck_count = 5,
>
> I'm not sure mck_count is a good name when used like proposed in this
> patch. We know that only 4 MCKs need to be handled for SAMA7G5 and 9 for
> SAMA7D65.
>
> Maybe, better change it here to 4 (.mck_count = 4) and to 9 above
> (.mck_count = 9) and adjust properly the assembly macros (see below)? What
> do you think?
Yes I think this is better and cleaner to read. Should this mck_count
match the pmc_mck_count variable name? Or should this be more
descriptive or would mcks be sufficient.
>
>> + },
>> + {
>> + .uhp_udp_mask = AT91SAM926x_PMC_UHP,
>> + .mckr = 0x28,
>> + .version = AT91_PMC_V2,
>> + .mck_count = 10,
>> },
>>
>> };
>> @@ -1386,7 +1399,7 @@ static const struct of_device_id atmel_pmc_ids[] __initconst = {
>> { .compatible = "atmel,sama5d2-pmc", .data = &pmc_infos[1] },
>> { .compatible = "microchip,sam9x60-pmc", .data = &pmc_infos[4] },
>> { .compatible = "microchip,sam9x7-pmc", .data = &pmc_infos[4] },
>> - { .compatible = "microchip,sama7d65-pmc", .data = &pmc_infos[4] },
>> + { .compatible = "microchip,sama7d65-pmc", .data = &pmc_infos[6] },
>> { .compatible = "microchip,sama7g5-pmc", .data = &pmc_infos[5] },
>> { /* sentinel */ },
>> };
>> @@ -1457,6 +1470,7 @@ static void __init at91_pm_init(void (*pm_idle)(void))
>> soc_pm.data.uhp_udp_mask = pmc->uhp_udp_mask;
>> soc_pm.data.pmc_mckr_offset = pmc->mckr;
>> soc_pm.data.pmc_version = pmc->version;
>> + soc_pm.data.pmc_mck_count = pmc->mck_count;
>>
>> if (pm_idle)
>> arm_pm_idle = pm_idle;
>> @@ -1659,7 +1673,8 @@ void __init sama7_pm_init(void)
>> AT91_PM_STANDBY, AT91_PM_ULP0, AT91_PM_ULP1, AT91_PM_BACKUP,
>> };
>> static const u32 iomaps[] __initconst = {
>> - [AT91_PM_ULP0] = AT91_PM_IOMAP(SFRBU),
>> + [AT91_PM_ULP0] = AT91_PM_IOMAP(SFRBU) |
>> + AT91_PM_IOMAP(SHDWC),
>
> In theory, as the wakeup sources can also resumes the system from standby
> (WFI), the shdwc should be mapped for standby, too. Unless I'm wrong and
> the wakeup sources covered by the SHDWC_SR register don't apply to standby
> (WFI).
The device can wake up from an RTT or RTC alarm event on both the
standby power mode and the ULP0 power mode, since the RTT/RTC are
included in the SHDWC_SR I think it is safe to have this.
If I understand what you are asking correctly.
>
>
>> [AT91_PM_ULP1] = AT91_PM_IOMAP(SFRBU) |
>> AT91_PM_IOMAP(SHDWC) |
>> AT91_PM_IOMAP(ETHC),
>> diff --git a/arch/arm/mach-at91/pm.h b/arch/arm/mach-at91/pm.h
>> index 53bdc9000e447..ccde9c8728c27 100644
>> --- a/arch/arm/mach-at91/pm.h
>> +++ b/arch/arm/mach-at91/pm.h
>> @@ -39,6 +39,7 @@ struct at91_pm_data {
>> unsigned int suspend_mode;
>> unsigned int pmc_mckr_offset;
>> unsigned int pmc_version;
>> + unsigned int pmc_mck_count;
>> };
>> #endif
>>
>> diff --git a/arch/arm/mach-at91/pm_data-offsets.c b/arch/arm/mach-at91/pm_data-offsets.c
>> index 40bd4e8fe40a5..59a4838038381 100644
>> --- a/arch/arm/mach-at91/pm_data-offsets.c
>> +++ b/arch/arm/mach-at91/pm_data-offsets.c
>> @@ -18,6 +18,8 @@ int main(void)
>> pmc_mckr_offset));
>> DEFINE(PM_DATA_PMC_VERSION, offsetof(struct at91_pm_data,
>> pmc_version));
>> + DEFINE(PM_DATA_PMC_MCK_COUNT, offsetof(struct at91_pm_data,
>> + pmc_mck_count));
>>
>> return 0;
>> }
>> diff --git a/arch/arm/mach-at91/pm_suspend.S b/arch/arm/mach-at91/pm_suspend.S
>> index e5869cca5e791..2bbcbb26adb28 100644
>> --- a/arch/arm/mach-at91/pm_suspend.S
>> +++ b/arch/arm/mach-at91/pm_suspend.S
>> @@ -814,17 +814,19 @@ sr_dis_exit:
>> .endm
>>
>> /**
>> - * at91_mckx_ps_enable: save MCK1..4 settings and switch it to main clock
>> + * at91_mckx_ps_enable: save MCK settings and switch it to main clock
>> *
>> - * Side effects: overwrites tmp1, tmp2
>> + * Side effects: overwrites tmp1, tmp2, tmp3
>> */
>> .macro at91_mckx_ps_enable
>> #ifdef CONFIG_SOC_SAMA7
>> ldr pmc, .pmc_base
>> + ldr tmp3, .mck_count
>>
>> - /* There are 4 MCKs we need to handle: MCK1..4 */
>> + /* Start at MCK1 and go until MCK_count */
>
> s/MCK_count/mck_count to align with the mck_count above.
>
>> mov tmp1, #1
>> -e_loop: cmp tmp1, #5
>> +e_loop:
>> + cmp tmp1, tmp3
>> beq e_done
>
> If providing mck_count = 4 (for SAMA7G5) and mck_count = 9 (for SAMA7D65)
> you can change this to:
>
> bqt e_done
>
>>
>> /* Write MCK ID to retrieve the settings. */
>> @@ -850,7 +852,37 @@ e_save_mck3:
>> b e_ps
>>
>> e_save_mck4:
>> + cmp tmp1, #4
>> + bne e_save_mck5
>> str tmp2, .saved_mck4
>> + b e_ps
>> +
>> +e_save_mck5:
>> + cmp tmp1, #5
>> + bne e_save_mck6
>> + str tmp2, .saved_mck5
>> + b e_ps
>> +
>> +e_save_mck6:
>> + cmp tmp1, #6
>> + bne e_save_mck7
>> + str tmp2, .saved_mck6
>> + b e_ps
>> +
>> +e_save_mck7:
>> + cmp tmp1, #7
>> + bne e_save_mck8
>> + str tmp2, .saved_mck7
>> + b e_ps
>> +
>> +e_save_mck8:
>> + cmp tmp1, #8
>> + bne e_save_mck9
>> + str tmp2, .saved_mck8
>> + b e_ps
>> +
>> +e_save_mck9:
>> + str tmp2, .saved_mck9
>>
>> e_ps:
>> /* Use CSS=MAINCK and DIV=1. */
>> @@ -870,17 +902,19 @@ e_done:
>> .endm
>>
>> /**
>> - * at91_mckx_ps_restore: restore MCK1..4 settings
>> + * at91_mckx_ps_restore: restore MCKx settings
>
> s/MCKx/MCK to align with the description from at91_mckx_ps_enable
>
>> *
>> * Side effects: overwrites tmp1, tmp2
>> */
>> .macro at91_mckx_ps_restore
>> #ifdef CONFIG_SOC_SAMA7
>> ldr pmc, .pmc_base
>> + ldr tmp2, .mck_count
>>
>> - /* There are 4 MCKs we need to handle: MCK1..4 */
>> + /* Start from MCK1 and go up to MCK_count */
>> mov tmp1, #1
>> -r_loop: cmp tmp1, #5
>> +r_loop:
>> + cmp tmp1, tmp2
>> beq r_done
>
> Same here:
> bgt r_done
>
> should be enough if providing mck_count = 4 or 9
>
>>
>> r_save_mck1:
>> @@ -902,7 +936,37 @@ r_save_mck3:
>> b r_ps
>>
>> r_save_mck4:
>> + cmp tmp1, #4
>> + bne r_save_mck5
>> ldr tmp2, .saved_mck4
>> + b r_ps
>> +
>> +r_save_mck5:
>> + cmp tmp1, #5
>> + bne r_save_mck6
>> + ldr tmp2, .saved_mck5
>> + b r_ps
>> +
>> +r_save_mck6:
>> + cmp tmp1, #6
>> + bne r_save_mck7
>> + ldr tmp2, .saved_mck6
>> + b r_ps
>> +
>> +r_save_mck7:
>> + cmp tmp1, #7
>> + bne r_save_mck8
>> + ldr tmp2, .saved_mck7
>> + b r_ps
>> +
>> +r_save_mck8:
>> + cmp tmp1, #8
>> + bne r_save_mck9
>> + ldr tmp2, .saved_mck8
>> + b r_ps
>> +
>> +r_save_mck9:
>> + ldr tmp2, .saved_mck9
>>
>> r_ps:
>> /* Write MCK ID to retrieve the settings. */
>> @@ -921,6 +985,7 @@ r_ps:
>> wait_mckrdy tmp1
>>
>> add tmp1, tmp1, #1
>> + ldr tmp2, .mck_count
>
> Or you can add tmp4 for this
>
>> b r_loop
>> r_done:
>> #endif
>> @@ -1045,6 +1110,10 @@ ENTRY(at91_pm_suspend_in_sram)
>> str tmp1, .memtype
>> ldr tmp1, [r0, #PM_DATA_MODE]
>> str tmp1, .pm_mode
>> +#ifdef CONFIG_SOC_SAMA7
>> + ldr tmp1, [r0, #PM_DATA_PMC_MCK_COUNT]
>> + str tmp1, .mck_count
>> +#endif
>>
>> /*
>> * ldrne below are here to preload their address in the TLB as access
>> @@ -1132,6 +1201,10 @@ ENDPROC(at91_pm_suspend_in_sram)
>> .word 0
>> .pmc_version:
>> .word 0
>> +#ifdef CONFIG_SOC_SAMA7
>> +.mck_count:
>> + .word 0
>> +#endif
>> .saved_mckr:
>> .word 0
>> .saved_pllar:
>> @@ -1155,6 +1228,16 @@ ENDPROC(at91_pm_suspend_in_sram)
>> .word 0
>> .saved_mck4:
>> .word 0
>> +.saved_mck5:
>> + .word 0
>> +.saved_mck6:
>> + .word 0
>> +.saved_mck7:
>> + .word 0
>> +.saved_mck8:
>> + .word 0
>> +.saved_mck9:
>> + .word 0
>> #endif
>>
>> ENTRY(at91_pm_suspend_in_sram_sz)
>
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH v2 12/15] ARM: at91: pm: Enable ULP0 for SAMA7D65
2025-02-14 18:09 ` Ryan.Wanner
@ 2025-02-17 7:18 ` Claudiu Beznea
2025-02-19 15:24 ` Ryan.Wanner
0 siblings, 1 reply; 43+ messages in thread
From: Claudiu Beznea @ 2025-02-17 7:18 UTC (permalink / raw)
To: Ryan.Wanner, lee, robh, krzk+dt, conor+dt, sre, Nicolas.Ferre,
alexandre.belloni, p.zabel
Cc: linux, devicetree, linux-kernel, linux-pm, linux-arm-kernel,
linux-rtc
Hi, Ryan,
On 14.02.2025 20:09, Ryan.Wanner@microchip.com wrote:
> On 2/13/25 01:20, Claudiu Beznea wrote:
>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>
>> Hi, Ryan,
>>
>>
>> On 10.02.2025 23:13, Ryan.Wanner@microchip.com wrote:
>>> From: Ryan Wanner <Ryan.Wanner@microchip.com>
>>>
>>> New clocks are saved to enable ULP0 for SAMA7D65 because this SoC has a
>>> total of 10 main clocks that need to be saved for ULP0 mode.
>>
>> Isn't 9 the total number of MCKs that are handled in the last/first phase
>> of suspend/resume?
> Yes I was including 10 to match the indexing in the mck_count variable.
> Since bgt instruction was suggested I will correct this to reflect the
> true behavior of the change.
>>
>> Also, the state of MCKs are saved/restored for ULP0 and ULP1 as well.
>>
>>>
>>> Add mck_count member to at91_pm_data, this will be used to determine
>>> how many mcks need to be saved. In the mck_count member will also make
>>> sure that no unnecessary clock settings are written during
>>> mck_ps_restore.
>>>
>>> Add SHDWC to ULP0 mapping to clear the SHDWC status after exiting low
>>> power modes.
>>
>> Can you explain why this clear need to be done? The commit message should
>> answer to the "what?" and "why?" questions.
>>
>>>
>>> Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com>
>>> Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
>>> ---
>>> arch/arm/mach-at91/pm.c | 19 +++++-
>>> arch/arm/mach-at91/pm.h | 1 +
>>> arch/arm/mach-at91/pm_data-offsets.c | 2 +
>>> arch/arm/mach-at91/pm_suspend.S | 97 ++++++++++++++++++++++++++--
>>> 4 files changed, 110 insertions(+), 9 deletions(-)
>>>
>>> diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
>>> index 55cab31ce1ecb..50bada544eede 100644
>>> --- a/arch/arm/mach-at91/pm.c
>>> +++ b/arch/arm/mach-at91/pm.c
>>> @@ -1337,6 +1337,7 @@ struct pmc_info {
>>> unsigned long uhp_udp_mask;
>>> unsigned long mckr;
>>> unsigned long version;
>>> + unsigned long mck_count;> };
>>>
>>> static const struct pmc_info pmc_infos[] __initconst = {
>>> @@ -1344,30 +1345,42 @@ static const struct pmc_info pmc_infos[] __initconst = {
>>> .uhp_udp_mask = AT91RM9200_PMC_UHP | AT91RM9200_PMC_UDP,
>>> .mckr = 0x30,
>>> .version = AT91_PMC_V1,
>>> + .mck_count = 1,
>>
>> As this member is used only for SAMA7 SoCs I would drop it here and above
>> (where initialized with 1).
>>
>>> },
>>>
>>> {
>>> .uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP,
>>> .mckr = 0x30,
>>> .version = AT91_PMC_V1,
>>> + .mck_count = 1,
>>> },
>>> {
>>> .uhp_udp_mask = AT91SAM926x_PMC_UHP,
>>> .mckr = 0x30,
>>> .version = AT91_PMC_V1,
>>> + .mck_count = 1,
>>> },
>>> { .uhp_udp_mask = 0,
>>> .mckr = 0x30,
>>> .version = AT91_PMC_V1,
>>> + .mck_count = 1,
>>> },
>>> {
>>> .uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP,
>>> .mckr = 0x28,
>>> .version = AT91_PMC_V2,
>>> + .mck_count = 1,
>>> },
>>> {
>>> .mckr = 0x28,
>>> .version = AT91_PMC_V2,
>>> + .mck_count = 5,
>>
>> I'm not sure mck_count is a good name when used like proposed in this
>> patch. We know that only 4 MCKs need to be handled for SAMA7G5 and 9 for
>> SAMA7D65.
>>
>> Maybe, better change it here to 4 (.mck_count = 4) and to 9 above
>> (.mck_count = 9) and adjust properly the assembly macros (see below)? What
>> do you think?
>
> Yes I think this is better and cleaner to read. Should this mck_count
> match the pmc_mck_count variable name? Or should this be more
> descriptive or would mcks be sufficient.
mck_count/mcks should be enough. These will be anyway in the context of
pmc_info.
>>
>>> + },
>>> + {
>>> + .uhp_udp_mask = AT91SAM926x_PMC_UHP,
>>> + .mckr = 0x28,
>>> + .version = AT91_PMC_V2,
>>> + .mck_count = 10,
>>> },
>>>
>>> };
>>> @@ -1386,7 +1399,7 @@ static const struct of_device_id atmel_pmc_ids[] __initconst = {
>>> { .compatible = "atmel,sama5d2-pmc", .data = &pmc_infos[1] },
>>> { .compatible = "microchip,sam9x60-pmc", .data = &pmc_infos[4] },
>>> { .compatible = "microchip,sam9x7-pmc", .data = &pmc_infos[4] },
>>> - { .compatible = "microchip,sama7d65-pmc", .data = &pmc_infos[4] },
>>> + { .compatible = "microchip,sama7d65-pmc", .data = &pmc_infos[6] },
>>> { .compatible = "microchip,sama7g5-pmc", .data = &pmc_infos[5] },
>>> { /* sentinel */ },
>>> };
>>> @@ -1457,6 +1470,7 @@ static void __init at91_pm_init(void (*pm_idle)(void))
>>> soc_pm.data.uhp_udp_mask = pmc->uhp_udp_mask;
>>> soc_pm.data.pmc_mckr_offset = pmc->mckr;
>>> soc_pm.data.pmc_version = pmc->version;
>>> + soc_pm.data.pmc_mck_count = pmc->mck_count;
>>>
>>> if (pm_idle)
>>> arm_pm_idle = pm_idle;
>>> @@ -1659,7 +1673,8 @@ void __init sama7_pm_init(void)
>>> AT91_PM_STANDBY, AT91_PM_ULP0, AT91_PM_ULP1, AT91_PM_BACKUP,
>>> };
>>> static const u32 iomaps[] __initconst = {
>>> - [AT91_PM_ULP0] = AT91_PM_IOMAP(SFRBU),
>>> + [AT91_PM_ULP0] = AT91_PM_IOMAP(SFRBU) |
>>> + AT91_PM_IOMAP(SHDWC),
>>
>> In theory, as the wakeup sources can also resumes the system from standby
>> (WFI), the shdwc should be mapped for standby, too. Unless I'm wrong and
>> the wakeup sources covered by the SHDWC_SR register don't apply to standby
>> (WFI).
> The device can wake up from an RTT or RTC alarm event on both the
> standby power mode and the ULP0 power mode, since the RTT/RTC are
> included in the SHDWC_SR I think it is safe to have this.
> If I understand what you are asking correctly.
I was asking if the SHDWC should also be mapped for standby like:
static const u32 iomaps[] __initconst = {
[AT91_PM_STANDBY] = AT91_PM_IOMAP(SHDWC) |
[AT91_PM_ULP0] = AT91_PM_IOMAP(SFRBU) |
AT91_PM_IOMAP(SHDWC),
[AT91_PM_ULP1] = AT91_PM_IOMAP(SFRBU) |
AT91_PM_IOMAP(SHDWC) |
AT91_PM_IOMAP(ETHC),
[AT91_PM_BACKUP] = AT91_PM_IOMAP(SFRBU) |
AT91_PM_IOMAP(SHDWC),
};
>>
>>
>>> [AT91_PM_ULP1] = AT91_PM_IOMAP(SFRBU) |
>>> AT91_PM_IOMAP(SHDWC) |
>>> AT91_PM_IOMAP(ETHC),
>>> diff --git a/arch/arm/mach-at91/pm.h b/arch/arm/mach-at91/pm.h
>>> index 53bdc9000e447..ccde9c8728c27 100644
>>> --- a/arch/arm/mach-at91/pm.h
>>> +++ b/arch/arm/mach-at91/pm.h
>>> @@ -39,6 +39,7 @@ struct at91_pm_data {
>>> unsigned int suspend_mode;
>>> unsigned int pmc_mckr_offset;
>>> unsigned int pmc_version;
>>> + unsigned int pmc_mck_count;
>>> };
>>> #endif
>>>
>>> diff --git a/arch/arm/mach-at91/pm_data-offsets.c b/arch/arm/mach-at91/pm_data-offsets.c
>>> index 40bd4e8fe40a5..59a4838038381 100644
>>> --- a/arch/arm/mach-at91/pm_data-offsets.c
>>> +++ b/arch/arm/mach-at91/pm_data-offsets.c
>>> @@ -18,6 +18,8 @@ int main(void)
>>> pmc_mckr_offset));
>>> DEFINE(PM_DATA_PMC_VERSION, offsetof(struct at91_pm_data,
>>> pmc_version));
>>> + DEFINE(PM_DATA_PMC_MCK_COUNT, offsetof(struct at91_pm_data,
>>> + pmc_mck_count));
>>>
>>> return 0;
>>> }
>>> diff --git a/arch/arm/mach-at91/pm_suspend.S b/arch/arm/mach-at91/pm_suspend.S
>>> index e5869cca5e791..2bbcbb26adb28 100644
>>> --- a/arch/arm/mach-at91/pm_suspend.S
>>> +++ b/arch/arm/mach-at91/pm_suspend.S
>>> @@ -814,17 +814,19 @@ sr_dis_exit:
>>> .endm
>>>
>>> /**
>>> - * at91_mckx_ps_enable: save MCK1..4 settings and switch it to main clock
>>> + * at91_mckx_ps_enable: save MCK settings and switch it to main clock
>>> *
>>> - * Side effects: overwrites tmp1, tmp2
>>> + * Side effects: overwrites tmp1, tmp2, tmp3
>>> */
>>> .macro at91_mckx_ps_enable
>>> #ifdef CONFIG_SOC_SAMA7
>>> ldr pmc, .pmc_base
>>> + ldr tmp3, .mck_count
>>>
>>> - /* There are 4 MCKs we need to handle: MCK1..4 */
>>> + /* Start at MCK1 and go until MCK_count */
>>
>> s/MCK_count/mck_count to align with the mck_count above.
>>
>>> mov tmp1, #1
>>> -e_loop: cmp tmp1, #5
>>> +e_loop:
>>> + cmp tmp1, tmp3
>>> beq e_done
>>
>> If providing mck_count = 4 (for SAMA7G5) and mck_count = 9 (for SAMA7D65)
>> you can change this to:
>>
>> bqt e_done
>>
>>>
>>> /* Write MCK ID to retrieve the settings. */
>>> @@ -850,7 +852,37 @@ e_save_mck3:
>>> b e_ps
>>>
>>> e_save_mck4:
>>> + cmp tmp1, #4
>>> + bne e_save_mck5
>>> str tmp2, .saved_mck4
>>> + b e_ps
>>> +
>>> +e_save_mck5:
>>> + cmp tmp1, #5
>>> + bne e_save_mck6
>>> + str tmp2, .saved_mck5
>>> + b e_ps
>>> +
>>> +e_save_mck6:
>>> + cmp tmp1, #6
>>> + bne e_save_mck7
>>> + str tmp2, .saved_mck6
>>> + b e_ps
>>> +
>>> +e_save_mck7:
>>> + cmp tmp1, #7
>>> + bne e_save_mck8
>>> + str tmp2, .saved_mck7
>>> + b e_ps
>>> +
>>> +e_save_mck8:
>>> + cmp tmp1, #8
>>> + bne e_save_mck9
>>> + str tmp2, .saved_mck8
>>> + b e_ps
>>> +
>>> +e_save_mck9:
>>> + str tmp2, .saved_mck9
>>>
>>> e_ps:
>>> /* Use CSS=MAINCK and DIV=1. */
>>> @@ -870,17 +902,19 @@ e_done:
>>> .endm
>>>
>>> /**
>>> - * at91_mckx_ps_restore: restore MCK1..4 settings
>>> + * at91_mckx_ps_restore: restore MCKx settings
>>
>> s/MCKx/MCK to align with the description from at91_mckx_ps_enable
>>
>>> *
>>> * Side effects: overwrites tmp1, tmp2
>>> */
>>> .macro at91_mckx_ps_restore
>>> #ifdef CONFIG_SOC_SAMA7
>>> ldr pmc, .pmc_base
>>> + ldr tmp2, .mck_count
>>>
>>> - /* There are 4 MCKs we need to handle: MCK1..4 */
>>> + /* Start from MCK1 and go up to MCK_count */
>>> mov tmp1, #1
>>> -r_loop: cmp tmp1, #5
>>> +r_loop:
>>> + cmp tmp1, tmp2
>>> beq r_done
>>
>> Same here:
>> bgt r_done
>>
>> should be enough if providing mck_count = 4 or 9
>>
>>>
>>> r_save_mck1:
>>> @@ -902,7 +936,37 @@ r_save_mck3:
>>> b r_ps
>>>
>>> r_save_mck4:
>>> + cmp tmp1, #4
>>> + bne r_save_mck5
>>> ldr tmp2, .saved_mck4
>>> + b r_ps
>>> +
>>> +r_save_mck5:
>>> + cmp tmp1, #5
>>> + bne r_save_mck6
>>> + ldr tmp2, .saved_mck5
>>> + b r_ps
>>> +
>>> +r_save_mck6:
>>> + cmp tmp1, #6
>>> + bne r_save_mck7
>>> + ldr tmp2, .saved_mck6
>>> + b r_ps
>>> +
>>> +r_save_mck7:
>>> + cmp tmp1, #7
>>> + bne r_save_mck8
>>> + ldr tmp2, .saved_mck7
>>> + b r_ps
>>> +
>>> +r_save_mck8:
>>> + cmp tmp1, #8
>>> + bne r_save_mck9
>>> + ldr tmp2, .saved_mck8
>>> + b r_ps
>>> +
>>> +r_save_mck9:
>>> + ldr tmp2, .saved_mck9
>>>
>>> r_ps:
>>> /* Write MCK ID to retrieve the settings. */
>>> @@ -921,6 +985,7 @@ r_ps:
>>> wait_mckrdy tmp1
>>>
>>> add tmp1, tmp1, #1
>>> + ldr tmp2, .mck_count
>>
>> Or you can add tmp4 for this
>>
>>> b r_loop
>>> r_done:
>>> #endif
>>> @@ -1045,6 +1110,10 @@ ENTRY(at91_pm_suspend_in_sram)
>>> str tmp1, .memtype
>>> ldr tmp1, [r0, #PM_DATA_MODE]
>>> str tmp1, .pm_mode
>>> +#ifdef CONFIG_SOC_SAMA7
>>> + ldr tmp1, [r0, #PM_DATA_PMC_MCK_COUNT]
>>> + str tmp1, .mck_count
>>> +#endif
>>>
>>> /*
>>> * ldrne below are here to preload their address in the TLB as access
>>> @@ -1132,6 +1201,10 @@ ENDPROC(at91_pm_suspend_in_sram)
>>> .word 0
>>> .pmc_version:
>>> .word 0
>>> +#ifdef CONFIG_SOC_SAMA7
>>> +.mck_count:
>>> + .word 0
>>> +#endif
>>> .saved_mckr:
>>> .word 0
>>> .saved_pllar:
>>> @@ -1155,6 +1228,16 @@ ENDPROC(at91_pm_suspend_in_sram)
>>> .word 0
>>> .saved_mck4:
>>> .word 0
>>> +.saved_mck5:
>>> + .word 0
>>> +.saved_mck6:
>>> + .word 0
>>> +.saved_mck7:
>>> + .word 0
>>> +.saved_mck8:
>>> + .word 0
>>> +.saved_mck9:
>>> + .word 0
>>> #endif
>>>
>>> ENTRY(at91_pm_suspend_in_sram_sz)
>>
>
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH v2 12/15] ARM: at91: pm: Enable ULP0 for SAMA7D65
2025-02-17 7:18 ` Claudiu Beznea
@ 2025-02-19 15:24 ` Ryan.Wanner
2025-02-24 8:55 ` Claudiu Beznea
0 siblings, 1 reply; 43+ messages in thread
From: Ryan.Wanner @ 2025-02-19 15:24 UTC (permalink / raw)
To: claudiu.beznea, lee, robh, krzk+dt, conor+dt, sre, Nicolas.Ferre,
alexandre.belloni, p.zabel
Cc: linux, devicetree, linux-kernel, linux-pm, linux-arm-kernel,
linux-rtc
On 2/17/25 00:18, Claudiu Beznea wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> Hi, Ryan,
>
> On 14.02.2025 20:09, Ryan.Wanner@microchip.com wrote:
>> On 2/13/25 01:20, Claudiu Beznea wrote:
>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>>
>>> Hi, Ryan,
>>>
>>>
>>> On 10.02.2025 23:13, Ryan.Wanner@microchip.com wrote:
>>>> From: Ryan Wanner <Ryan.Wanner@microchip.com>
>>>>
>>>> New clocks are saved to enable ULP0 for SAMA7D65 because this SoC has a
>>>> total of 10 main clocks that need to be saved for ULP0 mode.
>>>
>>> Isn't 9 the total number of MCKs that are handled in the last/first phase
>>> of suspend/resume?
>> Yes I was including 10 to match the indexing in the mck_count variable.
>> Since bgt instruction was suggested I will correct this to reflect the
>> true behavior of the change.
>>>
>>> Also, the state of MCKs are saved/restored for ULP0 and ULP1 as well.
>>>
>>>>
>>>> Add mck_count member to at91_pm_data, this will be used to determine
>>>> how many mcks need to be saved. In the mck_count member will also make
>>>> sure that no unnecessary clock settings are written during
>>>> mck_ps_restore.
>>>>
>>>> Add SHDWC to ULP0 mapping to clear the SHDWC status after exiting low
>>>> power modes.
>>>
>>> Can you explain why this clear need to be done? The commit message should
>>> answer to the "what?" and "why?" questions.
>>>
>>>>
>>>> Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com>
>>>> Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
>>>> ---
>>>> arch/arm/mach-at91/pm.c | 19 +++++-
>>>> arch/arm/mach-at91/pm.h | 1 +
>>>> arch/arm/mach-at91/pm_data-offsets.c | 2 +
>>>> arch/arm/mach-at91/pm_suspend.S | 97 ++++++++++++++++++++++++++--
>>>> 4 files changed, 110 insertions(+), 9 deletions(-)
>>>>
>>>> diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
>>>> index 55cab31ce1ecb..50bada544eede 100644
>>>> --- a/arch/arm/mach-at91/pm.c
>>>> +++ b/arch/arm/mach-at91/pm.c
>>>> @@ -1337,6 +1337,7 @@ struct pmc_info {
>>>> unsigned long uhp_udp_mask;
>>>> unsigned long mckr;
>>>> unsigned long version;
>>>> + unsigned long mck_count;> };
>>>>
>>>> static const struct pmc_info pmc_infos[] __initconst = {
>>>> @@ -1344,30 +1345,42 @@ static const struct pmc_info pmc_infos[] __initconst = {
>>>> .uhp_udp_mask = AT91RM9200_PMC_UHP | AT91RM9200_PMC_UDP,
>>>> .mckr = 0x30,
>>>> .version = AT91_PMC_V1,
>>>> + .mck_count = 1,
>>>
>>> As this member is used only for SAMA7 SoCs I would drop it here and above
>>> (where initialized with 1).
>>>
>>>> },
>>>>
>>>> {
>>>> .uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP,
>>>> .mckr = 0x30,
>>>> .version = AT91_PMC_V1,
>>>> + .mck_count = 1,
>>>> },
>>>> {
>>>> .uhp_udp_mask = AT91SAM926x_PMC_UHP,
>>>> .mckr = 0x30,
>>>> .version = AT91_PMC_V1,
>>>> + .mck_count = 1,
>>>> },
>>>> { .uhp_udp_mask = 0,
>>>> .mckr = 0x30,
>>>> .version = AT91_PMC_V1,
>>>> + .mck_count = 1,
>>>> },
>>>> {
>>>> .uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP,
>>>> .mckr = 0x28,
>>>> .version = AT91_PMC_V2,
>>>> + .mck_count = 1,
>>>> },
>>>> {
>>>> .mckr = 0x28,
>>>> .version = AT91_PMC_V2,
>>>> + .mck_count = 5,
>>>
>>> I'm not sure mck_count is a good name when used like proposed in this
>>> patch. We know that only 4 MCKs need to be handled for SAMA7G5 and 9 for
>>> SAMA7D65.
>>>
>>> Maybe, better change it here to 4 (.mck_count = 4) and to 9 above
>>> (.mck_count = 9) and adjust properly the assembly macros (see below)? What
>>> do you think?
>>
>> Yes I think this is better and cleaner to read. Should this mck_count
>> match the pmc_mck_count variable name? Or should this be more
>> descriptive or would mcks be sufficient.
>
> mck_count/mcks should be enough. These will be anyway in the context of
> pmc_info.
>
>>>
>>>> + },
>>>> + {
>>>> + .uhp_udp_mask = AT91SAM926x_PMC_UHP,
>>>> + .mckr = 0x28,
>>>> + .version = AT91_PMC_V2,
>>>> + .mck_count = 10,
>>>> },
>>>>
>>>> };
>>>> @@ -1386,7 +1399,7 @@ static const struct of_device_id atmel_pmc_ids[] __initconst = {
>>>> { .compatible = "atmel,sama5d2-pmc", .data = &pmc_infos[1] },
>>>> { .compatible = "microchip,sam9x60-pmc", .data = &pmc_infos[4] },
>>>> { .compatible = "microchip,sam9x7-pmc", .data = &pmc_infos[4] },
>>>> - { .compatible = "microchip,sama7d65-pmc", .data = &pmc_infos[4] },
>>>> + { .compatible = "microchip,sama7d65-pmc", .data = &pmc_infos[6] },
>>>> { .compatible = "microchip,sama7g5-pmc", .data = &pmc_infos[5] },
>>>> { /* sentinel */ },
>>>> };
>>>> @@ -1457,6 +1470,7 @@ static void __init at91_pm_init(void (*pm_idle)(void))
>>>> soc_pm.data.uhp_udp_mask = pmc->uhp_udp_mask;
>>>> soc_pm.data.pmc_mckr_offset = pmc->mckr;
>>>> soc_pm.data.pmc_version = pmc->version;
>>>> + soc_pm.data.pmc_mck_count = pmc->mck_count;
>>>>
>>>> if (pm_idle)
>>>> arm_pm_idle = pm_idle;
>>>> @@ -1659,7 +1673,8 @@ void __init sama7_pm_init(void)
>>>> AT91_PM_STANDBY, AT91_PM_ULP0, AT91_PM_ULP1, AT91_PM_BACKUP,
>>>> };
>>>> static const u32 iomaps[] __initconst = {
>>>> - [AT91_PM_ULP0] = AT91_PM_IOMAP(SFRBU),
>>>> + [AT91_PM_ULP0] = AT91_PM_IOMAP(SFRBU) |
>>>> + AT91_PM_IOMAP(SHDWC),
>>>
>>> In theory, as the wakeup sources can also resumes the system from standby
>>> (WFI), the shdwc should be mapped for standby, too. Unless I'm wrong and
>>> the wakeup sources covered by the SHDWC_SR register don't apply to standby
>>> (WFI).
>> The device can wake up from an RTT or RTC alarm event on both the
>> standby power mode and the ULP0 power mode, since the RTT/RTC are
>> included in the SHDWC_SR I think it is safe to have this.
>> If I understand what you are asking correctly.
>
> I was asking if the SHDWC should also be mapped for standby like:
Ok I see. I have a better understanding now of wake up sources table
like you showed below. I think for readability of code I should not have
SHDWC set as ULP0 and STANDBY source because in at91_pm_config_ws()
SHDWC is only configured as a wake up source in ULP1 power mode.
So removing SHDWC from the ULP0 wake up source would reflect more
accurately what is configured as a wake up source in the code. What do
you think?
Best
Ryan
>
> static const u32 iomaps[] __initconst = {
>
> [AT91_PM_STANDBY] = AT91_PM_IOMAP(SHDWC) |
>
> [AT91_PM_ULP0] = AT91_PM_IOMAP(SFRBU) |
>
> AT91_PM_IOMAP(SHDWC),
>
> [AT91_PM_ULP1] = AT91_PM_IOMAP(SFRBU) |
>
> AT91_PM_IOMAP(SHDWC) |
>
> AT91_PM_IOMAP(ETHC),
>
> [AT91_PM_BACKUP] = AT91_PM_IOMAP(SFRBU) |
>
> AT91_PM_IOMAP(SHDWC),
>
> };
>
>
>
>>>
>>>
>>>> [AT91_PM_ULP1] = AT91_PM_IOMAP(SFRBU) |
>>>> AT91_PM_IOMAP(SHDWC) |
>>>> AT91_PM_IOMAP(ETHC),
>>>> diff --git a/arch/arm/mach-at91/pm.h b/arch/arm/mach-at91/pm.h
>>>> index 53bdc9000e447..ccde9c8728c27 100644
>>>> --- a/arch/arm/mach-at91/pm.h
>>>> +++ b/arch/arm/mach-at91/pm.h
>>>> @@ -39,6 +39,7 @@ struct at91_pm_data {
>>>> unsigned int suspend_mode;
>>>> unsigned int pmc_mckr_offset;
>>>> unsigned int pmc_version;
>>>> + unsigned int pmc_mck_count;
>>>> };
>>>> #endif
>>>>
>>>> diff --git a/arch/arm/mach-at91/pm_data-offsets.c b/arch/arm/mach-at91/pm_data-offsets.c
>>>> index 40bd4e8fe40a5..59a4838038381 100644
>>>> --- a/arch/arm/mach-at91/pm_data-offsets.c
>>>> +++ b/arch/arm/mach-at91/pm_data-offsets.c
>>>> @@ -18,6 +18,8 @@ int main(void)
>>>> pmc_mckr_offset));
>>>> DEFINE(PM_DATA_PMC_VERSION, offsetof(struct at91_pm_data,
>>>> pmc_version));
>>>> + DEFINE(PM_DATA_PMC_MCK_COUNT, offsetof(struct at91_pm_data,
>>>> + pmc_mck_count));
>>>>
>>>> return 0;
>>>> }
>>>> diff --git a/arch/arm/mach-at91/pm_suspend.S b/arch/arm/mach-at91/pm_suspend.S
>>>> index e5869cca5e791..2bbcbb26adb28 100644
>>>> --- a/arch/arm/mach-at91/pm_suspend.S
>>>> +++ b/arch/arm/mach-at91/pm_suspend.S
>>>> @@ -814,17 +814,19 @@ sr_dis_exit:
>>>> .endm
>>>>
>>>> /**
>>>> - * at91_mckx_ps_enable: save MCK1..4 settings and switch it to main clock
>>>> + * at91_mckx_ps_enable: save MCK settings and switch it to main clock
>>>> *
>>>> - * Side effects: overwrites tmp1, tmp2
>>>> + * Side effects: overwrites tmp1, tmp2, tmp3
>>>> */
>>>> .macro at91_mckx_ps_enable
>>>> #ifdef CONFIG_SOC_SAMA7
>>>> ldr pmc, .pmc_base
>>>> + ldr tmp3, .mck_count
>>>>
>>>> - /* There are 4 MCKs we need to handle: MCK1..4 */
>>>> + /* Start at MCK1 and go until MCK_count */
>>>
>>> s/MCK_count/mck_count to align with the mck_count above.
>>>
>>>> mov tmp1, #1
>>>> -e_loop: cmp tmp1, #5
>>>> +e_loop:
>>>> + cmp tmp1, tmp3
>>>> beq e_done
>>>
>>> If providing mck_count = 4 (for SAMA7G5) and mck_count = 9 (for SAMA7D65)
>>> you can change this to:
>>>
>>> bqt e_done
>>>
>>>>
>>>> /* Write MCK ID to retrieve the settings. */
>>>> @@ -850,7 +852,37 @@ e_save_mck3:
>>>> b e_ps
>>>>
>>>> e_save_mck4:
>>>> + cmp tmp1, #4
>>>> + bne e_save_mck5
>>>> str tmp2, .saved_mck4
>>>> + b e_ps
>>>> +
>>>> +e_save_mck5:
>>>> + cmp tmp1, #5
>>>> + bne e_save_mck6
>>>> + str tmp2, .saved_mck5
>>>> + b e_ps
>>>> +
>>>> +e_save_mck6:
>>>> + cmp tmp1, #6
>>>> + bne e_save_mck7
>>>> + str tmp2, .saved_mck6
>>>> + b e_ps
>>>> +
>>>> +e_save_mck7:
>>>> + cmp tmp1, #7
>>>> + bne e_save_mck8
>>>> + str tmp2, .saved_mck7
>>>> + b e_ps
>>>> +
>>>> +e_save_mck8:
>>>> + cmp tmp1, #8
>>>> + bne e_save_mck9
>>>> + str tmp2, .saved_mck8
>>>> + b e_ps
>>>> +
>>>> +e_save_mck9:
>>>> + str tmp2, .saved_mck9
>>>>
>>>> e_ps:
>>>> /* Use CSS=MAINCK and DIV=1. */
>>>> @@ -870,17 +902,19 @@ e_done:
>>>> .endm
>>>>
>>>> /**
>>>> - * at91_mckx_ps_restore: restore MCK1..4 settings
>>>> + * at91_mckx_ps_restore: restore MCKx settings
>>>
>>> s/MCKx/MCK to align with the description from at91_mckx_ps_enable
>>>
>>>> *
>>>> * Side effects: overwrites tmp1, tmp2
>>>> */
>>>> .macro at91_mckx_ps_restore
>>>> #ifdef CONFIG_SOC_SAMA7
>>>> ldr pmc, .pmc_base
>>>> + ldr tmp2, .mck_count
>>>>
>>>> - /* There are 4 MCKs we need to handle: MCK1..4 */
>>>> + /* Start from MCK1 and go up to MCK_count */
>>>> mov tmp1, #1
>>>> -r_loop: cmp tmp1, #5
>>>> +r_loop:
>>>> + cmp tmp1, tmp2
>>>> beq r_done
>>>
>>> Same here:
>>> bgt r_done
>>>
>>> should be enough if providing mck_count = 4 or 9
>>>
>>>>
>>>> r_save_mck1:
>>>> @@ -902,7 +936,37 @@ r_save_mck3:
>>>> b r_ps
>>>>
>>>> r_save_mck4:
>>>> + cmp tmp1, #4
>>>> + bne r_save_mck5
>>>> ldr tmp2, .saved_mck4
>>>> + b r_ps
>>>> +
>>>> +r_save_mck5:
>>>> + cmp tmp1, #5
>>>> + bne r_save_mck6
>>>> + ldr tmp2, .saved_mck5
>>>> + b r_ps
>>>> +
>>>> +r_save_mck6:
>>>> + cmp tmp1, #6
>>>> + bne r_save_mck7
>>>> + ldr tmp2, .saved_mck6
>>>> + b r_ps
>>>> +
>>>> +r_save_mck7:
>>>> + cmp tmp1, #7
>>>> + bne r_save_mck8
>>>> + ldr tmp2, .saved_mck7
>>>> + b r_ps
>>>> +
>>>> +r_save_mck8:
>>>> + cmp tmp1, #8
>>>> + bne r_save_mck9
>>>> + ldr tmp2, .saved_mck8
>>>> + b r_ps
>>>> +
>>>> +r_save_mck9:
>>>> + ldr tmp2, .saved_mck9
>>>>
>>>> r_ps:
>>>> /* Write MCK ID to retrieve the settings. */
>>>> @@ -921,6 +985,7 @@ r_ps:
>>>> wait_mckrdy tmp1
>>>>
>>>> add tmp1, tmp1, #1
>>>> + ldr tmp2, .mck_count
>>>
>>> Or you can add tmp4 for this
>>>
>>>> b r_loop
>>>> r_done:
>>>> #endif
>>>> @@ -1045,6 +1110,10 @@ ENTRY(at91_pm_suspend_in_sram)
>>>> str tmp1, .memtype
>>>> ldr tmp1, [r0, #PM_DATA_MODE]
>>>> str tmp1, .pm_mode
>>>> +#ifdef CONFIG_SOC_SAMA7
>>>> + ldr tmp1, [r0, #PM_DATA_PMC_MCK_COUNT]
>>>> + str tmp1, .mck_count
>>>> +#endif
>>>>
>>>> /*
>>>> * ldrne below are here to preload their address in the TLB as access
>>>> @@ -1132,6 +1201,10 @@ ENDPROC(at91_pm_suspend_in_sram)
>>>> .word 0
>>>> .pmc_version:
>>>> .word 0
>>>> +#ifdef CONFIG_SOC_SAMA7
>>>> +.mck_count:
>>>> + .word 0
>>>> +#endif
>>>> .saved_mckr:
>>>> .word 0
>>>> .saved_pllar:
>>>> @@ -1155,6 +1228,16 @@ ENDPROC(at91_pm_suspend_in_sram)
>>>> .word 0
>>>> .saved_mck4:
>>>> .word 0
>>>> +.saved_mck5:
>>>> + .word 0
>>>> +.saved_mck6:
>>>> + .word 0
>>>> +.saved_mck7:
>>>> + .word 0
>>>> +.saved_mck8:
>>>> + .word 0
>>>> +.saved_mck9:
>>>> + .word 0
>>>> #endif
>>>>
>>>> ENTRY(at91_pm_suspend_in_sram_sz)
>>>
>>
>
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH v2 12/15] ARM: at91: pm: Enable ULP0 for SAMA7D65
2025-02-19 15:24 ` Ryan.Wanner
@ 2025-02-24 8:55 ` Claudiu Beznea
0 siblings, 0 replies; 43+ messages in thread
From: Claudiu Beznea @ 2025-02-24 8:55 UTC (permalink / raw)
To: Ryan.Wanner, lee, robh, krzk+dt, conor+dt, sre, Nicolas.Ferre,
alexandre.belloni, p.zabel
Cc: linux, devicetree, linux-kernel, linux-pm, linux-arm-kernel,
linux-rtc
On 19.02.2025 17:24, Ryan.Wanner@microchip.com wrote:
> On 2/17/25 00:18, Claudiu Beznea wrote:
>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>
>> Hi, Ryan,
>>
>> On 14.02.2025 20:09, Ryan.Wanner@microchip.com wrote:
>>> On 2/13/25 01:20, Claudiu Beznea wrote:
>>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>>>
>>>> Hi, Ryan,
>>>>
>>>>
>>>> On 10.02.2025 23:13, Ryan.Wanner@microchip.com wrote:
>>>>> From: Ryan Wanner <Ryan.Wanner@microchip.com>
>>>>>
>>>>> New clocks are saved to enable ULP0 for SAMA7D65 because this SoC has a
>>>>> total of 10 main clocks that need to be saved for ULP0 mode.
>>>>
>>>> Isn't 9 the total number of MCKs that are handled in the last/first phase
>>>> of suspend/resume?
>>> Yes I was including 10 to match the indexing in the mck_count variable.
>>> Since bgt instruction was suggested I will correct this to reflect the
>>> true behavior of the change.
>>>>
>>>> Also, the state of MCKs are saved/restored for ULP0 and ULP1 as well.
>>>>
>>>>>
>>>>> Add mck_count member to at91_pm_data, this will be used to determine
>>>>> how many mcks need to be saved. In the mck_count member will also make
>>>>> sure that no unnecessary clock settings are written during
>>>>> mck_ps_restore.
>>>>>
>>>>> Add SHDWC to ULP0 mapping to clear the SHDWC status after exiting low
>>>>> power modes.
>>>>
>>>> Can you explain why this clear need to be done? The commit message should
>>>> answer to the "what?" and "why?" questions.
>>>>
>>>>>
>>>>> Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com>
>>>>> Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
>>>>> ---
>>>>> arch/arm/mach-at91/pm.c | 19 +++++-
>>>>> arch/arm/mach-at91/pm.h | 1 +
>>>>> arch/arm/mach-at91/pm_data-offsets.c | 2 +
>>>>> arch/arm/mach-at91/pm_suspend.S | 97 ++++++++++++++++++++++++++--
>>>>> 4 files changed, 110 insertions(+), 9 deletions(-)
>>>>>
>>>>> diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
>>>>> index 55cab31ce1ecb..50bada544eede 100644
>>>>> --- a/arch/arm/mach-at91/pm.c
>>>>> +++ b/arch/arm/mach-at91/pm.c
>>>>> @@ -1337,6 +1337,7 @@ struct pmc_info {
>>>>> unsigned long uhp_udp_mask;
>>>>> unsigned long mckr;
>>>>> unsigned long version;
>>>>> + unsigned long mck_count;> };
>>>>>
>>>>> static const struct pmc_info pmc_infos[] __initconst = {
>>>>> @@ -1344,30 +1345,42 @@ static const struct pmc_info pmc_infos[] __initconst = {
>>>>> .uhp_udp_mask = AT91RM9200_PMC_UHP | AT91RM9200_PMC_UDP,
>>>>> .mckr = 0x30,
>>>>> .version = AT91_PMC_V1,
>>>>> + .mck_count = 1,
>>>>
>>>> As this member is used only for SAMA7 SoCs I would drop it here and above
>>>> (where initialized with 1).
>>>>
>>>>> },
>>>>>
>>>>> {
>>>>> .uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP,
>>>>> .mckr = 0x30,
>>>>> .version = AT91_PMC_V1,
>>>>> + .mck_count = 1,
>>>>> },
>>>>> {
>>>>> .uhp_udp_mask = AT91SAM926x_PMC_UHP,
>>>>> .mckr = 0x30,
>>>>> .version = AT91_PMC_V1,
>>>>> + .mck_count = 1,
>>>>> },
>>>>> { .uhp_udp_mask = 0,
>>>>> .mckr = 0x30,
>>>>> .version = AT91_PMC_V1,
>>>>> + .mck_count = 1,
>>>>> },
>>>>> {
>>>>> .uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP,
>>>>> .mckr = 0x28,
>>>>> .version = AT91_PMC_V2,
>>>>> + .mck_count = 1,
>>>>> },
>>>>> {
>>>>> .mckr = 0x28,
>>>>> .version = AT91_PMC_V2,
>>>>> + .mck_count = 5,
>>>>
>>>> I'm not sure mck_count is a good name when used like proposed in this
>>>> patch. We know that only 4 MCKs need to be handled for SAMA7G5 and 9 for
>>>> SAMA7D65.
>>>>
>>>> Maybe, better change it here to 4 (.mck_count = 4) and to 9 above
>>>> (.mck_count = 9) and adjust properly the assembly macros (see below)? What
>>>> do you think?
>>>
>>> Yes I think this is better and cleaner to read. Should this mck_count
>>> match the pmc_mck_count variable name? Or should this be more
>>> descriptive or would mcks be sufficient.
>>
>> mck_count/mcks should be enough. These will be anyway in the context of
>> pmc_info.
>>
>>>>
>>>>> + },
>>>>> + {
>>>>> + .uhp_udp_mask = AT91SAM926x_PMC_UHP,
>>>>> + .mckr = 0x28,
>>>>> + .version = AT91_PMC_V2,
>>>>> + .mck_count = 10,
>>>>> },
>>>>>
>>>>> };
>>>>> @@ -1386,7 +1399,7 @@ static const struct of_device_id atmel_pmc_ids[] __initconst = {
>>>>> { .compatible = "atmel,sama5d2-pmc", .data = &pmc_infos[1] },
>>>>> { .compatible = "microchip,sam9x60-pmc", .data = &pmc_infos[4] },
>>>>> { .compatible = "microchip,sam9x7-pmc", .data = &pmc_infos[4] },
>>>>> - { .compatible = "microchip,sama7d65-pmc", .data = &pmc_infos[4] },
>>>>> + { .compatible = "microchip,sama7d65-pmc", .data = &pmc_infos[6] },
>>>>> { .compatible = "microchip,sama7g5-pmc", .data = &pmc_infos[5] },
>>>>> { /* sentinel */ },
>>>>> };
>>>>> @@ -1457,6 +1470,7 @@ static void __init at91_pm_init(void (*pm_idle)(void))
>>>>> soc_pm.data.uhp_udp_mask = pmc->uhp_udp_mask;
>>>>> soc_pm.data.pmc_mckr_offset = pmc->mckr;
>>>>> soc_pm.data.pmc_version = pmc->version;
>>>>> + soc_pm.data.pmc_mck_count = pmc->mck_count;
>>>>>
>>>>> if (pm_idle)
>>>>> arm_pm_idle = pm_idle;
>>>>> @@ -1659,7 +1673,8 @@ void __init sama7_pm_init(void)
>>>>> AT91_PM_STANDBY, AT91_PM_ULP0, AT91_PM_ULP1, AT91_PM_BACKUP,
>>>>> };
>>>>> static const u32 iomaps[] __initconst = {
>>>>> - [AT91_PM_ULP0] = AT91_PM_IOMAP(SFRBU),
>>>>> + [AT91_PM_ULP0] = AT91_PM_IOMAP(SFRBU) |
>>>>> + AT91_PM_IOMAP(SHDWC),
>>>>
>>>> In theory, as the wakeup sources can also resumes the system from standby
>>>> (WFI), the shdwc should be mapped for standby, too. Unless I'm wrong and
>>>> the wakeup sources covered by the SHDWC_SR register don't apply to standby
>>>> (WFI).
>>> The device can wake up from an RTT or RTC alarm event on both the
>>> standby power mode and the ULP0 power mode, since the RTT/RTC are
>>> included in the SHDWC_SR I think it is safe to have this.
>>> If I understand what you are asking correctly.
>>
>> I was asking if the SHDWC should also be mapped for standby like:
> Ok I see. I have a better understanding now of wake up sources table
> like you showed below. I think for readability of code I should not have
> SHDWC set as ULP0 and STANDBY source because in at91_pm_config_ws()
> SHDWC is only configured as a wake up source in ULP1 power mode.
>
> So removing SHDWC from the ULP0 wake up source would reflect more
> accurately what is configured as a wake up source in the code. What do
> you think?
Sounds good.
Thank you,
Claudiu
^ permalink raw reply [flat|nested] 43+ messages in thread
end of thread, other threads:[~2025-02-24 8:55 UTC | newest]
Thread overview: 43+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-02-10 21:13 [PATCH v2 00/15] Enable Power Modes Support for SAMA7D65 SoC Ryan.Wanner
2025-02-10 21:13 ` [PATCH v2 01/15] dt-bindings: mfd: syscon: add microchip,sama7d65-ddr3phy Ryan.Wanner
2025-02-11 8:12 ` Krzysztof Kozlowski
2025-02-11 8:12 ` Krzysztof Kozlowski
2025-02-10 21:13 ` [PATCH v2 02/15] dt-bindings: mfd: syscon: add microchip,sama7d65-sfrbu Ryan.Wanner
2025-02-11 8:14 ` Krzysztof Kozlowski
2025-02-11 8:14 ` Krzysztof Kozlowski
2025-02-13 20:30 ` Conor Dooley
2025-02-13 20:30 ` Conor Dooley
2025-02-14 7:20 ` Krzysztof Kozlowski
2025-02-14 7:20 ` Krzysztof Kozlowski
2025-02-10 21:13 ` [PATCH v2 03/15] dt-bindings: sram: Add microchip,sama7d65-sram Ryan.Wanner
2025-02-10 21:13 ` [PATCH v2 04/15] dt-bindings: power: reset: atmel,sama5d2-shdwc: Add microchip,sama7d65-shdwc Ryan.Wanner
2025-02-10 21:13 ` [PATCH v2 05/15] dt-bindings: reset: atmel,at91sam9260-reset: add microchip,sama7d65-rstc Ryan.Wanner
2025-02-14 8:27 ` Krzysztof Kozlowski
2025-02-14 8:27 ` Krzysztof Kozlowski
2025-02-10 21:13 ` [PATCH v2 06/15] dt-bindings: rtc: at91rm9200: add microchip,sama7d65-rtc Ryan.Wanner
2025-02-12 8:18 ` Claudiu Beznea
2025-02-14 8:27 ` Krzysztof Kozlowski
2025-02-14 8:27 ` Krzysztof Kozlowski
2025-02-10 21:13 ` [PATCH v2 07/15] dt-bindings: at91rm9260-rtt: add microchip,sama7d65-rtt Ryan.Wanner
2025-02-12 8:18 ` Claudiu Beznea
2025-02-14 8:28 ` Krzysztof Kozlowski
2025-02-14 8:28 ` Krzysztof Kozlowski
2025-02-10 21:13 ` [PATCH v2 08/15] ARM: at91: Add PM support to sama7d65 Ryan.Wanner
2025-02-10 21:13 ` [PATCH v2 09/15] ARM: at91: pm: fix at91_suspend_finish for ZQ calibration Ryan.Wanner
2025-02-12 8:17 ` Claudiu Beznea
2025-02-10 21:13 ` [PATCH v2 10/15] ARM: at91: pm: add DT compatible support for sama7d65 Ryan.Wanner
2025-02-12 8:20 ` Claudiu Beznea
2025-02-10 21:13 ` [PATCH v2 11/15] ARM: at91: PM: Add Backup mode for SAMA7D65 Ryan.Wanner
2025-02-12 8:15 ` Claudiu Beznea
2025-02-10 21:13 ` [PATCH v2 12/15] ARM: at91: pm: Enable ULP0 " Ryan.Wanner
2025-02-13 8:20 ` Claudiu Beznea
2025-02-14 18:09 ` Ryan.Wanner
2025-02-17 7:18 ` Claudiu Beznea
2025-02-19 15:24 ` Ryan.Wanner
2025-02-24 8:55 ` Claudiu Beznea
2025-02-10 21:13 ` [PATCH v2 13/15] power: reset: at91-sama5d2_shdwc: Add sama7d65 PMC Ryan.Wanner
2025-02-12 8:20 ` Claudiu Beznea
2025-02-10 21:13 ` [PATCH v2 14/15] ARM: dts: microchip: sama7d65: Add Reset and Shutdown and PM support Ryan.Wanner
2025-02-13 8:28 ` Claudiu Beznea
2025-02-10 21:13 ` [PATCH v2 15/15] ARM: dts: microchip: add shutdown controller and rtt timer Ryan.Wanner
2025-02-13 8:30 ` Claudiu Beznea
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