From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 01EC6C19F28 for ; Wed, 3 Aug 2022 18:24:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238097AbiHCSYj (ORCPT ); Wed, 3 Aug 2022 14:24:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51582 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234206AbiHCSYb (ORCPT ); Wed, 3 Aug 2022 14:24:31 -0400 Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6C4FF1A81B for ; Wed, 3 Aug 2022 11:24:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1659551070; x=1691087070; h=message-id:date:mime-version:subject:to:cc:references: from:in-reply-to:content-transfer-encoding; bh=7MIs88H3kyaIudtvk+y+X2Vp/M2JMQXQ5EcsqEQqpsM=; b=lFkSXGl2VynccmG8cfTEK4WLFCflGcLaPxBDqJIC12s45FZwfEKpaFcT 13w8ke/3L8DMoEYPgfSJ1+29gIGd02Anldtz9ydf6h6fWLtX6pW+AKBTS zN4Yl98n2osnDq66fNkGAom/gKsAcjyDt5rhk4qBg1iUI3NCfAO+7QWMK 2MZxbU3hizz/nj52Ang4jCLZSt496mC0G0sDwZSE8IBXgOC+OkPvl4ccS y1bgAFLq7Haiu/r0/GxF5/ycZHvii7pgtwJBwoKBP3cp2Lzoe1HOYEng8 MyvZa43fhZWx2lOv4ecM37TTTVq0VB9M6EZH7MMDFw8wxGqhK4gg82+I9 Q==; X-IronPort-AV: E=McAfee;i="6400,9594,10428"; a="289757185" X-IronPort-AV: E=Sophos;i="5.93,214,1654585200"; d="scan'208";a="289757185" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Aug 2022 11:24:30 -0700 X-IronPort-AV: E=Sophos;i="5.93,214,1654585200"; d="scan'208";a="631255924" Received: from buichris-mobl.amr.corp.intel.com (HELO [10.209.124.150]) ([10.209.124.150]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Aug 2022 11:24:29 -0700 Message-ID: Date: Wed, 3 Aug 2022 11:24:30 -0700 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.11.0 Subject: Re: [PATCH v1.1 1/2] x86/sev: Use per-CPU PSC structure in prep for unaccepted memory support Content-Language: en-US To: Tom Lendacky , linux-kernel@vger.kernel.org, x86@kernel.org Cc: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "Kirill A. Shutemov" , "H. Peter Anvin" , Michael Roth , Joerg Roedel , Andy Lutomirski , Peter Zijlstra References: <1b50311c-448b-96aa-1d96-f4bfed409c1f@amd.com> <2a2adc3570ae9c24d03fff877c4fe79ed43605e0.1659550264.git.thomas.lendacky@amd.com> <9f47ed0f-99cc-a237-f09b-45291feffcd3@amd.com> From: Dave Hansen In-Reply-To: <9f47ed0f-99cc-a237-f09b-45291feffcd3@amd.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 8/3/22 11:21, Tom Lendacky wrote: >> Would it be simpler to just do a spin_trylock_irqsave()?  You fall back >> to early_set_pages_state() whenever you can't acquire the lock. > > I was looking at that and can definitely go that route if this approach > is preferred. I prefer it for sure. This whole iteration does look good to me versus the per-cpu version, so I say go ahead with doing this for v2 once you wait a bit for any more feedback.