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Mon, 17 May 2021 08:49:00 -0700 (PDT) Received: from [172.16.22.144] ([45.235.253.15]) by smtp.gmail.com with ESMTPSA id x24sm518189vkn.40.2021.05.17.08.49.00 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 17 May 2021 08:49:00 -0700 (PDT) Subject: Re: [PATCH v6 77/82] target/arm: Fix decode for VDOT (indexed) To: Peter Maydell References: <20210430202610.1136687-1-richard.henderson@linaro.org> <20210430202610.1136687-78-richard.henderson@linaro.org> <47db40f0-52c4-f282-ecf9-eab2bdb7f1d1@linaro.org> From: Richard Henderson Message-ID: Date: Mon, 17 May 2021 10:48:58 -0500 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.8.1 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::e34; envelope-from=richard.henderson@linaro.org; helo=mail-vs1-xe34.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm , QEMU Developers Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 5/16/21 11:09 AM, Peter Maydell wrote: > On Sat, 15 May 2021 at 18:13, Richard Henderson > wrote: >> >> On 5/13/21 2:25 PM, Peter Maydell wrote: >>>> -VDOT_scalar 1111 1110 0 . 10 .... .... 1101 . q:1 index:1 u:1 rm:4 \ >>>> - vm=%vm_dp vn=%vn_dp vd=%vd_dp >>>> +VDOT_scalar 1111 1110 0 . 10 .... .... 1101 . q:1 index:1 u:1 vm:4 \ >>>> + vn=%vn_dp vd=%vd_dp >>> >>> Is it possible to make this kind of bug a decodetree error? >>> It seems unlikely that there's a use for having a bit which is >>> decoded both by a %foo field specification and also in some >>> other way... >> >> That's not what's happening here. This has separate fields "rm" and "vm" >> decoded in different ways. > > But they overlap: rm:4 in the pattern itself is using bits [3:0], > and "vm=%vm_dp" is also using [3:0] because the %vm_dp field > specifier is defined as "5:1 0:4". I'm suggesting that if the > pattern uses a field specifier we should check that none of the > bits in that field specifier are used in the pattern for some > other purpose (here 'u' and 'rm'). We do this, more or less, for sve: # Three register operand, with governing predicate, vector element size @rda_pg_rn_rm ........ esz:2 . rm:5 ... pg:3 rn:5 rd:5 \ &rprrr_esz ra=%reg_movprfx where ra and rd overlap. Though ra and rd overlap exactly, so perhaps that's not quite the same as vm above, overlapping both rm and index. r~