From: Tom Rini <trini-OWPKS81ov/FWk0Htik3J/w@public.gmane.org>
To: David Gibson <david-xT8FGy+AXnRB3Ne2BGzF6laj5H9X9Tb+@public.gmane.org>
Cc: "Rob Herring" <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>,
"André Przywara" <andre.przywara-5wv7dgnIgG8@public.gmane.org>,
"Simon Glass" <sjg-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>,
"Devicetree Compiler"
<devicetree-compiler-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>
Subject: Re: Size growth?
Date: Thu, 29 Oct 2020 11:04:01 -0400 [thread overview]
Message-ID: <20201029150401.GG5340@bill-the-cat> (raw)
In-Reply-To: <20201029030247.GJ5604-l+x2Y8Cxqc4e6aEkudXLsA@public.gmane.org>
[-- Attachment #1: Type: text/plain, Size: 10923 bytes --]
On Thu, Oct 29, 2020 at 02:02:47PM +1100, David Gibson wrote:
> On Wed, Oct 28, 2020 at 12:49:08PM -0500, Rob Herring wrote:
> > On Tue, Oct 27, 2020 at 11:26 PM David Gibson
> > <david-xT8FGy+AXnRB3Ne2BGzF6laj5H9X9Tb+@public.gmane.org> wrote:
> > >
> > > On Tue, Oct 27, 2020 at 02:55:17PM -0500, Rob Herring wrote:
> > > > On Tue, Oct 27, 2020 at 10:58 AM André Przywara <andre.przywara@arm.com> wrote:
> > > > >
> > > > > On 26/10/2020 21:51, Rob Herring wrote:
> > > > > > On Thu, Oct 22, 2020 at 10:23 AM Tom Rini <trini-OWPKS81ov/FWk0Htik3J/w@public.gmane.org> wrote:
> > > > > >> On Fri, Oct 23, 2020 at 01:58:04AM +1100, David Gibson wrote:
> > > > > >>> On Thu, Oct 22, 2020 at 08:32:54AM -0400, Tom Rini wrote:
> > > > > >>>> On Thu, Oct 22, 2020 at 03:00:13PM +1100, David Gibson wrote:
> > > > > >>>>> On Wed, Oct 21, 2020 at 06:49:14PM -0400, Tom Rini wrote:
> > > > > >
> > > > > > [...]
> > > > > >
> > > > > >>>>>> But what does all of this _mean_ ? I kinda think I have an answer now.
> > > > > >>>>>> One of the things that sticks out is 6dcb8ba408ec adds a lot and
> > > > > >>>>>> 11738cf01f15 reduces it just a little.
> > > > > >>>>>
> > > > > >>>>> Ah, that's a tricky one. If we don't handle unaligned accesses we
> > > > > >>>>> instead get intermittent bug reports where it just crashes.
> > > > > >>>>
> > > > > >>>> We really need to talk about that then. There was a problem of people
> > > > > >>>> turning off the sanity check for making sure the entire device tree was
> > > > > >>>> aligned and then having everything crash.
> > > > > >>>
> > > > > >>> Ok... I'm not really sure where you're going with that thought.
> > > > > >>
> > > > > >> In my reading of the mailing list history of how this issue came up,
> > > > > >> it was someone was booting a dragonboard or something, and they (or
> > > > > >> rather, the board maintainer set by default) the flag to use the device
> > > > > >> tree wherever it is in memory and NOT to relocate it to a properly
> > > > > >> aligned address. This in turn lead to the kernel getting an unaligned
> > > > > >> device tree and everything crashing. The "I know what I'm doing" flag
> > > > > >> was set, violated the documented requirements for device trees need to
> > > > > >> reside in memory and everything blew up.
> > > > > >>
> > > > > >> After that it was noticed that there could be some internal
> > > > > >> mis-alignment and if you tried those accesses on a CPU that doesn't
> > > > > >> support doing those reads easily there could be problems, but that's not
> > > > > >> a common at all case (as noted by it not having been seen in practice).
> > > > > >
> > > > > > Nor a problem on many environments to begin with. More below...
> > > > > >
> > > > > >>>>> I suppose we could add an ASSUME_ALIGNED_ACCESS flag, and it will just
> > > > > >>>>> break for either an unaligned dtb (unlikely) or if you attempt to load
> > > > > >>>>> an unaligned value from a property (more likely, but don't add the
> > > > > >>>>> flag if you're not sure you don't need it).
> > > > > >>>>
> > > > > >>>> So long as it's abstracted in such a way that we don't grow the size of
> > > > > >>>> everything again, yes, that is the right way forward I think.
> > > > > >>>
> > > > > >>> All the ASSUME flags should be resolved at compile time (at least with
> > > > > >>> normal optimization levels enabled in the compiler), so testing for
> > > > > >>> those shouldn't increase size at all. If they do, something is wrong.
> > > > > >>
> > > > > >> I'm saying that how ever this new ASSUME flag is done, it needs to be
> > > > > >> done in such a way the compiler really will be smart about it. So
> > > > > >> something like making a new function that does fdt64_ld() if we aren't
> > > > > >> ASSUME_ALIGNED_ACCESS and fdt64_to_cpu() if we are
> > > > > >> ASSUME_ALIGNED_ACCESS.
> > > > > >
> > > > > > Ah, unaligned accesses again... To summarize, both performance and
> > > > > > size suffer with not doing unaligned accesses.
> > > > > >
> > > > > > Why not a HAS_UNALIGNED_ACCESS flag instead (or the inverse) that will
> > > > > > do unaligned accesses? That would be more aligned with what the system
> > > > > > can support rather than sanity checking associated with ASSUME_*.
> > >
> > > So, there are kind of two things here, (1) is "my platform can handle
> > > unaligned accesses" and (2) is "assume I don't need unaligned
> > > accesses". We can use the fast & small versions of fdt32_ld() etc. if
> > > either is true. However we need to consider those separately, because
> > > they can be independently true (or not) for different reasons. (1)
> > > depends on the hardware, whereas (2) depends on how you're using dtc,
> > > and, see below, you may need at least unaligned-handling fdt64_ld() in
> > > more cases than you think.
> >
> > Okay, I guess you were thinking of (2) for ASSUME_ALIGNED_ACCESS, but
> > I read it as (1).
>
> Yes.
>
> > > > > > To repeat from last time, everything ARMv6 and up can do unaligned
> > > > > > accesses if enabled.
> > > > >
> > > > > But that requires the MMU to be enabled, doesn't it? If I read the ARM
> > > > > ARM correctly, unaligned accesses always trap on device memory,
> > > > > regardless of SCTLR.A. And without the MMU enabled everything is device
> > > > > memory. We compile U-Boot with -mno-unaligned-access/-mstrict-align to
> > > > > cope with that, and that most likely affects libfdt as well?
> > > >
> > > > Ah yes, I think you are right.
> > > >
> > > > In that case, seems like we should figure out whether (internal)
> > > > unaligned accesses are possible with dtc generated dtbs at least
> > > > rather than just "not a common at all case (as noted by it not having
> > > > been seen in practice)." I'm sure David will point out that not all
> > > > dtbs come from dtc, but all the ones u-boot deals with do in
> > > > reality.
> > >
> > > Assuming the blob itself is 8-byte aligned in memory, then all
> > > structural elements (i.e. the tree metadata) of a compliant dtb will
> > > be naturally aligned. The spec requires 8-byte alignment of the mem
> > > reserve block w.r.t. the base of the blob and 4 byte aligned structure
> > > block w.r.t. the base of the blob. Likewise the layout of the mem
> > > reserve block will preserve 8-byte alignment of all the 64-bit values
> > > it contains, assuming the block itself starts 8-byte aligned.
> > > Similarly the structure blob will preserve 4-byte alignment of all its
> > > tags and other structural data (this amounts to requiring an alignment
> > > gap after node names and property values).
> > >
> > > However, "all structural elements" does not include values within
> > > property values themselves. Assuming propery alignment of the blocks
> > > and the blob itself, then all property values will *begin* 4 byte
> > > aligned. However that leaves two relevant cases:
> > >
> > > a) 64-bit property values may be 4-byte aligned but not 8-byte
> > > aligned
> >
> > I'd assume that while an arch may support only the above in terms of
> > misalignment, an arch that supports any alignment would always support
> > this as part of that. It would just be odd to support byte alignment
> > only up to 32-bit.
>
> Yes, I'd expect so.
>
> > I don't think we need to optimize the former case.
>
> I don't see how we would, in any case.
>
> > > b) complex property values including both strings and integers
> > > typically use a packed representation with no alignment gaps.
> > > Such property structures are usually avoided in modern bindings,
> > > but they definitely exist in a bunch of older bindings. Obviously
> > > that means that integer values sitting after arbitrary length
> > > strings may not have any natural alignment
> >
> > That's the user's problem IMO. Users of older bindings having this
> > aren't likely using a newish function like fdt32_ld either.
>
> That doesn't follow. The bindings still exist and are in use, e.g. on
> IBM PAPR systems, that's not correlated to how recent teh libfdt is.
>
> > > So acccesses made by libfdt internally should be safe(*) assuming the
> > > blob itself is loaded 8-byte aligned, and the dtb is compliant.
> > > However the libfdt user may hit both problems (a) and (b) getting
> > > things they actually want from the tree. fdt{32,64}_{ld,st}() are
> > > intended to handle those cases, so that they're useful for the caller
> > > to pull things from properties as well as for libfdt internal
> > > accesses.
> > >
> > > (*) There are a number of other functions that looked like they might
> > > be dangerous for case (a) because they are based on 64-bit
> > > property values: fdt_setprop_inplace_u64(), fdt_property_u64(),
> > > fdt_setprop_u64(), fdt_appendprop_u64() and
> > > fdt_appendprop_addrrange(). However I think they're actually
> > > ok, because the way they're built in terms of other functions
> > > means there's implicitly a memcpy() from a byte buffer.
> > >
> > > > > Also some 32-bit ARM platforms run U-Boot proper with the MMU disabled
> > > > > all the time, and I know of at least the sunxi-aarch64 SPL running with
> > > > > the MMU off as well.
> > > >
> > > > I'm making a mental note of this for the next time performance issues come up.
> > >
> > > Right, running early with MMU off is definitely a real use case for
> > > libfdt. For similar reasons we can't assume we have an OS which will
> > > trap and handle unaligned accesses, which we might for a more
> > > conventional userspace library.
> > >
> > > This kind of underscores why I'm a bit hesitant to introduce "my
> > > platform handles unaligned acccesses" flag. Not only does it require
> > > detailed knowledge of the target CPU, but it can also depend on
> > > exactly what mode that hardware is in.
> >
> > I think there's a more simple solution with no flags. Given all
> > internal accesses are at least 4-byte aligned, libfdt should just do
> > 32-bit accesses internally (as it used to). Maybe we need a check up
> > front that the dtb is 8-byte aligned though.
>
> That's not a bad idea. We could do it in fdt_ro_probe_().
>
> Although, one extra case occurs to me. Someone (is it uboot?) has a
> wacky format where dtbs for several platforms, along with kernels and
> other information are bundled together in a big dtb (that is, using
> the dtb encoding, even though it's not actually a device tree). The
> "sub-dtbs" in that will be 4-byte aligned, but maybe not 8-byte
> aligned.
Yes, about 12 years ago now U-Boot introduced (but it's useful anywhere,
really...) FIT images which are what you're thinking of. That's
unrelated to all of this however.
--
Tom
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next prev parent reply other threads:[~2020-10-29 15:04 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-10-16 19:36 Size growth? Tom Rini
2020-10-16 21:46 ` Simon Glass
[not found] ` <CAPnjgZ3jPciWmoVpuoYb9KC2h3eCevZsq+1BzefCOCAFCDoseQ-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2020-10-19 1:42 ` David Gibson
[not found] ` <20201019014213.GA11625-l+x2Y8Cxqc4e6aEkudXLsA@public.gmane.org>
2020-10-19 12:37 ` Tom Rini
2020-10-20 2:09 ` David Gibson
[not found] ` <20201020020907.GA64103-l+x2Y8Cxqc4e6aEkudXLsA@public.gmane.org>
2020-10-21 22:49 ` Tom Rini
2020-10-22 4:00 ` David Gibson
[not found] ` <20201022040013.GB1821515-l+x2Y8Cxqc4e6aEkudXLsA@public.gmane.org>
2020-10-22 12:32 ` Tom Rini
2020-10-22 14:58 ` David Gibson
[not found] ` <20201022145804.GI1821515-l+x2Y8Cxqc4e6aEkudXLsA@public.gmane.org>
2020-10-22 15:22 ` Tom Rini
2020-10-26 21:51 ` Rob Herring
[not found] ` <CAL_JsqJiKETTMJX3MsEmECE+jtbwYydVSgt1a6poz_L+pPRFTA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2020-10-26 22:17 ` Tom Rini
2020-10-27 15:57 ` André Przywara
[not found] ` <a14daf09-4d97-052f-5071-09e67ccb925e-5wv7dgnIgG8@public.gmane.org>
2020-10-27 19:55 ` Rob Herring
[not found] ` <CAL_JsqK_fC346UnCmXMJxKHCM6=eFBF_kmGt_fBdvwPXbPRkvw-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2020-10-28 4:26 ` David Gibson
[not found] ` <20201028042601.GA5604-l+x2Y8Cxqc4e6aEkudXLsA@public.gmane.org>
2020-10-28 12:05 ` Tom Rini
2020-10-29 2:55 ` David Gibson
[not found] ` <20201029025503.GI5604-l+x2Y8Cxqc4e6aEkudXLsA@public.gmane.org>
2020-10-29 15:06 ` Tom Rini
2020-10-29 15:48 ` Rob Herring
[not found] ` <CAL_JsqJUixnyZx-tu9EV8YZ-gSDE7i1jvMddnNZZWFzezaHftw-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2020-10-29 16:04 ` Tom Rini
2020-10-29 18:08 ` Rob Herring
[not found] ` <CAL_JsqJTTJAoTYwxDn3i0KETMXLyGg3WXzxN3-OdRLx=R96a-Q-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2020-10-29 20:21 ` Tom Rini
2020-11-02 2:06 ` David Gibson
2020-10-28 17:49 ` Rob Herring
[not found] ` <CAL_JsqJPrnjKjdmvyY2NOay0YrYc20Tr3OSr0yjq+9HjCN+anA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2020-10-29 3:02 ` David Gibson
[not found] ` <20201029030247.GJ5604-l+x2Y8Cxqc4e6aEkudXLsA@public.gmane.org>
2020-10-29 15:04 ` Tom Rini [this message]
2020-10-29 19:56 ` David Gibson
[not found] ` <20201029195658.GK5604-l+x2Y8Cxqc4e6aEkudXLsA@public.gmane.org>
2020-10-29 20:26 ` Tom Rini
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