* [PATCH 1/2] drm/i915/gt: Disable HW load balancing for CCS
2024-02-15 13:59 Andi Shyti
@ 2024-02-15 13:59 ` Andi Shyti
2024-02-15 16:55 ` Matt Roper
0 siblings, 1 reply; 13+ messages in thread
From: Andi Shyti @ 2024-02-15 13:59 UTC (permalink / raw
To: intel-gfx, dri-devel
Cc: Chris Wilson, Joonas Lahtinen, Matt Roper, stable, Andi Shyti,
Andi Shyti
The hardware should not dynamically balance the load between CCS
engines. Wa_16016805146 recommends disabling it across all
platforms.
Fixes: d2eae8e98d59 ("drm/i915/dg2: Drop force_probe requirement")
Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
Cc: Chris Wilson <chris.p.wilson@linux.intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: <stable@vger.kernel.org> # v6.2+
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 +
drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 ++++++
2 files changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 50962cfd1353..cf709f6c05ae 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -1478,6 +1478,7 @@
#define GEN12_RCU_MODE _MMIO(0x14800)
#define GEN12_RCU_MODE_CCS_ENABLE REG_BIT(0)
+#define XEHP_RCU_MODE_FIXED_SLICE_CCS_MODE REG_BIT(1)
#define CHV_FUSE_GT _MMIO(VLV_GUNIT_BASE + 0x2168)
#define CHV_FGT_DISABLE_SS0 (1 << 10)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index d67d44611c28..7f42c8015f71 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -2988,6 +2988,12 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
wa_mcr_masked_en(wal, GEN8_HALF_SLICE_CHICKEN1,
GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE);
}
+
+ /*
+ * Wa_16016805146: disable the CCS load balancing
+ * indiscriminately for all the platforms
+ */
+ wa_masked_en(wal, GEN12_RCU_MODE, XEHP_RCU_MODE_FIXED_SLICE_CCS_MODE);
}
static void
--
2.43.0
^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCH 1/2] drm/i915/gt: Disable HW load balancing for CCS
2024-02-15 13:59 ` [PATCH 1/2] drm/i915/gt: Disable HW load balancing for CCS Andi Shyti
@ 2024-02-15 16:55 ` Matt Roper
2024-02-19 10:17 ` Andi Shyti
0 siblings, 1 reply; 13+ messages in thread
From: Matt Roper @ 2024-02-15 16:55 UTC (permalink / raw
To: Andi Shyti
Cc: intel-gfx, dri-devel, Chris Wilson, Joonas Lahtinen, stable,
Andi Shyti
On Thu, Feb 15, 2024 at 02:59:23PM +0100, Andi Shyti wrote:
> The hardware should not dynamically balance the load between CCS
> engines. Wa_16016805146 recommends disabling it across all
Is this the right workaround number? When I check the database, this
workaround was rejected on both DG2-G10 and DG2-G11, and doesn't even
have an entry for DG2-G12.
There are other workarounds that sound somewhat related to load
balancing (e.g., part 3 of Wa_14019159160), but what's asked there is
more involved than just setting one register bit and conflicts a bit
with the second patch of this series.
Matt
> platforms.
>
> Fixes: d2eae8e98d59 ("drm/i915/dg2: Drop force_probe requirement")
> Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
> Cc: Chris Wilson <chris.p.wilson@linux.intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: <stable@vger.kernel.org> # v6.2+
> ---
> drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 +
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 ++++++
> 2 files changed, 7 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> index 50962cfd1353..cf709f6c05ae 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> @@ -1478,6 +1478,7 @@
>
> #define GEN12_RCU_MODE _MMIO(0x14800)
> #define GEN12_RCU_MODE_CCS_ENABLE REG_BIT(0)
> +#define XEHP_RCU_MODE_FIXED_SLICE_CCS_MODE REG_BIT(1)
>
> #define CHV_FUSE_GT _MMIO(VLV_GUNIT_BASE + 0x2168)
> #define CHV_FGT_DISABLE_SS0 (1 << 10)
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index d67d44611c28..7f42c8015f71 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -2988,6 +2988,12 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
> wa_mcr_masked_en(wal, GEN8_HALF_SLICE_CHICKEN1,
> GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE);
> }
> +
> + /*
> + * Wa_16016805146: disable the CCS load balancing
> + * indiscriminately for all the platforms
> + */
> + wa_masked_en(wal, GEN12_RCU_MODE, XEHP_RCU_MODE_FIXED_SLICE_CCS_MODE);
> }
>
> static void
> --
> 2.43.0
>
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 1/2] drm/i915/gt: Disable HW load balancing for CCS
2024-02-15 16:55 ` Matt Roper
@ 2024-02-19 10:17 ` Andi Shyti
2024-02-19 10:31 ` Andi Shyti
0 siblings, 1 reply; 13+ messages in thread
From: Andi Shyti @ 2024-02-19 10:17 UTC (permalink / raw
To: Matt Roper
Cc: Andi Shyti, intel-gfx, dri-devel, Chris Wilson, Joonas Lahtinen,
stable, Andi Shyti
Hi Matt,
On Thu, Feb 15, 2024 at 08:55:41AM -0800, Matt Roper wrote:
> On Thu, Feb 15, 2024 at 02:59:23PM +0100, Andi Shyti wrote:
> > The hardware should not dynamically balance the load between CCS
> > engines. Wa_16016805146 recommends disabling it across all
>
> Is this the right workaround number? When I check the database, this
> workaround was rejected on both DG2-G10 and DG2-G11, and doesn't even
> have an entry for DG2-G12.
>
> There are other workarounds that sound somewhat related to load
> balancing (e.g., part 3 of Wa_14019159160), but what's asked there is
> more involved than just setting one register bit and conflicts a bit
> with the second patch of this series.
thanks for checking it. Indeed the WA I mentioned is limited to
a specific platform. This recommendation comes in different WA,
e.g. this one: Wa_14019186972 (3rd point). Will start using that
as a reference.
Thank you.
Andi
>
>
> Matt
>
> > platforms.
> >
> > Fixes: d2eae8e98d59 ("drm/i915/dg2: Drop force_probe requirement")
> > Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
> > Cc: Chris Wilson <chris.p.wilson@linux.intel.com>
> > Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> > Cc: Matt Roper <matthew.d.roper@intel.com>
> > Cc: <stable@vger.kernel.org> # v6.2+
> > ---
> > drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 +
> > drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 ++++++
> > 2 files changed, 7 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> > index 50962cfd1353..cf709f6c05ae 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> > +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> > @@ -1478,6 +1478,7 @@
> >
> > #define GEN12_RCU_MODE _MMIO(0x14800)
> > #define GEN12_RCU_MODE_CCS_ENABLE REG_BIT(0)
> > +#define XEHP_RCU_MODE_FIXED_SLICE_CCS_MODE REG_BIT(1)
> >
> > #define CHV_FUSE_GT _MMIO(VLV_GUNIT_BASE + 0x2168)
> > #define CHV_FGT_DISABLE_SS0 (1 << 10)
> > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > index d67d44611c28..7f42c8015f71 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > @@ -2988,6 +2988,12 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
> > wa_mcr_masked_en(wal, GEN8_HALF_SLICE_CHICKEN1,
> > GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE);
> > }
> > +
> > + /*
> > + * Wa_16016805146: disable the CCS load balancing
> > + * indiscriminately for all the platforms
> > + */
> > + wa_masked_en(wal, GEN12_RCU_MODE, XEHP_RCU_MODE_FIXED_SLICE_CCS_MODE);
> > }
> >
> > static void
> > --
> > 2.43.0
> >
>
> --
> Matt Roper
> Graphics Software Engineer
> Linux GPU Platform Enablement
> Intel Corporation
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 1/2] drm/i915/gt: Disable HW load balancing for CCS
2024-02-19 10:17 ` Andi Shyti
@ 2024-02-19 10:31 ` Andi Shyti
0 siblings, 0 replies; 13+ messages in thread
From: Andi Shyti @ 2024-02-19 10:31 UTC (permalink / raw
To: Andi Shyti
Cc: Matt Roper, intel-gfx, dri-devel, Chris Wilson, Joonas Lahtinen,
stable, Andi Shyti
On Mon, Feb 19, 2024 at 11:17:33AM +0100, Andi Shyti wrote:
> On Thu, Feb 15, 2024 at 08:55:41AM -0800, Matt Roper wrote:
> > On Thu, Feb 15, 2024 at 02:59:23PM +0100, Andi Shyti wrote:
> > > The hardware should not dynamically balance the load between CCS
> > > engines. Wa_16016805146 recommends disabling it across all
> >
> > Is this the right workaround number? When I check the database, this
> > workaround was rejected on both DG2-G10 and DG2-G11, and doesn't even
> > have an entry for DG2-G12.
> >
> > There are other workarounds that sound somewhat related to load
> > balancing (e.g., part 3 of Wa_14019159160), but what's asked there is
> > more involved than just setting one register bit and conflicts a bit
> > with the second patch of this series.
>
> thanks for checking it. Indeed the WA I mentioned is limited to
> a specific platform. This recommendation comes in different WA,
> e.g. this one: Wa_14019186972 (3rd point). Will start using that
> as a reference.
actually you are right, I checked with Joonas and I will use
Wa_14019159160.
Thanks,
Andi
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH 0/2] Disable automatic load CCS load balancing
@ 2024-02-20 14:20 Andi Shyti
2024-02-20 14:20 ` [PATCH 1/2] drm/i915/gt: Disable HW load balancing for CCS Andi Shyti
` (3 more replies)
0 siblings, 4 replies; 13+ messages in thread
From: Andi Shyti @ 2024-02-20 14:20 UTC (permalink / raw
To: intel-gfx, dri-devel
Cc: Chris Wilson, Joonas Lahtinen, Matt Roper, John Harrison,
Tvrtko Ursulin, stable, Andi Shyti, Andi Shyti
Hi,
this series does basically two things:
1. Disables automatic load balancing as adviced by the hardware
workaround.
2. Forces the sharing of the load submitted to CCS among all the
CCS available (as of now only DG2 has more than one CCS). This
way the user, when sending a query, will see only one CCS
available.
Andi
Andi Shyti (2):
drm/i915/gt: Disable HW load balancing for CCS
drm/i915/gt: Set default CCS mode '1'
drivers/gpu/drm/i915/gt/intel_gt.c | 11 +++++++++++
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 3 +++
drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 ++++++
drivers/gpu/drm/i915/i915_drv.h | 17 +++++++++++++++++
drivers/gpu/drm/i915/i915_query.c | 5 +++--
5 files changed, 40 insertions(+), 2 deletions(-)
--
2.43.0
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH 1/2] drm/i915/gt: Disable HW load balancing for CCS
2024-02-20 14:20 [PATCH 0/2] Disable automatic load CCS load balancing Andi Shyti
@ 2024-02-20 14:20 ` Andi Shyti
2024-02-20 14:20 ` [PATCH 2/2] drm/i915/gt: Set default CCS mode '1' Andi Shyti
` (2 subsequent siblings)
3 siblings, 0 replies; 13+ messages in thread
From: Andi Shyti @ 2024-02-20 14:20 UTC (permalink / raw
To: intel-gfx, dri-devel
Cc: Chris Wilson, Joonas Lahtinen, Matt Roper, John Harrison,
Tvrtko Ursulin, stable, Andi Shyti, Andi Shyti
The hardware should not dynamically balance the load between CCS
engines. Wa_16016805146 recommends disabling it across all
platforms.
Fixes: d2eae8e98d59 ("drm/i915/dg2: Drop force_probe requirement")
Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
Cc: Chris Wilson <chris.p.wilson@linux.intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: <stable@vger.kernel.org> # v6.2+
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 +
drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 ++++++
2 files changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 50962cfd1353..cf709f6c05ae 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -1478,6 +1478,7 @@
#define GEN12_RCU_MODE _MMIO(0x14800)
#define GEN12_RCU_MODE_CCS_ENABLE REG_BIT(0)
+#define XEHP_RCU_MODE_FIXED_SLICE_CCS_MODE REG_BIT(1)
#define CHV_FUSE_GT _MMIO(VLV_GUNIT_BASE + 0x2168)
#define CHV_FGT_DISABLE_SS0 (1 << 10)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index d67d44611c28..7f42c8015f71 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -2988,6 +2988,12 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
wa_mcr_masked_en(wal, GEN8_HALF_SLICE_CHICKEN1,
GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE);
}
+
+ /*
+ * Wa_16016805146: disable the CCS load balancing
+ * indiscriminately for all the platforms
+ */
+ wa_masked_en(wal, GEN12_RCU_MODE, XEHP_RCU_MODE_FIXED_SLICE_CCS_MODE);
}
static void
--
2.43.0
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH 2/2] drm/i915/gt: Set default CCS mode '1'
2024-02-20 14:20 [PATCH 0/2] Disable automatic load CCS load balancing Andi Shyti
2024-02-20 14:20 ` [PATCH 1/2] drm/i915/gt: Disable HW load balancing for CCS Andi Shyti
@ 2024-02-20 14:20 ` Andi Shyti
2024-02-20 14:27 ` Tvrtko Ursulin
2024-02-27 12:18 ` Jani Nikula
2024-02-20 14:23 ` [PATCH 0/2] Disable automatic load CCS load balancing Andi Shyti
2024-02-20 14:34 ` Andi Shyti
3 siblings, 2 replies; 13+ messages in thread
From: Andi Shyti @ 2024-02-20 14:20 UTC (permalink / raw
To: intel-gfx, dri-devel
Cc: Chris Wilson, Joonas Lahtinen, Matt Roper, John Harrison,
Tvrtko Ursulin, stable, Andi Shyti, Andi Shyti
Since CCS automatic load balancing is disabled, we will impose a
fixed balancing policy that involves setting all the CCS engines
to work together on the same load.
Simultaneously, the user will see only 1 CCS rather than the
actual number. As of now, this change affects only DG2.
Fixes: d2eae8e98d59 ("drm/i915/dg2: Drop force_probe requirement")
Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
Cc: Chris Wilson <chris.p.wilson@linux.intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: <stable@vger.kernel.org> # v6.2+
---
drivers/gpu/drm/i915/gt/intel_gt.c | 11 +++++++++++
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 2 ++
drivers/gpu/drm/i915/i915_drv.h | 17 +++++++++++++++++
drivers/gpu/drm/i915/i915_query.c | 5 +++--
4 files changed, 33 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
index a425db5ed3a2..e19df4ef47f6 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -168,6 +168,14 @@ static void init_unused_rings(struct intel_gt *gt)
}
}
+static void intel_gt_apply_ccs_mode(struct intel_gt *gt)
+{
+ if (!IS_DG2(gt->i915))
+ return;
+
+ intel_uncore_write(gt->uncore, XEHP_CCS_MODE, 0);
+}
+
int intel_gt_init_hw(struct intel_gt *gt)
{
struct drm_i915_private *i915 = gt->i915;
@@ -195,6 +203,9 @@ int intel_gt_init_hw(struct intel_gt *gt)
intel_gt_init_swizzling(gt);
+ /* Configure CCS mode */
+ intel_gt_apply_ccs_mode(gt);
+
/*
* At least 830 can leave some of the unused rings
* "active" (ie. head != tail) after resume which
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index cf709f6c05ae..c148113770ea 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -1605,6 +1605,8 @@
#define GEN12_VOLTAGE_MASK REG_GENMASK(10, 0)
#define GEN12_CAGF_MASK REG_GENMASK(19, 11)
+#define XEHP_CCS_MODE _MMIO(0x14804)
+
#define GEN11_GT_INTR_DW(x) _MMIO(0x190018 + ((x) * 4))
#define GEN11_CSME (31)
#define GEN12_HECI_2 (30)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index e81b3b2858ac..0853ffd3cb8d 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -396,6 +396,23 @@ static inline struct intel_gt *to_gt(const struct drm_i915_private *i915)
(engine__); \
(engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node)))
+/*
+ * Exclude unavailable engines.
+ *
+ * Only the first CCS engine is utilized due to the disabling of CCS auto load
+ * balancing. As a result, all CCS engines operate collectively, functioning
+ * essentially as a single CCS engine, hence the count of active CCS engines is
+ * considered '1'.
+ * Currently, this applies to platforms with more than one CCS engine,
+ * specifically DG2.
+ */
+#define for_each_available_uabi_engine(engine__, i915__) \
+ for_each_uabi_engine(engine__, i915__) \
+ if ((IS_DG2(i915__)) && \
+ ((engine__)->uabi_class == I915_ENGINE_CLASS_COMPUTE) && \
+ ((engine__)->uabi_instance)) { } \
+ else
+
#define INTEL_INFO(i915) ((i915)->__info)
#define RUNTIME_INFO(i915) (&(i915)->__runtime)
#define DRIVER_CAPS(i915) (&(i915)->caps)
diff --git a/drivers/gpu/drm/i915/i915_query.c b/drivers/gpu/drm/i915/i915_query.c
index fa3e937ed3f5..2d41bda626a6 100644
--- a/drivers/gpu/drm/i915/i915_query.c
+++ b/drivers/gpu/drm/i915/i915_query.c
@@ -124,6 +124,7 @@ static int query_geometry_subslices(struct drm_i915_private *i915,
return fill_topology_info(sseu, query_item, sseu->geometry_subslice_mask);
}
+
static int
query_engine_info(struct drm_i915_private *i915,
struct drm_i915_query_item *query_item)
@@ -140,7 +141,7 @@ query_engine_info(struct drm_i915_private *i915,
if (query_item->flags)
return -EINVAL;
- for_each_uabi_engine(engine, i915)
+ for_each_available_uabi_engine(engine, i915)
num_uabi_engines++;
len = struct_size(query_ptr, engines, num_uabi_engines);
@@ -155,7 +156,7 @@ query_engine_info(struct drm_i915_private *i915,
info_ptr = &query_ptr->engines[0];
- for_each_uabi_engine(engine, i915) {
+ for_each_available_uabi_engine(engine, i915) {
info.engine.engine_class = engine->uabi_class;
info.engine.engine_instance = engine->uabi_instance;
info.flags = I915_ENGINE_INFO_HAS_LOGICAL_INSTANCE;
--
2.43.0
^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCH 0/2] Disable automatic load CCS load balancing
2024-02-20 14:20 [PATCH 0/2] Disable automatic load CCS load balancing Andi Shyti
2024-02-20 14:20 ` [PATCH 1/2] drm/i915/gt: Disable HW load balancing for CCS Andi Shyti
2024-02-20 14:20 ` [PATCH 2/2] drm/i915/gt: Set default CCS mode '1' Andi Shyti
@ 2024-02-20 14:23 ` Andi Shyti
2024-02-20 14:34 ` Andi Shyti
3 siblings, 0 replies; 13+ messages in thread
From: Andi Shyti @ 2024-02-20 14:23 UTC (permalink / raw
To: Andi Shyti
Cc: intel-gfx, dri-devel, Chris Wilson, Joonas Lahtinen, Matt Roper,
John Harrison, Tvrtko Ursulin, stable, Andi Shyti
Hi,
I'm sorry, I forgot to add the changelog. Here it is:
v1 -> v2
========
- In Patch 1 use the correct workaround number (thanks Matt).
- In Patch 2 do not add the extra CCS engines to the exposed UABI
engine list and adapt the engine counting accordingly (thanks
Tvrtko).
- Reword the commit of Patch 2 (thanks John).
On Tue, Feb 20, 2024 at 03:20:32PM +0100, Andi Shyti wrote:
> Hi,
>
> this series does basically two things:
>
> 1. Disables automatic load balancing as adviced by the hardware
> workaround.
>
> 2. Forces the sharing of the load submitted to CCS among all the
> CCS available (as of now only DG2 has more than one CCS). This
> way the user, when sending a query, will see only one CCS
> available.
>
> Andi
>
> Andi Shyti (2):
> drm/i915/gt: Disable HW load balancing for CCS
> drm/i915/gt: Set default CCS mode '1'
>
> drivers/gpu/drm/i915/gt/intel_gt.c | 11 +++++++++++
> drivers/gpu/drm/i915/gt/intel_gt_regs.h | 3 +++
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 ++++++
> drivers/gpu/drm/i915/i915_drv.h | 17 +++++++++++++++++
> drivers/gpu/drm/i915/i915_query.c | 5 +++--
> 5 files changed, 40 insertions(+), 2 deletions(-)
>
> --
> 2.43.0
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 2/2] drm/i915/gt: Set default CCS mode '1'
2024-02-20 14:20 ` [PATCH 2/2] drm/i915/gt: Set default CCS mode '1' Andi Shyti
@ 2024-02-20 14:27 ` Tvrtko Ursulin
2024-02-20 14:33 ` Andi Shyti
2024-02-27 12:18 ` Jani Nikula
1 sibling, 1 reply; 13+ messages in thread
From: Tvrtko Ursulin @ 2024-02-20 14:27 UTC (permalink / raw
To: Andi Shyti, intel-gfx, dri-devel
Cc: Chris Wilson, Joonas Lahtinen, Matt Roper, John Harrison, stable,
Andi Shyti
On 20/02/2024 14:20, Andi Shyti wrote:
> Since CCS automatic load balancing is disabled, we will impose a
> fixed balancing policy that involves setting all the CCS engines
> to work together on the same load.
Erm *all* CSS engines work together..
> Simultaneously, the user will see only 1 CCS rather than the
> actual number. As of now, this change affects only DG2.
... *one* CCS engine.
>
> Fixes: d2eae8e98d59 ("drm/i915/dg2: Drop force_probe requirement")
> Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
> Cc: Chris Wilson <chris.p.wilson@linux.intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: <stable@vger.kernel.org> # v6.2+
> ---
> drivers/gpu/drm/i915/gt/intel_gt.c | 11 +++++++++++
> drivers/gpu/drm/i915/gt/intel_gt_regs.h | 2 ++
> drivers/gpu/drm/i915/i915_drv.h | 17 +++++++++++++++++
> drivers/gpu/drm/i915/i915_query.c | 5 +++--
> 4 files changed, 33 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
> index a425db5ed3a2..e19df4ef47f6 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
> @@ -168,6 +168,14 @@ static void init_unused_rings(struct intel_gt *gt)
> }
> }
>
> +static void intel_gt_apply_ccs_mode(struct intel_gt *gt)
> +{
> + if (!IS_DG2(gt->i915))
> + return;
> +
> + intel_uncore_write(gt->uncore, XEHP_CCS_MODE, 0);
> +}
> +
> int intel_gt_init_hw(struct intel_gt *gt)
> {
> struct drm_i915_private *i915 = gt->i915;
> @@ -195,6 +203,9 @@ int intel_gt_init_hw(struct intel_gt *gt)
>
> intel_gt_init_swizzling(gt);
>
> + /* Configure CCS mode */
> + intel_gt_apply_ccs_mode(gt);
> +
> /*
> * At least 830 can leave some of the unused rings
> * "active" (ie. head != tail) after resume which
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> index cf709f6c05ae..c148113770ea 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> @@ -1605,6 +1605,8 @@
> #define GEN12_VOLTAGE_MASK REG_GENMASK(10, 0)
> #define GEN12_CAGF_MASK REG_GENMASK(19, 11)
>
> +#define XEHP_CCS_MODE _MMIO(0x14804)
> +
> #define GEN11_GT_INTR_DW(x) _MMIO(0x190018 + ((x) * 4))
> #define GEN11_CSME (31)
> #define GEN12_HECI_2 (30)
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index e81b3b2858ac..0853ffd3cb8d 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -396,6 +396,23 @@ static inline struct intel_gt *to_gt(const struct drm_i915_private *i915)
> (engine__); \
> (engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node)))
>
> +/*
> + * Exclude unavailable engines.
> + *
> + * Only the first CCS engine is utilized due to the disabling of CCS auto load
> + * balancing. As a result, all CCS engines operate collectively, functioning
> + * essentially as a single CCS engine, hence the count of active CCS engines is
> + * considered '1'.
> + * Currently, this applies to platforms with more than one CCS engine,
> + * specifically DG2.
> + */
> +#define for_each_available_uabi_engine(engine__, i915__) \
> + for_each_uabi_engine(engine__, i915__) \
> + if ((IS_DG2(i915__)) && \
> + ((engine__)->uabi_class == I915_ENGINE_CLASS_COMPUTE) && \
> + ((engine__)->uabi_instance)) { } \
> + else
> +
I thought the plan was to simply not register the engine. Like that it
would be a simpler patch.
> #define INTEL_INFO(i915) ((i915)->__info)
> #define RUNTIME_INFO(i915) (&(i915)->__runtime)
> #define DRIVER_CAPS(i915) (&(i915)->caps)
> diff --git a/drivers/gpu/drm/i915/i915_query.c b/drivers/gpu/drm/i915/i915_query.c
> index fa3e937ed3f5..2d41bda626a6 100644
> --- a/drivers/gpu/drm/i915/i915_query.c
> +++ b/drivers/gpu/drm/i915/i915_query.c
> @@ -124,6 +124,7 @@ static int query_geometry_subslices(struct drm_i915_private *i915,
> return fill_topology_info(sseu, query_item, sseu->geometry_subslice_mask);
> }
>
> +
!
> static int
> query_engine_info(struct drm_i915_private *i915,
> struct drm_i915_query_item *query_item)
> @@ -140,7 +141,7 @@ query_engine_info(struct drm_i915_private *i915,
> if (query_item->flags)
> return -EINVAL;
>
> - for_each_uabi_engine(engine, i915)
> + for_each_available_uabi_engine(engine, i915)
> num_uabi_engines++;
>
> len = struct_size(query_ptr, engines, num_uabi_engines);
> @@ -155,7 +156,7 @@ query_engine_info(struct drm_i915_private *i915,
>
> info_ptr = &query_ptr->engines[0];
>
> - for_each_uabi_engine(engine, i915) {
> + for_each_available_uabi_engine(engine, i915) {
> info.engine.engine_class = engine->uabi_class;
> info.engine.engine_instance = engine->uabi_instance;
> info.flags = I915_ENGINE_INFO_HAS_LOGICAL_INSTANCE;
I thought you agreed that this still misses to hide the engine on direct
lookup from userspace such as context map, PMU, SSEU. All of those would
automatically be handled by not registering the engine.
Regards,
Tvrtko
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 2/2] drm/i915/gt: Set default CCS mode '1'
2024-02-20 14:27 ` Tvrtko Ursulin
@ 2024-02-20 14:33 ` Andi Shyti
0 siblings, 0 replies; 13+ messages in thread
From: Andi Shyti @ 2024-02-20 14:33 UTC (permalink / raw
To: Tvrtko Ursulin
Cc: Andi Shyti, intel-gfx, dri-devel, Chris Wilson, Joonas Lahtinen,
Matt Roper, John Harrison, stable, Andi Shyti
On Tue, Feb 20, 2024 at 02:27:07PM +0000, Tvrtko Ursulin wrote:
>
> On 20/02/2024 14:20, Andi Shyti wrote:
> > Since CCS automatic load balancing is disabled, we will impose a
> > fixed balancing policy that involves setting all the CCS engines
> > to work together on the same load.
>
> Erm *all* CSS engines work together..
>
> > Simultaneously, the user will see only 1 CCS rather than the
> > actual number. As of now, this change affects only DG2.
>
> ... *one* CCS engine.
ops... I sent V1 again!
Sorry, I will send v2 now
Thanks!
Andi
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 0/2] Disable automatic load CCS load balancing
2024-02-20 14:20 [PATCH 0/2] Disable automatic load CCS load balancing Andi Shyti
` (2 preceding siblings ...)
2024-02-20 14:23 ` [PATCH 0/2] Disable automatic load CCS load balancing Andi Shyti
@ 2024-02-20 14:34 ` Andi Shyti
3 siblings, 0 replies; 13+ messages in thread
From: Andi Shyti @ 2024-02-20 14:34 UTC (permalink / raw
To: Andi Shyti
Cc: intel-gfx, dri-devel, Chris Wilson, Joonas Lahtinen, Matt Roper,
John Harrison, Tvrtko Ursulin, stable, Andi Shyti
Please, ignore, I sent V1 again.
Sorry about the noise!
Andi
On Tue, Feb 20, 2024 at 03:20:32PM +0100, Andi Shyti wrote:
> Hi,
>
> this series does basically two things:
>
> 1. Disables automatic load balancing as adviced by the hardware
> workaround.
>
> 2. Forces the sharing of the load submitted to CCS among all the
> CCS available (as of now only DG2 has more than one CCS). This
> way the user, when sending a query, will see only one CCS
> available.
>
> Andi
>
> Andi Shyti (2):
> drm/i915/gt: Disable HW load balancing for CCS
> drm/i915/gt: Set default CCS mode '1'
>
> drivers/gpu/drm/i915/gt/intel_gt.c | 11 +++++++++++
> drivers/gpu/drm/i915/gt/intel_gt_regs.h | 3 +++
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 ++++++
> drivers/gpu/drm/i915/i915_drv.h | 17 +++++++++++++++++
> drivers/gpu/drm/i915/i915_query.c | 5 +++--
> 5 files changed, 40 insertions(+), 2 deletions(-)
>
> --
> 2.43.0
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 2/2] drm/i915/gt: Set default CCS mode '1'
2024-02-20 14:20 ` [PATCH 2/2] drm/i915/gt: Set default CCS mode '1' Andi Shyti
2024-02-20 14:27 ` Tvrtko Ursulin
@ 2024-02-27 12:18 ` Jani Nikula
2024-02-27 13:01 ` Andi Shyti
1 sibling, 1 reply; 13+ messages in thread
From: Jani Nikula @ 2024-02-27 12:18 UTC (permalink / raw
To: Andi Shyti, intel-gfx, dri-devel
Cc: Chris Wilson, Joonas Lahtinen, Matt Roper, John Harrison,
Tvrtko Ursulin, stable, Andi Shyti, Andi Shyti
On Tue, 20 Feb 2024, Andi Shyti <andi.shyti@linux.intel.com> wrote:
> Since CCS automatic load balancing is disabled, we will impose a
> fixed balancing policy that involves setting all the CCS engines
> to work together on the same load.
>
> Simultaneously, the user will see only 1 CCS rather than the
> actual number. As of now, this change affects only DG2.
>
> Fixes: d2eae8e98d59 ("drm/i915/dg2: Drop force_probe requirement")
> Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
> Cc: Chris Wilson <chris.p.wilson@linux.intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: <stable@vger.kernel.org> # v6.2+
> ---
> drivers/gpu/drm/i915/gt/intel_gt.c | 11 +++++++++++
> drivers/gpu/drm/i915/gt/intel_gt_regs.h | 2 ++
> drivers/gpu/drm/i915/i915_drv.h | 17 +++++++++++++++++
> drivers/gpu/drm/i915/i915_query.c | 5 +++--
> 4 files changed, 33 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
> index a425db5ed3a2..e19df4ef47f6 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
> @@ -168,6 +168,14 @@ static void init_unused_rings(struct intel_gt *gt)
> }
> }
>
> +static void intel_gt_apply_ccs_mode(struct intel_gt *gt)
> +{
> + if (!IS_DG2(gt->i915))
> + return;
> +
> + intel_uncore_write(gt->uncore, XEHP_CCS_MODE, 0);
> +}
> +
> int intel_gt_init_hw(struct intel_gt *gt)
> {
> struct drm_i915_private *i915 = gt->i915;
> @@ -195,6 +203,9 @@ int intel_gt_init_hw(struct intel_gt *gt)
>
> intel_gt_init_swizzling(gt);
>
> + /* Configure CCS mode */
> + intel_gt_apply_ccs_mode(gt);
> +
> /*
> * At least 830 can leave some of the unused rings
> * "active" (ie. head != tail) after resume which
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> index cf709f6c05ae..c148113770ea 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> @@ -1605,6 +1605,8 @@
> #define GEN12_VOLTAGE_MASK REG_GENMASK(10, 0)
> #define GEN12_CAGF_MASK REG_GENMASK(19, 11)
>
> +#define XEHP_CCS_MODE _MMIO(0x14804)
> +
> #define GEN11_GT_INTR_DW(x) _MMIO(0x190018 + ((x) * 4))
> #define GEN11_CSME (31)
> #define GEN12_HECI_2 (30)
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index e81b3b2858ac..0853ffd3cb8d 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -396,6 +396,23 @@ static inline struct intel_gt *to_gt(const struct drm_i915_private *i915)
> (engine__); \
> (engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node)))
>
> +/*
> + * Exclude unavailable engines.
> + *
> + * Only the first CCS engine is utilized due to the disabling of CCS auto load
> + * balancing. As a result, all CCS engines operate collectively, functioning
> + * essentially as a single CCS engine, hence the count of active CCS engines is
> + * considered '1'.
> + * Currently, this applies to platforms with more than one CCS engine,
> + * specifically DG2.
> + */
> +#define for_each_available_uabi_engine(engine__, i915__) \
Hrmh, I've been trying to pester folks to move the existing engine
iterator macros away from i915_drv.h, so not happy to see more.
But since this is Cc: stable, better do that in a follow-up. Please?
> + for_each_uabi_engine(engine__, i915__) \
> + if ((IS_DG2(i915__)) && \
> + ((engine__)->uabi_class == I915_ENGINE_CLASS_COMPUTE) && \
> + ((engine__)->uabi_instance)) { } \
> + else
We have for_each_if for this.
> +
> #define INTEL_INFO(i915) ((i915)->__info)
> #define RUNTIME_INFO(i915) (&(i915)->__runtime)
> #define DRIVER_CAPS(i915) (&(i915)->caps)
> diff --git a/drivers/gpu/drm/i915/i915_query.c b/drivers/gpu/drm/i915/i915_query.c
> index fa3e937ed3f5..2d41bda626a6 100644
> --- a/drivers/gpu/drm/i915/i915_query.c
> +++ b/drivers/gpu/drm/i915/i915_query.c
> @@ -124,6 +124,7 @@ static int query_geometry_subslices(struct drm_i915_private *i915,
> return fill_topology_info(sseu, query_item, sseu->geometry_subslice_mask);
> }
>
> +
Superfluous newline change.
> static int
> query_engine_info(struct drm_i915_private *i915,
> struct drm_i915_query_item *query_item)
> @@ -140,7 +141,7 @@ query_engine_info(struct drm_i915_private *i915,
> if (query_item->flags)
> return -EINVAL;
>
> - for_each_uabi_engine(engine, i915)
> + for_each_available_uabi_engine(engine, i915)
> num_uabi_engines++;
>
> len = struct_size(query_ptr, engines, num_uabi_engines);
> @@ -155,7 +156,7 @@ query_engine_info(struct drm_i915_private *i915,
>
> info_ptr = &query_ptr->engines[0];
>
> - for_each_uabi_engine(engine, i915) {
> + for_each_available_uabi_engine(engine, i915) {
> info.engine.engine_class = engine->uabi_class;
> info.engine.engine_instance = engine->uabi_instance;
> info.flags = I915_ENGINE_INFO_HAS_LOGICAL_INSTANCE;
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 2/2] drm/i915/gt: Set default CCS mode '1'
2024-02-27 12:18 ` Jani Nikula
@ 2024-02-27 13:01 ` Andi Shyti
0 siblings, 0 replies; 13+ messages in thread
From: Andi Shyti @ 2024-02-27 13:01 UTC (permalink / raw
To: Jani Nikula
Cc: Andi Shyti, intel-gfx, dri-devel, Chris Wilson, Joonas Lahtinen,
Matt Roper, John Harrison, Tvrtko Ursulin, stable, Andi Shyti
Hi Jani,
thanks, there has been a v2 after this and your comments have
been addressed somehow.
There will be a v3, as well.
Thanks,
Andi
On Tue, Feb 27, 2024 at 02:18:01PM +0200, Jani Nikula wrote:
> On Tue, 20 Feb 2024, Andi Shyti <andi.shyti@linux.intel.com> wrote:
> > Since CCS automatic load balancing is disabled, we will impose a
> > fixed balancing policy that involves setting all the CCS engines
> > to work together on the same load.
> >
> > Simultaneously, the user will see only 1 CCS rather than the
> > actual number. As of now, this change affects only DG2.
> >
> > Fixes: d2eae8e98d59 ("drm/i915/dg2: Drop force_probe requirement")
> > Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
> > Cc: Chris Wilson <chris.p.wilson@linux.intel.com>
> > Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> > Cc: Matt Roper <matthew.d.roper@intel.com>
> > Cc: <stable@vger.kernel.org> # v6.2+
> > ---
> > drivers/gpu/drm/i915/gt/intel_gt.c | 11 +++++++++++
> > drivers/gpu/drm/i915/gt/intel_gt_regs.h | 2 ++
> > drivers/gpu/drm/i915/i915_drv.h | 17 +++++++++++++++++
> > drivers/gpu/drm/i915/i915_query.c | 5 +++--
> > 4 files changed, 33 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
> > index a425db5ed3a2..e19df4ef47f6 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_gt.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
> > @@ -168,6 +168,14 @@ static void init_unused_rings(struct intel_gt *gt)
> > }
> > }
> >
> > +static void intel_gt_apply_ccs_mode(struct intel_gt *gt)
> > +{
> > + if (!IS_DG2(gt->i915))
> > + return;
> > +
> > + intel_uncore_write(gt->uncore, XEHP_CCS_MODE, 0);
> > +}
> > +
> > int intel_gt_init_hw(struct intel_gt *gt)
> > {
> > struct drm_i915_private *i915 = gt->i915;
> > @@ -195,6 +203,9 @@ int intel_gt_init_hw(struct intel_gt *gt)
> >
> > intel_gt_init_swizzling(gt);
> >
> > + /* Configure CCS mode */
> > + intel_gt_apply_ccs_mode(gt);
> > +
> > /*
> > * At least 830 can leave some of the unused rings
> > * "active" (ie. head != tail) after resume which
> > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> > index cf709f6c05ae..c148113770ea 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> > +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> > @@ -1605,6 +1605,8 @@
> > #define GEN12_VOLTAGE_MASK REG_GENMASK(10, 0)
> > #define GEN12_CAGF_MASK REG_GENMASK(19, 11)
> >
> > +#define XEHP_CCS_MODE _MMIO(0x14804)
> > +
> > #define GEN11_GT_INTR_DW(x) _MMIO(0x190018 + ((x) * 4))
> > #define GEN11_CSME (31)
> > #define GEN12_HECI_2 (30)
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > index e81b3b2858ac..0853ffd3cb8d 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -396,6 +396,23 @@ static inline struct intel_gt *to_gt(const struct drm_i915_private *i915)
> > (engine__); \
> > (engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node)))
> >
> > +/*
> > + * Exclude unavailable engines.
> > + *
> > + * Only the first CCS engine is utilized due to the disabling of CCS auto load
> > + * balancing. As a result, all CCS engines operate collectively, functioning
> > + * essentially as a single CCS engine, hence the count of active CCS engines is
> > + * considered '1'.
> > + * Currently, this applies to platforms with more than one CCS engine,
> > + * specifically DG2.
> > + */
> > +#define for_each_available_uabi_engine(engine__, i915__) \
>
> Hrmh, I've been trying to pester folks to move the existing engine
> iterator macros away from i915_drv.h, so not happy to see more.
>
> But since this is Cc: stable, better do that in a follow-up. Please?
>
> > + for_each_uabi_engine(engine__, i915__) \
> > + if ((IS_DG2(i915__)) && \
> > + ((engine__)->uabi_class == I915_ENGINE_CLASS_COMPUTE) && \
> > + ((engine__)->uabi_instance)) { } \
> > + else
>
> We have for_each_if for this.
>
> > +
> > #define INTEL_INFO(i915) ((i915)->__info)
> > #define RUNTIME_INFO(i915) (&(i915)->__runtime)
> > #define DRIVER_CAPS(i915) (&(i915)->caps)
> > diff --git a/drivers/gpu/drm/i915/i915_query.c b/drivers/gpu/drm/i915/i915_query.c
> > index fa3e937ed3f5..2d41bda626a6 100644
> > --- a/drivers/gpu/drm/i915/i915_query.c
> > +++ b/drivers/gpu/drm/i915/i915_query.c
> > @@ -124,6 +124,7 @@ static int query_geometry_subslices(struct drm_i915_private *i915,
> > return fill_topology_info(sseu, query_item, sseu->geometry_subslice_mask);
> > }
> >
> > +
>
> Superfluous newline change.
>
> > static int
> > query_engine_info(struct drm_i915_private *i915,
> > struct drm_i915_query_item *query_item)
> > @@ -140,7 +141,7 @@ query_engine_info(struct drm_i915_private *i915,
> > if (query_item->flags)
> > return -EINVAL;
> >
> > - for_each_uabi_engine(engine, i915)
> > + for_each_available_uabi_engine(engine, i915)
> > num_uabi_engines++;
> >
> > len = struct_size(query_ptr, engines, num_uabi_engines);
> > @@ -155,7 +156,7 @@ query_engine_info(struct drm_i915_private *i915,
> >
> > info_ptr = &query_ptr->engines[0];
> >
> > - for_each_uabi_engine(engine, i915) {
> > + for_each_available_uabi_engine(engine, i915) {
> > info.engine.engine_class = engine->uabi_class;
> > info.engine.engine_instance = engine->uabi_instance;
> > info.flags = I915_ENGINE_INFO_HAS_LOGICAL_INSTANCE;
>
> --
> Jani Nikula, Intel
^ permalink raw reply [flat|nested] 13+ messages in thread
end of thread, other threads:[~2024-02-27 13:02 UTC | newest]
Thread overview: 13+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2024-02-20 14:20 [PATCH 0/2] Disable automatic load CCS load balancing Andi Shyti
2024-02-20 14:20 ` [PATCH 1/2] drm/i915/gt: Disable HW load balancing for CCS Andi Shyti
2024-02-20 14:20 ` [PATCH 2/2] drm/i915/gt: Set default CCS mode '1' Andi Shyti
2024-02-20 14:27 ` Tvrtko Ursulin
2024-02-20 14:33 ` Andi Shyti
2024-02-27 12:18 ` Jani Nikula
2024-02-27 13:01 ` Andi Shyti
2024-02-20 14:23 ` [PATCH 0/2] Disable automatic load CCS load balancing Andi Shyti
2024-02-20 14:34 ` Andi Shyti
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2024-02-15 13:59 Andi Shyti
2024-02-15 13:59 ` [PATCH 1/2] drm/i915/gt: Disable HW load balancing for CCS Andi Shyti
2024-02-15 16:55 ` Matt Roper
2024-02-19 10:17 ` Andi Shyti
2024-02-19 10:31 ` Andi Shyti
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