From: Sasha Levin <sashal@kernel.org>
To: linux-kernel@vger.kernel.org, stable@vger.kernel.org
Cc: Sung Joon Kim <sungjoon.kim@amd.com>,
Anthony Koo <anthony.koo@amd.com>, Wayne Lin <wayne.lin@amd.com>,
Daniel Wheeler <daniel.wheeler@amd.com>,
Alex Deucher <alexander.deucher@amd.com>,
Sasha Levin <sashal@kernel.org>,
harry.wentland@amd.com, sunpeng.li@amd.com,
Rodrigo.Siqueira@amd.com, christian.koenig@amd.com,
Xinhui.Pan@amd.com, airlied@gmail.com, daniel@ffwll.ch,
alvin.lee2@amd.com, jun.lei@amd.com, wenjing.liu@amd.com,
aric.cyr@amd.com, dillon.varone@amd.com, chiawen.huang@amd.com,
amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org
Subject: [PATCH AUTOSEL 6.6 34/43] drm/amd/display: Disable seamless boot on 128b/132b encoding
Date: Tue, 7 May 2024 19:09:55 -0400 [thread overview]
Message-ID: <20240507231033.393285-34-sashal@kernel.org> (raw)
In-Reply-To: <20240507231033.393285-1-sashal@kernel.org>
From: Sung Joon Kim <sungjoon.kim@amd.com>
[ Upstream commit 6f0c228ed9184287031a66b46a79e5a3d2e73a86 ]
[why]
preOS will not support display mode programming and link training
for UHBR rates.
[how]
If we detect a sink that's UHBR capable, disable seamless boot
Reviewed-by: Anthony Koo <anthony.koo@amd.com>
Acked-by: Wayne Lin <wayne.lin@amd.com>
Signed-off-by: Sung Joon Kim <sungjoon.kim@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 46b10ff8f6d41..72db370e2f21f 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1710,6 +1710,9 @@ bool dc_validate_boot_timing(const struct dc *dc,
return false;
}
+ if (link->dpcd_caps.channel_coding_cap.bits.DP_128b_132b_SUPPORTED)
+ return false;
+
if (dc->link_srv->edp_is_ilr_optimization_required(link, crtc_timing)) {
DC_LOG_EVENT_LINK_TRAINING("Seamless boot disabled to optimize eDP link rate\n");
return false;
--
2.43.0
next prev parent reply other threads:[~2024-05-07 23:11 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20240507231033.393285-1-sashal@kernel.org>
2024-05-07 23:09 ` [PATCH AUTOSEL 6.6 28/43] drm/amdgpu: Fix VRAM memory accounting Sasha Levin
2024-05-07 23:09 ` [PATCH AUTOSEL 6.6 29/43] drm/amd/display: Add dtbclk access to dcn315 Sasha Levin
2024-05-07 23:09 ` [PATCH AUTOSEL 6.6 30/43] drm/amd/display: Atom Integrated System Info v2_2 for DCN35 Sasha Levin
2024-05-07 23:09 ` [PATCH AUTOSEL 6.6 31/43] drm/amd/display: Allocate zero bw after bw alloc enable Sasha Levin
2024-05-07 23:09 ` [PATCH AUTOSEL 6.6 32/43] drm/amd/display: Add VCO speed parameter for DCN31 FPU Sasha Levin
2024-05-07 23:09 ` [PATCH AUTOSEL 6.6 33/43] drm/amd/display: Fix DC mode screen flickering on DCN321 Sasha Levin
2024-05-07 23:09 ` Sasha Levin [this message]
2024-05-07 23:09 ` [PATCH AUTOSEL 6.6 35/43] drm/amdkfd: Flush the process wq before creating a kfd_process Sasha Levin
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