From: Animesh Manna <animesh.manna@intel.com>
To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org
Cc: uma.shankar@intel.com, dibin.moolakadan.subrahmanian@intel.com,
jani.nikula@intel.com, Animesh Manna <animesh.manna@intel.com>
Subject: [PATCH v4 09/13] drm/i915/cmtg: Modify existing hook to disable CMTG
Date: Sun, 12 Apr 2026 16:07:08 +0530 [thread overview]
Message-ID: <20260412103712.4021213-10-animesh.manna@intel.com> (raw)
In-Reply-To: <20260412103712.4021213-1-animesh.manna@intel.com>
From: Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>
Earlier cmtg_disable() used to disable all instances of CMTG
which cannot handle individual request for specific CMTG instance.
Introduce cmtg_disable_all() which will disable all cmtg instances
and cmtg_disable() only disable specific instance.
v2:
- Use intel_de_rmw to simplify. [Uma]
Signed-off-by: Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
drivers/gpu/drm/i915/display/intel_cmtg.c | 30 +++++++++++++++++--
drivers/gpu/drm/i915/display/intel_cmtg.h | 1 +
.../gpu/drm/i915/display/intel_cmtg_regs.h | 1 +
3 files changed, 29 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c b/drivers/gpu/drm/i915/display/intel_cmtg.c
index c043fb4f9789..00e5bdd1b063 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.c
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
@@ -137,8 +137,8 @@ static bool intel_cmtg_disable_requires_modeset(struct intel_display *display,
return cmtg_config->trans_a_secondary || cmtg_config->trans_b_secondary;
}
-static void intel_cmtg_disable(struct intel_display *display,
- struct intel_cmtg_config *cmtg_config)
+static void intel_cmtg_disable_all(struct intel_display *display,
+ struct intel_cmtg_config *cmtg_config)
{
u32 clk_sel_clr = 0;
u32 clk_sel_set = 0;
@@ -169,6 +169,30 @@ static void intel_cmtg_disable(struct intel_display *display,
intel_de_rmw(display, CMTG_CLK_SEL, clk_sel_clr, clk_sel_set);
}
+void intel_cmtg_disable(const struct intel_crtc_state *crtc_state)
+{
+ struct intel_display *display = to_intel_display(crtc_state);
+ enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+
+ if (!intel_cmtg_is_supported(crtc_state))
+ return;
+
+ intel_de_rmw(display, TRANS_VRR_CTL_CMTG(cpu_transcoder),
+ VRR_CTL_VRR_ENABLE | VRR_CTL_FLIP_LINE_EN, 0);
+
+ intel_de_rmw(display, TRANS_DDI_FUNC_CTL2(display, cpu_transcoder),
+ PORT_SYNC_MODE_ENABLE, 0);
+
+ intel_de_rmw(display, TRANS_CMTG_CTL(cpu_transcoder), CMTG_ENABLE, 0);
+
+ if (intel_de_wait_for_clear_ms(display, TRANS_CMTG_CTL(cpu_transcoder), CMTG_STATE, 50)) {
+ drm_WARN(display->drm, 1, "CMTG: %s disable timeout\n",
+ transcoder_name(cpu_transcoder));
+ return;
+ }
+
+ drm_dbg_kms(display->drm, "CMTG: %s disabled\n", transcoder_name(cpu_transcoder));
+}
/*
* Read out CMTG configuration and, on platforms that allow disabling it without
* a modeset, do it.
@@ -196,7 +220,7 @@ void intel_cmtg_sanitize(struct intel_display *display)
if (intel_cmtg_disable_requires_modeset(display, &cmtg_config))
return;
- intel_cmtg_disable(display, &cmtg_config);
+ intel_cmtg_disable_all(display, &cmtg_config);
}
bool intel_cmtg_is_allowed(const struct intel_crtc_state *crtc_state)
diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.h b/drivers/gpu/drm/i915/display/intel_cmtg.h
index 12abbafa7d08..79785afccc51 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.h
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.h
@@ -11,6 +11,7 @@
struct intel_display;
struct intel_crtc_state;
+void intel_cmtg_disable(const struct intel_crtc_state *crtc_state);
void intel_cmtg_enable_ddi(const struct intel_crtc_state *crtc_state);
void intel_cmtg_enable_sync(const struct intel_crtc_state *crtc_state);
void intel_cmtg_set_m_n(const struct intel_crtc_state *crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
index d447a72bd9fa..d2f83829b8a7 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
@@ -22,6 +22,7 @@
_TRANS_CMTG_CTL_A, _TRANS_CMTG_CTL_B)
#define CMTG_ENABLE REG_BIT(31)
#define CMTG_SYNC_TO_PORT REG_BIT(29)
+#define CMTG_STATE REG_BIT(23)
#define _TRANS_HTOTAL_CMTG_A 0x6F000
#define _TRANS_HTOTAL_CMTG_B 0x6F100
--
2.29.0
next prev parent reply other threads:[~2026-04-12 11:08 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-04-12 10:36 [PATCH v4 00/13] CMTG enablement Animesh Manna
2026-04-12 10:37 ` [PATCH v4 01/13] drm/i915/cmtg: Add intel_cmtg_is_allowed() for CMTG Animesh Manna
2026-04-14 13:31 ` Jani Nikula
2026-04-12 10:37 ` [PATCH v4 02/13] drm/i915/cmtg: Set CMTG clock select Animesh Manna
2026-04-12 10:37 ` [PATCH v4 03/13] drm/i915/cmtg: Set timings for CMTG Animesh Manna
2026-04-14 13:33 ` Jani Nikula
2026-04-17 6:03 ` Manna, Animesh
2026-04-17 10:26 ` Ville Syrjälä
2026-04-23 4:37 ` Manna, Animesh
2026-04-23 4:55 ` Manna, Animesh
2026-04-23 10:51 ` Ville Syrjälä
2026-04-23 11:07 ` Manna, Animesh
2026-04-29 12:01 ` Ville Syrjälä
2026-04-30 7:16 ` Manna, Animesh
2026-04-12 10:37 ` [PATCH v4 04/13] drm/i915/cmtg: Program VRR registers of CMTG Animesh Manna
2026-04-12 10:37 ` [PATCH v4 05/13] drm/i915/cmtg: Set transcoder mn for CMTG Animesh Manna
2026-04-12 10:37 ` [PATCH v4 06/13] drm/i915/cmtg: Add hook to enable CMTG with sync to port Animesh Manna
2026-04-12 10:37 ` [PATCH v4 07/13] drm/i915/cmtg: Add a hook to make eDP transcoder secondary Animesh Manna
2026-04-12 10:37 ` [PATCH v4 08/13] drm/i915/cmtg: Split CMTG support check from intel_cmtg_is_allowed() Animesh Manna
2026-04-12 10:37 ` Animesh Manna [this message]
2026-04-12 10:37 ` [PATCH v4 10/13] drm/i915/cmtg: Add trigger to enable/disable cmtg Animesh Manna
2026-04-12 10:37 ` [PATCH v4 11/13] drm/i915/cmtg: Add CMTG interrupt handling Animesh Manna
2026-04-12 10:37 ` [PATCH v4 12/13] drm/i915/cmtg: Disable CMTG if dc3co is not allowed Animesh Manna
2026-04-12 10:37 ` [PATCH v4 13/13] drm/i915/cmtg: Set target_dc_state flag for lobf/psr2/pr-alpm Animesh Manna
2026-04-13 12:19 ` Dibin Moolakadan Subrahmanian
2026-04-12 11:16 ` ✓ CI.KUnit: success for CMTG enablement (rev5) Patchwork
2026-04-12 12:05 ` ✓ Xe.CI.BAT: " Patchwork
2026-04-12 13:01 ` ✗ Xe.CI.FULL: failure " Patchwork
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