From: Animesh Manna <animesh.manna@intel.com>
To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org
Cc: uma.shankar@intel.com, dibin.moolakadan.subrahmanian@intel.com,
jani.nikula@intel.com, Animesh Manna <animesh.manna@intel.com>
Subject: [PATCH v4 04/13] drm/i915/cmtg: Program VRR registers of CMTG
Date: Sun, 12 Apr 2026 16:07:03 +0530 [thread overview]
Message-ID: <20260412103712.4021213-5-animesh.manna@intel.com> (raw)
In-Reply-To: <20260412103712.4021213-1-animesh.manna@intel.com>
Program the VRR registers of CMTG, as the VRR timing generator
will always be enabled for NVL.
v2: Use sw state instead of reading from hardware. [Jani]
v3: Program cmtg vrr control and timing registers along with
vrr transcoder registers.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
drivers/gpu/drm/i915/display/intel_cmtg.c | 33 +++++++++++++++++++
drivers/gpu/drm/i915/display/intel_cmtg.h | 2 ++
.../gpu/drm/i915/display/intel_cmtg_regs.h | 20 +++++++++++
drivers/gpu/drm/i915/display/intel_vrr.c | 5 +++
4 files changed, 60 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c b/drivers/gpu/drm/i915/display/intel_cmtg.c
index a3db1368bd83..c5ef9de2e408 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.c
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
@@ -16,6 +16,7 @@
#include "intel_display_power.h"
#include "intel_display_regs.h"
#include "intel_display_types.h"
+#include "intel_vrr_regs.h"
/**
* DOC: Common Primary Timing Generator (CMTG)
@@ -281,3 +282,35 @@ void intel_cmtg_set_timings(const struct intel_crtc_state *crtc_state, bool lrr)
intel_de_write(display, TRANS_SET_CTX_LATENCY_CMTG(cpu_transcoder),
crtc_state->set_context_latency);
}
+
+void intel_cmtg_set_vrr_timings(const struct intel_crtc_state *crtc_state)
+{
+ struct intel_display *display = to_intel_display(crtc_state);
+ enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+
+ if (!intel_cmtg_is_allowed(crtc_state))
+ return;
+
+ intel_de_write(display, TRANS_VRR_VMIN_CMTG(cpu_transcoder), crtc_state->vrr.vmin);
+ intel_de_write(display, TRANS_VRR_VMAX_CMTG(cpu_transcoder), crtc_state->vrr.vmax);
+ intel_de_write(display, TRANS_VRR_FLIPLINE_CMTG(cpu_transcoder), crtc_state->vrr.flipline);
+}
+
+void intel_cmtg_set_vrr_ctl(const struct intel_crtc_state *crtc_state)
+{
+ struct intel_display *display = to_intel_display(crtc_state);
+ enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+ u32 vrr_ctl;
+
+ if (!intel_cmtg_is_allowed(crtc_state))
+ return;
+
+ vrr_ctl = VRR_CTL_VRR_ENABLE | VRR_CTL_FLIP_LINE_EN |
+ XELPD_VRR_CTL_VRR_GUARDBAND(crtc_state->vrr.guardband);
+
+ /* TODO: The code below may need to be revisited once CMRR is enabled */
+ if (crtc_state->cmrr.enable)
+ vrr_ctl |= VRR_CTL_CMRR_ENABLE;
+
+ intel_de_write(display, TRANS_VRR_CTL_CMTG(cpu_transcoder), vrr_ctl);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.h b/drivers/gpu/drm/i915/display/intel_cmtg.h
index 53a44f505dd2..c92e3a62ff0d 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.h
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.h
@@ -11,6 +11,8 @@
struct intel_display;
struct intel_crtc_state;
+void intel_cmtg_set_vrr_timings(const struct intel_crtc_state *crtc_state);
+void intel_cmtg_set_vrr_ctl(const struct intel_crtc_state *crtc_state);
void intel_cmtg_set_timings(const struct intel_crtc_state *crtc_state, bool lrr);
void intel_cmtg_set_clk_select(const struct intel_crtc_state *crtc_state);
void intel_cmtg_sanitize(struct intel_display *display);
diff --git a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
index f7fc812d8ef0..b50ada371262 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
@@ -51,4 +51,24 @@
_TRANS_SET_CTX_LATENCY_CMTG_A, \
_TRANS_SET_CTX_LATENCY_CMTG_B)
+#define _TRANS_VRR_CTL_CMTG_A 0x6F420
+#define _TRANS_VRR_CTL_CMTG_B 0x6F520
+#define TRANS_VRR_CTL_CMTG(trans) _MMIO_TRANS((trans), \
+ _TRANS_VRR_CTL_CMTG_A, _TRANS_VRR_CTL_CMTG_B)
+#define _TRANS_VRR_VMAX_CMTG_A 0x6F424
+#define _TRANS_VRR_VMAX_CMTG_B 0x6F524
+#define TRANS_VRR_VMAX_CMTG(trans) _MMIO_TRANS((trans), \
+ _TRANS_VRR_VMAX_CMTG_A, \
+ _TRANS_VRR_VMAX_CMTG_B)
+#define _TRANS_VRR_VMIN_CMTG_A 0x6F434
+#define _TRANS_VRR_VMIN_CMTG_B 0x6F534
+#define TRANS_VRR_VMIN_CMTG(trans) _MMIO_TRANS((trans), \
+ _TRANS_VRR_VMIN_CMTG_A, \
+ _TRANS_VRR_VMIN_CMTG_B)
+#define _TRANS_VRR_FLIPLINE_CMTG_A 0x6F438
+#define _TRANS_VRR_FLIPLINE_CMTG_B 0x6F538
+#define TRANS_VRR_FLIPLINE_CMTG(trans) _MMIO_TRANS((trans), \
+ _TRANS_VRR_FLIPLINE_CMTG_A, \
+ _TRANS_VRR_FLIPLINE_CMTG_B)
+
#endif /* __INTEL_CMTG_REGS_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index fae1186a90b2..ce71cf35fba5 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -7,6 +7,7 @@
#include <drm/drm_print.h>
#include "intel_alpm.h"
+#include "intel_cmtg.h"
#include "intel_crtc.h"
#include "intel_de.h"
#include "intel_display_regs.h"
@@ -324,6 +325,8 @@ void intel_vrr_set_fixed_rr_timings(const struct intel_crtc_state *crtc_state)
intel_vrr_fixed_rr_hw_vmax(crtc_state) - 1);
intel_de_write(display, TRANS_VRR_FLIPLINE(display, cpu_transcoder),
intel_vrr_fixed_rr_hw_flipline(crtc_state) - 1);
+
+ intel_cmtg_set_vrr_timings(crtc_state);
}
static
@@ -922,6 +925,8 @@ static void intel_vrr_tg_enable(const struct intel_crtc_state *crtc_state,
vrr_ctl |= VRR_CTL_CMRR_ENABLE;
intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), vrr_ctl);
+
+ intel_cmtg_set_vrr_ctl(crtc_state);
}
static void intel_vrr_tg_disable(const struct intel_crtc_state *old_crtc_state)
--
2.29.0
next prev parent reply other threads:[~2026-04-12 11:07 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-04-12 10:36 [PATCH v4 00/13] CMTG enablement Animesh Manna
2026-04-12 10:37 ` [PATCH v4 01/13] drm/i915/cmtg: Add intel_cmtg_is_allowed() for CMTG Animesh Manna
2026-04-14 13:31 ` Jani Nikula
2026-04-12 10:37 ` [PATCH v4 02/13] drm/i915/cmtg: Set CMTG clock select Animesh Manna
2026-04-12 10:37 ` [PATCH v4 03/13] drm/i915/cmtg: Set timings for CMTG Animesh Manna
2026-04-14 13:33 ` Jani Nikula
2026-04-17 6:03 ` Manna, Animesh
2026-04-17 10:26 ` Ville Syrjälä
2026-04-23 4:37 ` Manna, Animesh
2026-04-23 4:55 ` Manna, Animesh
2026-04-23 10:51 ` Ville Syrjälä
2026-04-23 11:07 ` Manna, Animesh
2026-04-29 12:01 ` Ville Syrjälä
2026-04-30 7:16 ` Manna, Animesh
2026-04-12 10:37 ` Animesh Manna [this message]
2026-04-12 10:37 ` [PATCH v4 05/13] drm/i915/cmtg: Set transcoder mn " Animesh Manna
2026-04-12 10:37 ` [PATCH v4 06/13] drm/i915/cmtg: Add hook to enable CMTG with sync to port Animesh Manna
2026-04-12 10:37 ` [PATCH v4 07/13] drm/i915/cmtg: Add a hook to make eDP transcoder secondary Animesh Manna
2026-04-12 10:37 ` [PATCH v4 08/13] drm/i915/cmtg: Split CMTG support check from intel_cmtg_is_allowed() Animesh Manna
2026-04-12 10:37 ` [PATCH v4 09/13] drm/i915/cmtg: Modify existing hook to disable CMTG Animesh Manna
2026-04-12 10:37 ` [PATCH v4 10/13] drm/i915/cmtg: Add trigger to enable/disable cmtg Animesh Manna
2026-04-12 10:37 ` [PATCH v4 11/13] drm/i915/cmtg: Add CMTG interrupt handling Animesh Manna
2026-04-12 10:37 ` [PATCH v4 12/13] drm/i915/cmtg: Disable CMTG if dc3co is not allowed Animesh Manna
2026-04-12 10:37 ` [PATCH v4 13/13] drm/i915/cmtg: Set target_dc_state flag for lobf/psr2/pr-alpm Animesh Manna
2026-04-13 12:19 ` Dibin Moolakadan Subrahmanian
2026-04-12 11:16 ` ✓ CI.KUnit: success for CMTG enablement (rev5) Patchwork
2026-04-12 12:05 ` ✓ Xe.CI.BAT: " Patchwork
2026-04-12 13:01 ` ✗ Xe.CI.FULL: failure " Patchwork
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