From: Animesh Manna <animesh.manna@intel.com>
To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org
Cc: uma.shankar@intel.com, dibin.moolakadan.subrahmanian@intel.com,
jani.nikula@intel.com, Animesh Manna <animesh.manna@intel.com>
Subject: [PATCH v4 05/13] drm/i915/cmtg: Set transcoder mn for CMTG
Date: Sun, 12 Apr 2026 16:07:04 +0530 [thread overview]
Message-ID: <20260412103712.4021213-6-animesh.manna@intel.com> (raw)
In-Reply-To: <20260412103712.4021213-1-animesh.manna@intel.com>
Program CMTG link M/N.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
drivers/gpu/drm/i915/display/intel_cmtg.c | 13 +++++++++++++
drivers/gpu/drm/i915/display/intel_cmtg.h | 1 +
drivers/gpu/drm/i915/display/intel_cmtg_regs.h | 9 +++++++++
drivers/gpu/drm/i915/display/intel_display.c | 1 +
4 files changed, 24 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c b/drivers/gpu/drm/i915/display/intel_cmtg.c
index c5ef9de2e408..aecee4157405 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.c
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
@@ -314,3 +314,16 @@ void intel_cmtg_set_vrr_ctl(const struct intel_crtc_state *crtc_state)
intel_de_write(display, TRANS_VRR_CTL_CMTG(cpu_transcoder), vrr_ctl);
}
+
+void intel_cmtg_set_m_n(const struct intel_crtc_state *crtc_state)
+{
+ struct intel_display *display = to_intel_display(crtc_state);
+ enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+ const struct intel_link_m_n *m_n = &crtc_state->dp_m_n;
+
+ if (!intel_cmtg_is_allowed(crtc_state))
+ return;
+
+ intel_de_write(display, TRANS_LINKM1_CMTG(cpu_transcoder), m_n->link_m);
+ intel_de_write(display, TRANS_LINKN1_CMTG(cpu_transcoder), m_n->link_n);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.h b/drivers/gpu/drm/i915/display/intel_cmtg.h
index c92e3a62ff0d..6796eb727eef 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.h
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.h
@@ -11,6 +11,7 @@
struct intel_display;
struct intel_crtc_state;
+void intel_cmtg_set_m_n(const struct intel_crtc_state *crtc_state);
void intel_cmtg_set_vrr_timings(const struct intel_crtc_state *crtc_state);
void intel_cmtg_set_vrr_ctl(const struct intel_crtc_state *crtc_state);
void intel_cmtg_set_timings(const struct intel_crtc_state *crtc_state, bool lrr);
diff --git a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
index b50ada371262..b6a549aec033 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
@@ -45,6 +45,15 @@
#define TRANS_VSYNC_CMTG(trans) _MMIO_TRANS((trans), \
_TRANS_VSYNC_CMTG_A, _TRANS_VSYNC_CMTG_B)
+#define _TRANS_LINKM1_CMTG_A 0x6F040
+#define _TRANS_LINKM1_CMTG_B 0x6F140
+#define TRANS_LINKM1_CMTG(trans) _MMIO_TRANS((trans), \
+ _TRANS_LINKM1_CMTG_A, _TRANS_LINKM1_CMTG_B)
+#define _TRANS_LINKN1_CMTG_A 0x6F044
+#define _TRANS_LINKN1_CMTG_B 0x6F144
+#define TRANS_LINKN1_CMTG(trans) _MMIO_TRANS((trans), \
+ _TRANS_LINKN1_CMTG_A, _TRANS_LINKN1_CMTG_B)
+
#define _TRANS_SET_CTX_LATENCY_CMTG_A 0x6F07C
#define _TRANS_SET_CTX_LATENCY_CMTG_B 0x6F17C
#define TRANS_SET_CTX_LATENCY_CMTG(trans) _MMIO_TRANS((trans), \
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index bf58ae5d3535..e8470b7ce13f 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1615,6 +1615,7 @@ static void hsw_configure_cpu_transcoder(const struct intel_crtc_state *crtc_sta
&crtc_state->dp_m2_n2);
}
+ intel_cmtg_set_m_n(crtc_state);
intel_set_transcoder_timings(crtc_state);
if (cpu_transcoder != TRANSCODER_EDP)
--
2.29.0
next prev parent reply other threads:[~2026-04-12 11:07 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-04-12 10:36 [PATCH v4 00/13] CMTG enablement Animesh Manna
2026-04-12 10:37 ` [PATCH v4 01/13] drm/i915/cmtg: Add intel_cmtg_is_allowed() for CMTG Animesh Manna
2026-04-14 13:31 ` Jani Nikula
2026-04-12 10:37 ` [PATCH v4 02/13] drm/i915/cmtg: Set CMTG clock select Animesh Manna
2026-04-12 10:37 ` [PATCH v4 03/13] drm/i915/cmtg: Set timings for CMTG Animesh Manna
2026-04-14 13:33 ` Jani Nikula
2026-04-17 6:03 ` Manna, Animesh
2026-04-17 10:26 ` Ville Syrjälä
2026-04-23 4:37 ` Manna, Animesh
2026-04-23 4:55 ` Manna, Animesh
2026-04-23 10:51 ` Ville Syrjälä
2026-04-23 11:07 ` Manna, Animesh
2026-04-29 12:01 ` Ville Syrjälä
2026-04-30 7:16 ` Manna, Animesh
2026-04-12 10:37 ` [PATCH v4 04/13] drm/i915/cmtg: Program VRR registers of CMTG Animesh Manna
2026-04-12 10:37 ` Animesh Manna [this message]
2026-04-12 10:37 ` [PATCH v4 06/13] drm/i915/cmtg: Add hook to enable CMTG with sync to port Animesh Manna
2026-04-12 10:37 ` [PATCH v4 07/13] drm/i915/cmtg: Add a hook to make eDP transcoder secondary Animesh Manna
2026-04-12 10:37 ` [PATCH v4 08/13] drm/i915/cmtg: Split CMTG support check from intel_cmtg_is_allowed() Animesh Manna
2026-04-12 10:37 ` [PATCH v4 09/13] drm/i915/cmtg: Modify existing hook to disable CMTG Animesh Manna
2026-04-12 10:37 ` [PATCH v4 10/13] drm/i915/cmtg: Add trigger to enable/disable cmtg Animesh Manna
2026-04-12 10:37 ` [PATCH v4 11/13] drm/i915/cmtg: Add CMTG interrupt handling Animesh Manna
2026-04-12 10:37 ` [PATCH v4 12/13] drm/i915/cmtg: Disable CMTG if dc3co is not allowed Animesh Manna
2026-04-12 10:37 ` [PATCH v4 13/13] drm/i915/cmtg: Set target_dc_state flag for lobf/psr2/pr-alpm Animesh Manna
2026-04-13 12:19 ` Dibin Moolakadan Subrahmanian
2026-04-12 11:16 ` ✓ CI.KUnit: success for CMTG enablement (rev5) Patchwork
2026-04-12 12:05 ` ✓ Xe.CI.BAT: " Patchwork
2026-04-12 13:01 ` ✗ Xe.CI.FULL: failure " Patchwork
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