From: Animesh Manna <animesh.manna@intel.com>
To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org
Cc: uma.shankar@intel.com, dibin.moolakadan.subrahmanian@intel.com,
jani.nikula@intel.com, Animesh Manna <animesh.manna@intel.com>
Subject: [PATCH v4 06/13] drm/i915/cmtg: Add hook to enable CMTG with sync to port
Date: Sun, 12 Apr 2026 16:07:05 +0530 [thread overview]
Message-ID: <20260412103712.4021213-7-animesh.manna@intel.com> (raw)
In-Reply-To: <20260412103712.4021213-1-animesh.manna@intel.com>
Add a hook to enable CMTG by programming CMTG CTL with Sync to Port.
When CMTG starts running, the Sync to Port bit will be cleared. Add
a wait to check its running status and trigger WARN_ON() on timeout.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
drivers/gpu/drm/i915/display/intel_cmtg.c | 27 ++++++++++++++++---
drivers/gpu/drm/i915/display/intel_cmtg.h | 1 +
.../gpu/drm/i915/display/intel_cmtg_regs.h | 7 +++--
3 files changed, 29 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c b/drivers/gpu/drm/i915/display/intel_cmtg.c
index aecee4157405..be8b513cde45 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.c
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
@@ -104,11 +104,11 @@ static void intel_cmtg_get_config(struct intel_display *display,
{
u32 val;
- val = intel_de_read(display, TRANS_CMTG_CTL_A);
+ val = intel_de_read(display, TRANS_CMTG_CTL(TRANSCODER_A));
cmtg_config->cmtg_a_enable = val & CMTG_ENABLE;
if (intel_cmtg_has_cmtg_b(display)) {
- val = intel_de_read(display, TRANS_CMTG_CTL_B);
+ val = intel_de_read(display, TRANS_CMTG_CTL(TRANSCODER_B));
cmtg_config->cmtg_b_enable = val & CMTG_ENABLE;
}
@@ -141,14 +141,14 @@ static void intel_cmtg_disable(struct intel_display *display,
if (cmtg_config->cmtg_a_enable) {
drm_dbg_kms(display->drm, "Disabling CMTG A\n");
- intel_de_rmw(display, TRANS_CMTG_CTL_A, CMTG_ENABLE, 0);
+ intel_de_rmw(display, TRANS_CMTG_CTL(TRANSCODER_A), CMTG_ENABLE, 0);
clk_sel_clr |= CMTG_CLK_SEL_A_MASK;
clk_sel_set |= CMTG_CLK_SEL_A_DISABLED;
}
if (cmtg_config->cmtg_b_enable) {
drm_dbg_kms(display->drm, "Disabling CMTG B\n");
- intel_de_rmw(display, TRANS_CMTG_CTL_B, CMTG_ENABLE, 0);
+ intel_de_rmw(display, TRANS_CMTG_CTL(TRANSCODER_B), CMTG_ENABLE, 0);
clk_sel_clr |= CMTG_CLK_SEL_B_MASK;
clk_sel_set |= CMTG_CLK_SEL_B_DISABLED;
}
@@ -327,3 +327,22 @@ void intel_cmtg_set_m_n(const struct intel_crtc_state *crtc_state)
intel_de_write(display, TRANS_LINKM1_CMTG(cpu_transcoder), m_n->link_m);
intel_de_write(display, TRANS_LINKN1_CMTG(cpu_transcoder), m_n->link_n);
}
+
+void intel_cmtg_enable_sync(const struct intel_crtc_state *crtc_state)
+{
+ struct intel_display *display = to_intel_display(crtc_state);
+ enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+ u32 cmtg_ctl;
+
+ if (!intel_cmtg_is_allowed(crtc_state))
+ return;
+
+ cmtg_ctl = CMTG_SYNC_TO_PORT | CMTG_ENABLE;
+
+ intel_de_rmw(display, TRANS_CMTG_CTL(cpu_transcoder), 0, cmtg_ctl);
+ if (intel_de_wait_for_clear_ms(display, TRANS_CMTG_CTL(cpu_transcoder),
+ CMTG_SYNC_TO_PORT, 50)) {
+ drm_WARN(display->drm, 1, "CMTG: %s enable timeout\n",
+ transcoder_name(cpu_transcoder));
+ }
+}
diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.h b/drivers/gpu/drm/i915/display/intel_cmtg.h
index 6796eb727eef..64ff6a19948a 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.h
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.h
@@ -11,6 +11,7 @@
struct intel_display;
struct intel_crtc_state;
+void intel_cmtg_enable_sync(const struct intel_crtc_state *crtc_state);
void intel_cmtg_set_m_n(const struct intel_crtc_state *crtc_state);
void intel_cmtg_set_vrr_timings(const struct intel_crtc_state *crtc_state);
void intel_cmtg_set_vrr_ctl(const struct intel_crtc_state *crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
index b6a549aec033..d447a72bd9fa 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
@@ -16,9 +16,12 @@
#define CMTG_CLK_SELECT_PHYB_ENABLE REG_FIELD_PREP(CMTG_CLK_SEL_B_MASK, 0x6)
#define CMTG_CLK_SEL_B_DISABLED REG_FIELD_PREP(CMTG_CLK_SEL_B_MASK, 0)
-#define TRANS_CMTG_CTL_A _MMIO(0x6fa88)
-#define TRANS_CMTG_CTL_B _MMIO(0x6fb88)
+#define _TRANS_CMTG_CTL_A 0x6fa88
+#define _TRANS_CMTG_CTL_B 0x6fb88
+#define TRANS_CMTG_CTL(trans) _MMIO_TRANS((trans), \
+ _TRANS_CMTG_CTL_A, _TRANS_CMTG_CTL_B)
#define CMTG_ENABLE REG_BIT(31)
+#define CMTG_SYNC_TO_PORT REG_BIT(29)
#define _TRANS_HTOTAL_CMTG_A 0x6F000
#define _TRANS_HTOTAL_CMTG_B 0x6F100
--
2.29.0
next prev parent reply other threads:[~2026-04-12 11:08 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-04-12 10:36 [PATCH v4 00/13] CMTG enablement Animesh Manna
2026-04-12 10:37 ` [PATCH v4 01/13] drm/i915/cmtg: Add intel_cmtg_is_allowed() for CMTG Animesh Manna
2026-04-14 13:31 ` Jani Nikula
2026-04-12 10:37 ` [PATCH v4 02/13] drm/i915/cmtg: Set CMTG clock select Animesh Manna
2026-04-12 10:37 ` [PATCH v4 03/13] drm/i915/cmtg: Set timings for CMTG Animesh Manna
2026-04-14 13:33 ` Jani Nikula
2026-04-17 6:03 ` Manna, Animesh
2026-04-17 10:26 ` Ville Syrjälä
2026-04-23 4:37 ` Manna, Animesh
2026-04-23 4:55 ` Manna, Animesh
2026-04-23 10:51 ` Ville Syrjälä
2026-04-23 11:07 ` Manna, Animesh
2026-04-29 12:01 ` Ville Syrjälä
2026-04-30 7:16 ` Manna, Animesh
2026-04-12 10:37 ` [PATCH v4 04/13] drm/i915/cmtg: Program VRR registers of CMTG Animesh Manna
2026-04-12 10:37 ` [PATCH v4 05/13] drm/i915/cmtg: Set transcoder mn for CMTG Animesh Manna
2026-04-12 10:37 ` Animesh Manna [this message]
2026-04-12 10:37 ` [PATCH v4 07/13] drm/i915/cmtg: Add a hook to make eDP transcoder secondary Animesh Manna
2026-04-12 10:37 ` [PATCH v4 08/13] drm/i915/cmtg: Split CMTG support check from intel_cmtg_is_allowed() Animesh Manna
2026-04-12 10:37 ` [PATCH v4 09/13] drm/i915/cmtg: Modify existing hook to disable CMTG Animesh Manna
2026-04-12 10:37 ` [PATCH v4 10/13] drm/i915/cmtg: Add trigger to enable/disable cmtg Animesh Manna
2026-04-12 10:37 ` [PATCH v4 11/13] drm/i915/cmtg: Add CMTG interrupt handling Animesh Manna
2026-04-12 10:37 ` [PATCH v4 12/13] drm/i915/cmtg: Disable CMTG if dc3co is not allowed Animesh Manna
2026-04-12 10:37 ` [PATCH v4 13/13] drm/i915/cmtg: Set target_dc_state flag for lobf/psr2/pr-alpm Animesh Manna
2026-04-13 12:19 ` Dibin Moolakadan Subrahmanian
2026-04-12 11:16 ` ✓ CI.KUnit: success for CMTG enablement (rev5) Patchwork
2026-04-12 12:05 ` ✓ Xe.CI.BAT: " Patchwork
2026-04-12 13:01 ` ✗ Xe.CI.FULL: failure " Patchwork
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20260412103712.4021213-7-animesh.manna@intel.com \
--to=animesh.manna@intel.com \
--cc=dibin.moolakadan.subrahmanian@intel.com \
--cc=intel-gfx@lists.freedesktop.org \
--cc=intel-xe@lists.freedesktop.org \
--cc=jani.nikula@intel.com \
--cc=uma.shankar@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).