From: Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>
To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org
Cc: animesh.manna@intel.com, uma.shankar@intel.com,
suresh.kumar.kurmi@intel.com
Subject: [PATCH v2 02/13] drm/i915/display: Switch DC3Co enable from standalone bit to DC level encoding
Date: Wed, 22 Apr 2026 21:56:10 +0530 [thread overview]
Message-ID: <20260422162622.1869831-3-dibin.moolakadan.subrahmanian@intel.com> (raw)
In-Reply-To: <20260422162622.1869831-1-dibin.moolakadan.subrahmanian@intel.com>
On platforms prior to xe3, DC3CO was controlled via a standalone enable
bit. Starting with xe3, DC3CO is encoded as part of the existing
DC_STATE_EN_UPTO_DC* field.
No functional change, as DC3CO is not enabled on platforms prior to xe3.
Changes in v2:
- Update commit header (Uma Shankar)
Signed-off-by: Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/display/intel_display_power.c | 6 +++---
drivers/gpu/drm/i915/display/intel_display_power_well.c | 4 ++--
drivers/gpu/drm/i915/display/intel_display_regs.h | 2 +-
drivers/gpu/drm/i915/display/intel_dmc_wl.c | 2 +-
4 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 80ecf373fb19..77c32492caa1 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -267,7 +267,7 @@ sanitize_target_dc_state(struct intel_display *display,
static const u32 states[] = {
DC_STATE_EN_UPTO_DC6,
DC_STATE_EN_UPTO_DC5,
- DC_STATE_EN_DC3CO,
+ DC_STATE_EN_UPTO_DC3CO,
DC_STATE_DISABLE,
};
int i;
@@ -999,10 +999,10 @@ static u32 get_allowed_dc_mask(struct intel_display *display, int enable_dc)
switch (requested_dc) {
case 4:
- mask |= DC_STATE_EN_DC3CO | DC_STATE_EN_UPTO_DC6;
+ mask |= DC_STATE_EN_UPTO_DC3CO | DC_STATE_EN_UPTO_DC6;
break;
case 3:
- mask |= DC_STATE_EN_DC3CO | DC_STATE_EN_UPTO_DC5;
+ mask |= DC_STATE_EN_UPTO_DC3CO | DC_STATE_EN_UPTO_DC5;
break;
case 2:
mask |= DC_STATE_EN_UPTO_DC6;
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
index a7c5290edec1..b5e6437c3d8d 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
@@ -772,7 +772,7 @@ static u32 gen9_dc_mask(struct intel_display *display)
mask = DC_STATE_EN_UPTO_DC5;
if (DISPLAY_VER(display) >= 12)
- mask |= DC_STATE_EN_DC3CO | DC_STATE_EN_UPTO_DC6
+ mask |= DC_STATE_EN_UPTO_DC3CO | DC_STATE_EN_UPTO_DC6
| DC_STATE_EN_DC9;
else if (DISPLAY_VER(display) == 11)
mask |= DC_STATE_EN_UPTO_DC6 | DC_STATE_EN_DC9;
@@ -1022,7 +1022,7 @@ static void bxt_verify_dpio_phy_power_wells(struct intel_display *display)
static bool gen9_dc_off_power_well_enabled(struct intel_display *display,
struct i915_power_well *power_well)
{
- return ((intel_de_read(display, DC_STATE_EN) & DC_STATE_EN_DC3CO) == 0 &&
+ return ((intel_de_read(display, DC_STATE_EN) & DC_STATE_EN_UPTO_DC3CO) == 0 &&
(intel_de_read(display, DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0);
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
index dada8dc27ea4..2ad211da9157 100644
--- a/drivers/gpu/drm/i915/display/intel_display_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
@@ -3039,13 +3039,13 @@ enum skl_power_gate {
/* GEN9 DC */
#define DC_STATE_EN _MMIO(0x45504)
#define DC_STATE_DISABLE 0
-#define DC_STATE_EN_DC3CO REG_BIT(30)
#define DC_STATE_DC3CO_STATUS REG_BIT(29)
#define HOLD_PHY_CLKREQ_PG1_LATCH REG_BIT(21)
#define HOLD_PHY_PG1_LATCH REG_BIT(20)
#define DC_STATE_EN_UPTO_DC5 (1 << 0)
#define DC_STATE_EN_DC9 (1 << 3)
#define DC_STATE_EN_UPTO_DC6 (2 << 0)
+#define DC_STATE_EN_UPTO_DC3CO (3 << 0)
#define DC_STATE_EN_UPTO_DC5_DC6_MASK 0x3
#define DC_STATE_DEBUG _MMIO(0x45520)
diff --git a/drivers/gpu/drm/i915/display/intel_dmc_wl.c b/drivers/gpu/drm/i915/display/intel_dmc_wl.c
index ddf1a1f1ebc3..13192531cd49 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc_wl.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc_wl.c
@@ -260,7 +260,7 @@ static bool intel_dmc_wl_check_range(struct intel_display *display,
* the DMC and requires a DC exit for proper access.
*/
switch (dc_state) {
- case DC_STATE_EN_DC3CO:
+ case DC_STATE_EN_UPTO_DC3CO:
ranges = xe3lpd_dc3co_dmc_ranges;
break;
case DC_STATE_EN_UPTO_DC5:
--
2.43.0
next prev parent reply other threads:[~2026-04-22 16:26 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-04-22 16:26 [PATCH v2 00/13] drm/i915/display: Add DC3CO support Dibin Moolakadan Subrahmanian
2026-04-22 16:26 ` [PATCH v2 01/13] drm/i915/display: Remove TGL " Dibin Moolakadan Subrahmanian
2026-04-22 16:26 ` Dibin Moolakadan Subrahmanian [this message]
2026-04-22 16:26 ` [PATCH v2 03/13] drm/i915/display: Use FIELD_PREP() for DC state enable bits Dibin Moolakadan Subrahmanian
2026-04-22 16:26 ` [PATCH v2 04/13] drm/i915/display: Add DC3CO DC_STATE enable/disable support Dibin Moolakadan Subrahmanian
2026-04-22 16:26 ` [PATCH v2 05/13] drm/i915/display: Add DC3CO support check and validate target DC state Dibin Moolakadan Subrahmanian
2026-04-29 5:13 ` Manna, Animesh
2026-04-29 7:31 ` Dibin Moolakadan Subrahmanian
2026-04-22 16:26 ` [PATCH v2 06/13] drm/i915/display: Add HAS_DC3CO() macro Dibin Moolakadan Subrahmanian
2026-04-27 3:00 ` Shankar, Uma
2026-04-22 16:26 ` [PATCH v2 07/13] drm/i915/display: Add DC3CO eligibility computation Dibin Moolakadan Subrahmanian
2026-04-27 3:10 ` Shankar, Uma
2026-04-27 6:06 ` Dibin Moolakadan Subrahmanian
2026-04-29 5:42 ` Manna, Animesh
2026-04-29 7:05 ` Dibin Moolakadan Subrahmanian
2026-04-22 16:26 ` [PATCH v2 08/13] drm/i915/display: Store DC3CO eligibility in PSR state Dibin Moolakadan Subrahmanian
2026-04-27 3:11 ` Shankar, Uma
2026-04-22 16:26 ` [PATCH v2 09/13] drm/i915/display: PSR2: Set idle_frames to 0 for DC3CO Dibin Moolakadan Subrahmanian
2026-04-27 3:13 ` Shankar, Uma
2026-04-22 16:26 ` [PATCH v2 10/13] drm/i915/display: Enable DC3CO idle protocol in ALPM Dibin Moolakadan Subrahmanian
2026-04-27 3:14 ` Shankar, Uma
2026-04-22 16:26 ` [PATCH v2 11/13] drm/i915/display: PSR Add delayed work to exit DC3CO Dibin Moolakadan Subrahmanian
2026-04-27 3:15 ` Shankar, Uma
2026-04-22 16:26 ` [PATCH v2 12/13] drm/i915/display: Add helper to enable DC counter Dibin Moolakadan Subrahmanian
2026-04-22 16:26 ` [PATCH v2 13/13] drm/i915/display: Add DC3CO count and residency in dmc debugfs Dibin Moolakadan Subrahmanian
2026-04-22 21:27 ` ✓ CI.KUnit: success for drm/i915/display: Add DC3CO support (rev2) Patchwork
2026-04-22 22:50 ` ✓ Xe.CI.BAT: " Patchwork
2026-04-23 6:15 ` ✗ Xe.CI.FULL: failure " Patchwork
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