From: Vinod Govindapillai <vinod.govindapillai@intel.com>
To: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org
Cc: vinod.govindapillai@intel.com, ville.syrjala@linux.intel.com
Subject: [PATCH v2 06/11] drm/i915/bw: update the routine to get max dclk from qgv points
Date: Mon, 11 May 2026 15:28:11 +0300 [thread overview]
Message-ID: <20260511122816.1235478-7-vinod.govindapillai@intel.com> (raw)
In-Reply-To: <20260511122816.1235478-1-vinod.govindapillai@intel.com>
As the qgv points are in the sorted order in pmdemand supported
versions, get the dclk from last qgv point.
Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
---
drivers/gpu/drm/i915/display/intel_bw.c | 16 ++++++++++++----
1 file changed, 12 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index 7b8801a88cb2..f05fdb5f24c9 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -391,11 +391,19 @@ static int adl_calc_psf_bw(int clk)
return DIV_ROUND_CLOSEST(64 * clk * 100, 6);
}
-static int icl_sagv_max_dclk(const struct intel_qgv_info *qi)
+static int icl_sagv_max_dclk(struct intel_display *display,
+ const struct intel_qgv_info *qi)
{
u16 dclk = 0;
int i;
+ /* QGV points are in sorted order in pmdemand supported versions */
+ if (HAS_PMDEMAND(display)) {
+ int max_point = max(0, qi->num_points - 1);
+
+ return qi->points[max_point].dclk;
+ }
+
for (i = 0; i < qi->num_points; i++)
dclk = max(dclk, qi->points[i].dclk);
@@ -495,7 +503,7 @@ static int icl_get_bw_info(struct intel_display *display,
return ret;
}
- dclk_max = icl_sagv_max_dclk(&qi);
+ dclk_max = icl_sagv_max_dclk(display, &qi);
maxdebw = min(sa->deprogbwlimit * 1000, dclk_max * 16 * 6 / 10);
ipqdepth = min(ipqdepthpch, sa->displayrtids / num_channels);
qi.deinterleave = DIV_ROUND_UP(num_channels, is_y_tile ? 4 : 2);
@@ -581,7 +589,7 @@ static int tgl_get_bw_info(struct intel_display *display,
if (qi.max_numchannels != 0)
num_channels = min_t(u8, num_channels, qi.max_numchannels);
- dclk_max = icl_sagv_max_dclk(&qi);
+ dclk_max = icl_sagv_max_dclk(display, &qi);
peakbw = num_channels * DIV_ROUND_UP(qi.channel_width, 8) * dclk_max;
maxdebw = min(sa->deprogbwlimit * 1000, peakbw * DEPROGBWPCLIMIT / 100);
@@ -705,7 +713,7 @@ static int xe2_hpd_get_bw_info(struct intel_display *display,
return ret;
}
- peakbw = num_channels * qi.channel_width / 8 * icl_sagv_max_dclk(&qi);
+ peakbw = num_channels * qi.channel_width / 8 * icl_sagv_max_dclk(display, &qi);
maxdebw = min(sa->deprogbwlimit * 1000, peakbw * DEPROGBWPCLIMIT / 10);
for (i = 0; i < qi.num_points; i++) {
--
2.43.0
next prev parent reply other threads:[~2026-05-11 12:28 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-11 12:28 [PATCH v2 00/11] drm/i915/display: reduce the pm demand peak bw based on display data rate Vinod Govindapillai
2026-05-11 12:28 ` [PATCH v2 01/11] drm/i915/wm: clear the plane ddb_y entries on plane disable Vinod Govindapillai
2026-05-11 12:28 ` [PATCH v2 02/11] drm/i915/pm_demand: introduce HAS_PMDEMAND macro Vinod Govindapillai
2026-05-11 12:28 ` [PATCH v2 03/11] drm/i915/display: sagv pre/post plane calls to check pmdemand support Vinod Govindapillai
2026-05-11 12:28 ` [PATCH v2 04/11] drm/i915/bw: Extract icl_init_qgv_info() Vinod Govindapillai
2026-05-11 12:28 ` [PATCH v2 05/11] drm/i915/bw: sort the qgv points based on the dclk Vinod Govindapillai
2026-05-11 12:28 ` Vinod Govindapillai [this message]
2026-05-11 12:28 ` [PATCH v2 07/11] drm/i915/bw: update the routine to find the peakbw in MTL Vinod Govindapillai
2026-05-11 12:28 ` [PATCH v2 08/11] drm/i915/bw: update the tile-y dependency based on the display version Vinod Govindapillai
2026-05-11 12:28 ` [PATCH v2 09/11] drm/i915/bw: consolidate the debug info of bw/dgv/psf data Vinod Govindapillai
2026-05-12 11:49 ` Jani Nikula
2026-05-11 12:28 ` [PATCH v2 10/11] drm/i915/bw: extract update_sagv_status() Vinod Govindapillai
2026-05-11 12:28 ` [PATCH v2 11/11] drm/i915/bw: insert a sw bw info entry to cater low data rate usecases Vinod Govindapillai
2026-05-12 11:51 ` Jani Nikula
2026-05-12 12:02 ` Govindapillai, Vinod
2026-05-11 16:28 ` ✓ CI.KUnit: success for drm/i915/display: reduce the pm demand peak bw based on display data rate Patchwork
2026-05-11 17:33 ` ✓ Xe.CI.BAT: " Patchwork
2026-05-11 19:30 ` ✗ Xe.CI.FULL: failure " Patchwork
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