From: Vinod Govindapillai <vinod.govindapillai@intel.com>
To: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org
Cc: vinod.govindapillai@intel.com, ville.syrjala@linux.intel.com
Subject: [PATCH v2 08/11] drm/i915/bw: update the tile-y dependency based on the display version
Date: Mon, 11 May 2026 15:28:13 +0300 [thread overview]
Message-ID: <20260511122816.1235478-9-vinod.govindapillai@intel.com> (raw)
In-Reply-To: <20260511122816.1235478-1-vinod.govindapillai@intel.com>
Consolidate the tile-y dependency into a separate function and
use it to determine whether tile-y need to take into account for
the bw calculations. Especially for post MTL cases, as per the
bspec, no need to take the tile_y into account for the
de interleave values.
Bspec: 64631, 68859
Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
---
drivers/gpu/drm/i915/display/intel_bw.c | 13 +++++++++++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index 177c3fd8f74a..858da1710a61 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -483,12 +483,21 @@ static const struct intel_sa_info xe3lpd_3002_sa_info = {
.derating = 10,
};
+static bool is_tile_y_factored(struct intel_display *display)
+{
+ /* TGL supports Y-tile for LPDDR4/5, but not for DDR4 */
+ if (DISPLAY_VER(display) >= 14)
+ return false;
+
+ return true;
+}
+
static int icl_get_bw_info(struct intel_display *display,
const struct dram_info *dram_info,
const struct intel_sa_info *sa)
{
struct intel_qgv_info qi = {};
- bool is_y_tile = true; /* assume y tile may be used */
+ bool is_y_tile = is_tile_y_factored(display);
int num_channels = max_t(u8, 1, dram_info->num_channels);
int ipqdepth, ipqdepthpch = 16;
int dclk_max;
@@ -559,7 +568,7 @@ static int tgl_get_bw_info(struct intel_display *display,
const struct intel_sa_info *sa)
{
struct intel_qgv_info qi = {};
- bool is_y_tile = true; /* assume y tile may be used */
+ bool is_y_tile = is_tile_y_factored(display);
int num_channels = max_t(u8, 1, dram_info->num_channels);
int ipqdepth, ipqdepthpch = 16;
int dclk_max;
--
2.43.0
next prev parent reply other threads:[~2026-05-11 12:28 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-11 12:28 [PATCH v2 00/11] drm/i915/display: reduce the pm demand peak bw based on display data rate Vinod Govindapillai
2026-05-11 12:28 ` [PATCH v2 01/11] drm/i915/wm: clear the plane ddb_y entries on plane disable Vinod Govindapillai
2026-05-11 12:28 ` [PATCH v2 02/11] drm/i915/pm_demand: introduce HAS_PMDEMAND macro Vinod Govindapillai
2026-05-11 12:28 ` [PATCH v2 03/11] drm/i915/display: sagv pre/post plane calls to check pmdemand support Vinod Govindapillai
2026-05-11 12:28 ` [PATCH v2 04/11] drm/i915/bw: Extract icl_init_qgv_info() Vinod Govindapillai
2026-05-11 12:28 ` [PATCH v2 05/11] drm/i915/bw: sort the qgv points based on the dclk Vinod Govindapillai
2026-05-11 12:28 ` [PATCH v2 06/11] drm/i915/bw: update the routine to get max dclk from qgv points Vinod Govindapillai
2026-05-11 12:28 ` [PATCH v2 07/11] drm/i915/bw: update the routine to find the peakbw in MTL Vinod Govindapillai
2026-05-11 12:28 ` Vinod Govindapillai [this message]
2026-05-11 12:28 ` [PATCH v2 09/11] drm/i915/bw: consolidate the debug info of bw/dgv/psf data Vinod Govindapillai
2026-05-12 11:49 ` Jani Nikula
2026-05-11 12:28 ` [PATCH v2 10/11] drm/i915/bw: extract update_sagv_status() Vinod Govindapillai
2026-05-11 12:28 ` [PATCH v2 11/11] drm/i915/bw: insert a sw bw info entry to cater low data rate usecases Vinod Govindapillai
2026-05-12 11:51 ` Jani Nikula
2026-05-12 12:02 ` Govindapillai, Vinod
2026-05-11 16:28 ` ✓ CI.KUnit: success for drm/i915/display: reduce the pm demand peak bw based on display data rate Patchwork
2026-05-11 17:33 ` ✓ Xe.CI.BAT: " Patchwork
2026-05-11 19:30 ` ✗ Xe.CI.FULL: failure " Patchwork
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