From: Animesh Manna <animesh.manna@intel.com>
To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org
Cc: uma.shankar@intel.com, dibin.moolakadan.subrahmanian@intel.com,
ville.syrjala@linux.intel.com, jani.nikula@intel.com,
Animesh Manna <animesh.manna@intel.com>
Subject: [PATCH v5 15/15] drm/i915/cmtg: Restore CMTG after DC6 entry
Date: Tue, 12 May 2026 19:02:08 +0530 [thread overview]
Message-ID: <20260512133208.1363116-16-animesh.manna@intel.com> (raw)
In-Reply-To: <20260512133208.1363116-1-animesh.manna@intel.com>
Restore CMTG registers after DC6 exit, as they lose their values
in the low-power state.
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 12 ++++++++-
.../drm/i915/display/intel_display_power.c | 25 +++++++++++++++++++
.../drm/i915/display/intel_display_power.h | 3 +++
3 files changed, 39 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 6dc561713c35..324a2c722422 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7544,9 +7544,19 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
bool modeset = intel_crtc_needs_modeset(new_crtc_state);
+ bool dc3co_to_dc6 = intel_display_power_get_dc3co_to_dc6(display);
/* CMTG needs to be restored on DC6 exit and on modset*/
- if (modeset && new_crtc_state->hw.active && !crtc->cmtg.enabled) {
+ if ((modeset || dc3co_to_dc6) && new_crtc_state->hw.active && !crtc->cmtg.enabled) {
+ if (dc3co_to_dc6) {
+ intel_cmtg_set_clk_select(new_crtc_state);
+ intel_cmtg_set_timings(new_crtc_state, false);
+ intel_cmtg_set_vrr_timings(new_crtc_state);
+ intel_cmtg_set_vrr_ctl(new_crtc_state);
+ intel_cmtg_set_m_n(new_crtc_state);
+ intel_display_power_reset_dc3co_to_dc6(display);
+ }
+
intel_cmtg_enable_sync(new_crtc_state);
intel_cmtg_set_hwgb(new_crtc_state);
intel_cmtg_enable_ddi(new_crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 80ecf373fb19..94f6f4b1f388 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -285,6 +285,27 @@ sanitize_target_dc_state(struct intel_display *display,
return target_dc_state;
}
+bool intel_display_power_get_dc3co_to_dc6(struct intel_display *display)
+{
+ struct i915_power_domains *power_domains = &display->power.domains;
+ bool ret;
+
+ mutex_lock(&power_domains->lock);
+ ret = power_domains->dc3co_to_dc6;
+ mutex_unlock(&power_domains->lock);
+
+ return ret;
+}
+
+void intel_display_power_reset_dc3co_to_dc6(struct intel_display *display)
+{
+ struct i915_power_domains *power_domains = &display->power.domains;
+
+ mutex_lock(&power_domains->lock);
+ power_domains->dc3co_to_dc6 = false;
+ mutex_unlock(&power_domains->lock);
+}
+
/**
* intel_display_power_set_target_dc_state - Set target dc state.
* @display: display device
@@ -320,6 +341,10 @@ void intel_display_power_set_target_dc_state(struct intel_display *display,
if (!dc_off_enabled)
intel_power_well_enable(display, power_well);
+ if (power_domains->target_dc_state == DC_STATE_EN_UPTO_DC3CO &&
+ state == DC_STATE_EN_UPTO_DC6)
+ power_domains->dc3co_to_dc6 = true;
+
power_domains->target_dc_state = state;
if (!dc_off_enabled)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
index d616d5d09cbe..ce1225bbc789 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power.h
@@ -138,6 +138,7 @@ struct i915_power_domains {
*/
bool initializing;
bool display_core_suspended;
+ bool dc3co_to_dc6;
int power_well_count;
u32 dc_state;
@@ -183,6 +184,8 @@ void intel_display_power_suspend_late(struct intel_display *display, bool s2idle
void intel_display_power_resume_early(struct intel_display *display);
void intel_display_power_suspend(struct intel_display *display);
void intel_display_power_resume(struct intel_display *display);
+bool intel_display_power_get_dc3co_to_dc6(struct intel_display *display);
+void intel_display_power_reset_dc3co_to_dc6(struct intel_display *display);
void intel_display_power_set_target_dc_state(struct intel_display *display,
u32 state);
u32 intel_display_power_get_current_dc_state(struct intel_display *display);
--
2.29.0
next prev parent reply other threads:[~2026-05-12 14:04 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-12 13:31 [PATCH v5 00/15] CMTG enablement Animesh Manna
2026-05-12 13:31 ` [PATCH v5 01/15] drm/i915/cmtg: Add intel_cmtg_is_allowed() for CMTG Animesh Manna
2026-05-12 13:31 ` [PATCH v5 02/15] drm/i915/cmtg: Set CMTG clock select Animesh Manna
2026-05-12 13:31 ` [PATCH v5 03/15] drm/i915/cmtg: Add cmtg transcoder offset in struct _device_info Animesh Manna
2026-05-12 13:31 ` [PATCH v5 04/15] drm/i915/cmtg: Set timings for CMTG Animesh Manna
2026-05-12 13:31 ` [PATCH v5 05/15] drm/i915/cmtg: Program VRR registers of CMTG Animesh Manna
2026-05-12 13:31 ` [PATCH v5 06/15] drm/i915/cmtg: Set transcoder mn for CMTG Animesh Manna
2026-05-12 13:32 ` [PATCH v5 07/15] drm/i915/cmtg: Add hook to enable CMTG with sync to port Animesh Manna
2026-05-12 13:32 ` [PATCH v5 08/15] drm/i915/cmtg: Add a hook to make eDP transcoder secondary Animesh Manna
2026-05-12 13:32 ` [PATCH v5 09/15] drm/i915/cmtg: Split CMTG support check from intel_cmtg_is_allowed() Animesh Manna
2026-05-12 13:32 ` [PATCH v5 10/15] drm/i915/cmtg: Modify existing hook to disable CMTG Animesh Manna
2026-05-12 13:32 ` [PATCH v5 11/15] drm/i915/cmtg: Add CMTG interrupt handling Animesh Manna
2026-05-12 13:32 ` [PATCH v5 12/15] drm/i915/cmtg: Add CMTG HWGB programming Animesh Manna
2026-05-12 13:32 ` [PATCH v5 13/15] drm/i915/cmtg: Add CMTG scan line programming Animesh Manna
2026-05-12 13:32 ` [PATCH v5 14/15] drm/i915/cmtg: Add trigger to enable/disable cmtg Animesh Manna
2026-05-12 13:32 ` Animesh Manna [this message]
2026-05-13 3:19 ` ✓ CI.KUnit: success for CMTG enablement (rev6) Patchwork
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