From: "Manna, Animesh" <animesh.manna@intel.com>
To: "Nikula, Jani" <jani.nikula@intel.com>,
"intel-gfx@lists.freedesktop.org"
<intel-gfx@lists.freedesktop.org>,
"intel-xe@lists.freedesktop.org" <intel-xe@lists.freedesktop.org>
Cc: "Shankar, Uma" <uma.shankar@intel.com>,
Dibin Moolakadan Subrahmanian
<dibin.moolakadan.subrahmanian@intel.com>
Subject: RE: [PATCH v4 03/13] drm/i915/cmtg: Set timings for CMTG
Date: Fri, 17 Apr 2026 06:03:52 +0000 [thread overview]
Message-ID: <DS0PR11MB804961654148D027B4F03601F9202@DS0PR11MB8049.namprd11.prod.outlook.com> (raw)
In-Reply-To: <d9c82dabf89fb932b3c10aa0ee768fdda181c396@intel.com>
> -----Original Message-----
> From: Nikula, Jani <jani.nikula@intel.com>
> Sent: Tuesday, April 14, 2026 7:03 PM
> To: Manna, Animesh <animesh.manna@intel.com>; intel-
> gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Cc: Shankar, Uma <uma.shankar@intel.com>; Dibin Moolakadan
> Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>; Manna,
> Animesh <animesh.manna@intel.com>
> Subject: Re: [PATCH v4 03/13] drm/i915/cmtg: Set timings for CMTG
>
> On Sun, 12 Apr 2026, Animesh Manna <animesh.manna@intel.com> wrote:
> > Timing registers are separate for CMTG, read transcoder register and
> > program cmtg transcoder with those values.
> >
> > v2:
> > - Use sw state instead of reading directly from hardware. [Jani]
> > - Move set_timing later after encoder enable. [Dibin]
> >
> > v3:
> > - Replace id with trans. [Jani]
> > - Program cmtg set_timing() along with primary transcoder timing.
> >
> > v4:
> > - Use _MMIO_TRANS() for cmtg registers instead of direct
> > multiplication. [Jani]
> >
> > Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_cmtg.c | 61 ++++++++++++++++++-
> > drivers/gpu/drm/i915/display/intel_cmtg.h | 3 +
> > .../gpu/drm/i915/display/intel_cmtg_regs.h | 31 ++++++++++
> > drivers/gpu/drm/i915/display/intel_display.c | 4 ++
> > 4 files changed, 98 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c
> > b/drivers/gpu/drm/i915/display/intel_cmtg.c
> > index 403f9e10a8dc..a3db1368bd83 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cmtg.c
> > +++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
> > @@ -4,7 +4,6 @@
> > */
> >
> > #include <linux/string_choices.h>
> > -#include <linux/types.h>
> >
> > #include <drm/drm_device.h>
> > #include <drm/drm_print.h>
> > @@ -222,3 +221,63 @@ void intel_cmtg_set_clk_select(const struct
> intel_crtc_state *crtc_state)
> > if (clk_sel_set)
> > intel_de_rmw(display, CMTG_CLK_SEL, clk_sel_clr,
> clk_sel_set); }
> > +
> > +void intel_cmtg_set_timings(const struct intel_crtc_state
> > +*crtc_state, bool lrr) {
> > + struct intel_display *display = to_intel_display(crtc_state);
> > + enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> > + const struct drm_display_mode *adjusted_mode = &crtc_state-
> >hw.adjusted_mode;
> > + u32 crtc_vdisplay, crtc_vtotal, crtc_vblank_start, crtc_vblank_end;
> > +
> > + if (!intel_cmtg_is_allowed(crtc_state))
> > + return;
> > +
> > + crtc_vdisplay = adjusted_mode->crtc_vdisplay;
> > +
> > + /*
> > + * For platforms that always use VRR Timing Generator, the
> VTOTAL.Vtotal
> > + * bits are not required. Since the support for these bits is going to
> > + * be deprecated in upcoming platforms, avoid writing these bits for
> the
> > + * platforms that do not use legacy Timing Generator.
> > + */
> > + crtc_vtotal = 1;
> > +
> > + /*
> > + * VBLANK_START not used by hw, just clear it
> > + * to make it stand out in register dumps.
> > + */
> > + crtc_vblank_start = 1;
> > +
> > + crtc_vblank_end = adjusted_mode->crtc_vblank_end;
> > +
> > + if (lrr) {
> > + intel_de_write(display,
> TRANS_VTOTAL_CMTG(cpu_transcoder),
> > + VACTIVE(crtc_vdisplay - 1) |
> > + VTOTAL(crtc_vtotal - 1));
> > + intel_de_write(display,
> TRANS_VBLANK_CMTG(cpu_transcoder),
> > + VBLANK_START(crtc_vblank_start - 1) |
> > + VBLANK_END(crtc_vblank_end - 1));
> > + return;
> > + }
> > +
> > + intel_de_write(display, TRANS_HTOTAL_CMTG(cpu_transcoder),
> > + HACTIVE(adjusted_mode->crtc_hdisplay - 1) |
> > + HTOTAL(adjusted_mode->crtc_htotal - 1));
> > + intel_de_write(display, TRANS_HBLANK_CMTG(cpu_transcoder),
> > + HBLANK_START(adjusted_mode->crtc_hblank_start - 1) |
> > + HBLANK_END(adjusted_mode->crtc_hblank_end - 1));
> > + intel_de_write(display, TRANS_HSYNC_CMTG(cpu_transcoder),
> > + HSYNC_START(adjusted_mode->crtc_hsync_start - 1) |
> > + HSYNC_END(adjusted_mode->crtc_hsync_end - 1));
> > + intel_de_write(display, TRANS_VTOTAL_CMTG(cpu_transcoder),
> > + VACTIVE(crtc_vdisplay - 1) |
> > + VTOTAL(crtc_vtotal - 1));
> > + intel_de_write(display, TRANS_VBLANK_CMTG(cpu_transcoder),
> > + VBLANK_START(crtc_vblank_start - 1) |
> > + VBLANK_END(crtc_vblank_end - 1));
> > + intel_de_write(display, TRANS_VSYNC_CMTG(cpu_transcoder),
> > + VSYNC_START(adjusted_mode->crtc_vsync_start - 1) |
> > + VSYNC_END(adjusted_mode->crtc_vsync_end - 1));
> > + intel_de_write(display,
> TRANS_SET_CTX_LATENCY_CMTG(cpu_transcoder),
> > + crtc_state->set_context_latency); }
> > diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.h
> > b/drivers/gpu/drm/i915/display/intel_cmtg.h
> > index 660ec513626e..53a44f505dd2 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cmtg.h
> > +++ b/drivers/gpu/drm/i915/display/intel_cmtg.h
> > @@ -6,9 +6,12 @@
> > #ifndef __INTEL_CMTG_H__
> > #define __INTEL_CMTG_H__
> >
> > +#include <linux/types.h>
> > +
> > struct intel_display;
> > struct intel_crtc_state;
> >
> > +void intel_cmtg_set_timings(const struct intel_crtc_state
> > +*crtc_state, bool lrr);
> > void intel_cmtg_set_clk_select(const struct intel_crtc_state
> > *crtc_state); void intel_cmtg_sanitize(struct intel_display
> > *display); bool intel_cmtg_is_allowed(const struct intel_crtc_state
> > *crtc_state); diff --git
> > a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> > b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> > index 4a80b88d88fd..f7fc812d8ef0 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> > +++ b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> > @@ -20,4 +20,35 @@
> > #define TRANS_CMTG_CTL_B _MMIO(0x6fb88)
> > #define CMTG_ENABLE REG_BIT(31)
> >
> > +#define _TRANS_HTOTAL_CMTG_A 0x6F000
> > +#define _TRANS_HTOTAL_CMTG_B 0x6F100
> > +#define TRANS_HTOTAL_CMTG(trans) _MMIO_TRANS((trans), \
> > + _TRANS_HTOTAL_CMTG_A,
> _TRANS_HTOTAL_CMTG_B)
> > +#define _TRANS_HBLANK_CMTG_A 0x6F004
> > +#define _TRANS_HBLANK_CMTG_B 0x6F104
> > +#define TRANS_HBLANK_CMTG(trans) _MMIO_TRANS((trans), \
> > + _TRANS_HBLANK_CMTG_A,
> _TRANS_HBLANK_CMTG_B)
> > +#define _TRANS_HSYNC_CMTG_A 0x6F008
> > +#define _TRANS_HSYNC_CMTG_B 0x6F108
> > +#define TRANS_HSYNC_CMTG(trans)
> _MMIO_TRANS((trans), \
> > + _TRANS_HSYNC_CMTG_A,
> _TRANS_HSYNC_CMTG_B)
> > +#define _TRANS_VTOTAL_CMTG_A 0x6F00C
> > +#define _TRANS_VTOTAL_CMTG_B 0x6F10C
> > +#define TRANS_VTOTAL_CMTG(trans) _MMIO_TRANS((trans), \
> > + _TRANS_VTOTAL_CMTG_A,
> _TRANS_VTOTAL_CMTG_B)
> > +#define _TRANS_VBLANK_CMTG_A 0x6F010
> > +#define _TRANS_VBLANK_CMTG_B 0x6F110
> > +#define TRANS_VBLANK_CMTG(trans) _MMIO_TRANS((trans), \
> > + _TRANS_VBLANK_CMTG_A,
> _TRANS_VBLANK_CMTG_B)
> > +#define _TRANS_VSYNC_CMTG_A 0x6F014
> > +#define _TRANS_VSYNC_CMTG_B 0x6F114
> > +#define TRANS_VSYNC_CMTG(trans)
> _MMIO_TRANS((trans), \
> > + _TRANS_VSYNC_CMTG_A,
> _TRANS_VSYNC_CMTG_B)
>
> I though there was already feedback that these match the regular transcoder
> registers.
_TRANS_HTOTAL_A 0x60000
_TRANS_HTOTAL_B 0x61000
_TRANS_HTOTAL_CMTG_A 0x6F000
_TRANS_HTOTAL_CMTG_B 0x6F100
I am not clear how to match?
Regards,
Animesh
>
> BR,
> Jani.
>
> > +
> > +#define _TRANS_SET_CTX_LATENCY_CMTG_A 0x6F07C
> > +#define _TRANS_SET_CTX_LATENCY_CMTG_B 0x6F17C
> > +#define TRANS_SET_CTX_LATENCY_CMTG(trans)
> _MMIO_TRANS((trans), \
> > +
> _TRANS_SET_CTX_LATENCY_CMTG_A, \
> > +
> _TRANS_SET_CTX_LATENCY_CMTG_B)
> > +
> > #endif /* __INTEL_CMTG_REGS_H__ */
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index 58a654ca0d20..bf58ae5d3535 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -60,6 +60,7 @@
> > #include "intel_bw.h"
> > #include "intel_cdclk.h"
> > #include "intel_clock_gating.h"
> > +#include "intel_cmtg.h"
> > #include "intel_color.h"
> > #include "intel_crt.h"
> > #include "intel_crtc.h"
> > @@ -2753,6 +2754,8 @@ static void intel_set_transcoder_timings(const
> struct intel_crtc_state *crtc_sta
> > intel_de_write(display,
> DP_MIN_HBLANK_CTL(cpu_transcoder),
> > crtc_state->min_hblank);
> > }
> > +
> > + intel_cmtg_set_timings(crtc_state, false);
> > }
> >
> > static void intel_set_transcoder_timings_lrr(const struct
> > intel_crtc_state *crtc_state) @@ -2814,6 +2817,7 @@ static void
> intel_set_transcoder_timings_lrr(const struct intel_crtc_state *crtc
> > VACTIVE(crtc_vdisplay - 1) |
> > VTOTAL(crtc_vtotal - 1));
> >
> > + intel_cmtg_set_timings(crtc_state, true);
> > intel_vrr_set_fixed_rr_timings(crtc_state);
> > intel_vrr_transcoder_enable(crtc_state);
> > }
>
> --
> Jani Nikula, Intel
next prev parent reply other threads:[~2026-04-17 6:03 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-04-12 10:36 [PATCH v4 00/13] CMTG enablement Animesh Manna
2026-04-12 10:37 ` [PATCH v4 01/13] drm/i915/cmtg: Add intel_cmtg_is_allowed() for CMTG Animesh Manna
2026-04-14 13:31 ` Jani Nikula
2026-04-12 10:37 ` [PATCH v4 02/13] drm/i915/cmtg: Set CMTG clock select Animesh Manna
2026-04-12 10:37 ` [PATCH v4 03/13] drm/i915/cmtg: Set timings for CMTG Animesh Manna
2026-04-14 13:33 ` Jani Nikula
2026-04-17 6:03 ` Manna, Animesh [this message]
2026-04-17 10:26 ` Ville Syrjälä
2026-04-23 4:37 ` Manna, Animesh
2026-04-23 4:55 ` Manna, Animesh
2026-04-23 10:51 ` Ville Syrjälä
2026-04-23 11:07 ` Manna, Animesh
2026-04-29 12:01 ` Ville Syrjälä
2026-04-30 7:16 ` Manna, Animesh
2026-04-12 10:37 ` [PATCH v4 04/13] drm/i915/cmtg: Program VRR registers of CMTG Animesh Manna
2026-04-12 10:37 ` [PATCH v4 05/13] drm/i915/cmtg: Set transcoder mn for CMTG Animesh Manna
2026-04-12 10:37 ` [PATCH v4 06/13] drm/i915/cmtg: Add hook to enable CMTG with sync to port Animesh Manna
2026-04-12 10:37 ` [PATCH v4 07/13] drm/i915/cmtg: Add a hook to make eDP transcoder secondary Animesh Manna
2026-04-12 10:37 ` [PATCH v4 08/13] drm/i915/cmtg: Split CMTG support check from intel_cmtg_is_allowed() Animesh Manna
2026-04-12 10:37 ` [PATCH v4 09/13] drm/i915/cmtg: Modify existing hook to disable CMTG Animesh Manna
2026-04-12 10:37 ` [PATCH v4 10/13] drm/i915/cmtg: Add trigger to enable/disable cmtg Animesh Manna
2026-04-12 10:37 ` [PATCH v4 11/13] drm/i915/cmtg: Add CMTG interrupt handling Animesh Manna
2026-04-12 10:37 ` [PATCH v4 12/13] drm/i915/cmtg: Disable CMTG if dc3co is not allowed Animesh Manna
2026-04-12 10:37 ` [PATCH v4 13/13] drm/i915/cmtg: Set target_dc_state flag for lobf/psr2/pr-alpm Animesh Manna
2026-04-13 12:19 ` Dibin Moolakadan Subrahmanian
2026-04-12 11:16 ` ✓ CI.KUnit: success for CMTG enablement (rev5) Patchwork
2026-04-12 12:05 ` ✓ Xe.CI.BAT: " Patchwork
2026-04-12 13:01 ` ✗ Xe.CI.FULL: failure " Patchwork
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