From: "Upadhyay, Tejas" <tejas.upadhyay@intel.com>
To: "Tauro, Riana" <riana.tauro@intel.com>,
"intel-xe@lists.freedesktop.org" <intel-xe@lists.freedesktop.org>
Cc: "Gupta, Anshuman" <anshuman.gupta@intel.com>,
"Vivi, Rodrigo" <rodrigo.vivi@intel.com>,
"aravind.iddamsetty@linux.intel.com"
<aravind.iddamsetty@linux.intel.com>,
"Nilawar, Badal" <badal.nilawar@intel.com>,
"Jadav, Raag" <raag.jadav@intel.com>,
"Koppuravuri, Ravi Kishore" <ravi.kishore.koppuravuri@intel.com>,
"Koujalagi, Mallesh" <mallesh.koujalagi@intel.com>,
"Purkait, Soham" <soham.purkait@intel.com>,
"Ghimiray, Himal Prasad" <himal.prasad.ghimiray@intel.com>
Subject: RE: [PATCH v4 09/13] drm/xe/xe_ras: Handle uncorrectable device memory errors
Date: Tue, 21 Apr 2026 06:08:58 +0000 [thread overview]
Message-ID: <SN6PR11MB3232AC3177251C7384108B53812C2@SN6PR11MB3232.namprd11.prod.outlook.com> (raw)
In-Reply-To: <20260417085812.4013309-24-riana.tauro@intel.com>
> -----Original Message-----
> From: Tauro, Riana <riana.tauro@intel.com>
> Sent: 17 April 2026 14:28
> To: intel-xe@lists.freedesktop.org
> Cc: Tauro, Riana <riana.tauro@intel.com>; Gupta, Anshuman
> <anshuman.gupta@intel.com>; Vivi, Rodrigo <rodrigo.vivi@intel.com>;
> aravind.iddamsetty@linux.intel.com; Nilawar, Badal
> <badal.nilawar@intel.com>; Jadav, Raag <raag.jadav@intel.com>;
> Koppuravuri, Ravi Kishore <ravi.kishore.koppuravuri@intel.com>; Koujalagi,
> Mallesh <mallesh.koujalagi@intel.com>; Purkait, Soham
> <soham.purkait@intel.com>; Upadhyay, Tejas <tejas.upadhyay@intel.com>;
> Ghimiray, Himal Prasad <himal.prasad.ghimiray@intel.com>
> Subject: [PATCH v4 09/13] drm/xe/xe_ras: Handle uncorrectable device
> memory errors
>
> Add support to handle uncorrectable device memory errors. Double bit ECC
> (Error Correcting Code) errors are logged. These will be handled using Page
> offlining in a later patch. The other memory error categories require a
> Secondary bus reset (SBR) to recover.
>
> Cc: Tejas Upadhyay <tejas.upadhyay@intel.com>
> Cc: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
> Signed-off-by: Riana Tauro <riana.tauro@intel.com>
> ---
> Memory offlining patch will be integrated once
> https://patchwork.freedesktop.org/series/161473/ is merged.
> ---
> drivers/gpu/drm/xe/xe_ras.c | 23 ++++++++++++
> drivers/gpu/drm/xe/xe_ras_types.h | 61
> +++++++++++++++++++++++++++++++
> 2 files changed, 84 insertions(+)
>
> diff --git a/drivers/gpu/drm/xe/xe_ras.c b/drivers/gpu/drm/xe/xe_ras.c index
> 5010cf6211ea..347844b3d2bf 100644
> --- a/drivers/gpu/drm/xe/xe_ras.c
> +++ b/drivers/gpu/drm/xe/xe_ras.c
> @@ -138,6 +138,26 @@ static enum xe_ras_recovery_action
> handle_soc_internal_errors(struct xe_device *
> return XE_RAS_RECOVERY_ACTION_RESET;
> }
>
> +static enum xe_ras_recovery_action handle_memory_errors(struct xe_device
> *xe,
> + struct
> xe_ras_error_array *arr)
> +{
> + struct xe_ras_memory_error *error_info = (struct
> xe_ras_memory_error *)arr->error_details;
> + struct xe_ras_error_category category = error_info->category;
> + struct xe_ras_error_common common = arr->error_class.common;
> +
> + xe_err(xe, "[RAS]: %s %s Error detected", severity_to_str(xe,
> common.severity),
> + comp_to_str(xe, common.component));
don't need \n?
> +
> + if (category.ecc_error) {
> + xe_err(xe, "[RAS]: Double bit ECC error detected at sw address
> 0x%llx\n",
> + (unsigned long long)error_info->sw_address);
> + /* TODO: page offline handling for 2-bit ECC errors and return
> accordingly */
> + }
> +
> + /* Request a RESET for other device memory error categories */
> + return XE_RAS_RECOVERY_ACTION_RESET;
> +}
> +
> static void prepare_sysctrl_command(struct xe_sysctrl_mailbox_command
> *command,
> u32 cmd_mask, void *request, size_t
> request_len,
> void *response, size_t response_len) @@ -
> 217,6 +237,9 @@ enum xe_ras_recovery_action xe_ras_process_errors(struct
> xe_device *xe)
> case XE_RAS_COMPONENT_SOC_INTERNAL:
> action = handle_soc_internal_errors(xe, &arr);
> break;
> + case XE_RAS_COMPONENT_DEVICE_MEMORY:
> + action = handle_memory_errors(xe, &arr);
> + break;
> default:
> xe_err(xe, "[RAS]: Unknown error component
> %u\n", component);
> action = XE_RAS_RECOVERY_ACTION_RESET;
> diff --git a/drivers/gpu/drm/xe/xe_ras_types.h
> b/drivers/gpu/drm/xe/xe_ras_types.h
> index 4f640124f38f..020e3f92a057 100644
> --- a/drivers/gpu/drm/xe/xe_ras_types.h
> +++ b/drivers/gpu/drm/xe/xe_ras_types.h
> @@ -199,4 +199,65 @@ struct xe_ras_ieh_error {
> /** @additional_info: Additional information */
> u32 additional_info[10];
> } __packed;
> +
> +/**
> + * struct xe_ras_hardware_address - Device memory hardware address
> +details
> + *
> + * Hardware physical address structure for device memory error reporting.
> + */
> +struct xe_ras_hardware_address {
> + /** @column: Column address */
> + u64 column:6;
> + /** @bank: Bank */
> + u64 bank:2;
> + /** @bank_group: Bank group */
> + u64 bank_group:2;
> + /** @row: Row address */
> + u64 row:16;
> + /** @channel: Memory Channel */
> + u64 channel:8;
> + /** @msu: MSU index */
> + u64 msu:8;
> + /** @reserved: Reserved for future use */
> + u64 reserved:22;
> +} __packed;
> +
> +/**
> + * struct xe_ras_error_category - Device memory error category details
> +*/ struct xe_ras_error_category {
> + /** @pma_error: PMA (Power Management Agent) error */
> + u8 pma_error:1;
> + /** @ecc_error: Double bit ECC error */
> + u8 ecc_error:1;
> + /** @poison_detected: Write poison detected */
> + u8 poison_detected:1;
> + /** @parity_error: Parity error */
> + u8 parity_error:1;
> + /** @phy_error: PHY error */
> + u8 phy_error:1;
> + /** @reserved: Reserved for future use */
> + u8 reserved:3;
> +} __packed;
> +
> +/**
> + * struct xe_ras_memory_error - Device memory error details
> + *
> + * This structure provides detailed information about a device memory error.
> + * Cast from error_details array for device memory errors.
> + */
> +struct xe_ras_memory_error {
> + /** @category: Device memory error category */
> + struct xe_ras_error_category category;
> + /** @reserved: Reserved for future use */
> + u8 reserved[7];
> + /** @hw_address: Memory hardware physical address */
> + struct xe_ras_hardware_address hw_address;
> + /** @sw_address: Software address where error occurred */
Introduced but not used, can be moved to next patch?
Tejas
> + u64 sw_address;
> + /** @log_array: Error syndromes associated with the error */
> + u32 log_array[8];
> + /** @reserved2: Reserved for future use */
> + u32 reserved2[2];
> +} __packed;
> #endif
> --
> 2.47.1
next prev parent reply other threads:[~2026-04-21 6:09 UTC|newest]
Thread overview: 45+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-04-17 8:58 [PATCH v4 00/13] Introduce Xe Uncorrectable Error Handling Riana Tauro
2026-04-17 8:58 ` [PATCH v4 01/13] drm/xe/xe_survivability: Decouple survivability info from boot survivability Riana Tauro
2026-04-17 8:58 ` [PATCH v4 02/13] drm/xe/xe_pci_error: Implement PCI error recovery callbacks Riana Tauro
2026-04-27 6:35 ` Raag Jadav
2026-05-06 13:59 ` Tauro, Riana
2026-04-17 8:58 ` [PATCH v4 03/13] drm/xe/xe_pci_error: Group all devres to release them on PCIe slot reset Riana Tauro
2026-04-17 8:58 ` [PATCH v4 04/13] drm/xe: Skip device access during PCI error recovery Riana Tauro
2026-04-30 12:58 ` Anshuman Gupta
2026-05-06 15:41 ` Tauro, Riana
2026-04-17 8:58 ` [PATCH v4 05/13] drm/xe/xe_ras: Initialize Uncorrectable AER Registers Riana Tauro
2026-04-27 7:56 ` Raag Jadav
2026-05-05 5:22 ` Tauro, Riana
2026-04-17 8:58 ` [PATCH v4 06/13] drm/xe/xe_ras: Add basic structures and commands for uncorrectable errors Riana Tauro
2026-04-17 17:38 ` Matt Roper
2026-04-17 21:25 ` Jadav, Raag
2026-04-17 21:32 ` Matt Roper
2026-04-20 5:34 ` Tauro, Riana
2026-04-20 7:49 ` Raag Jadav
2026-04-17 8:58 ` [PATCH v4 07/13] drm/xe/xe_ras: Add support for uncorrectable core-compute errors Riana Tauro
2026-04-27 8:24 ` Raag Jadav
2026-05-05 5:28 ` Tauro, Riana
2026-04-17 8:58 ` [PATCH v4 08/13] drm/xe/xe_ras: Handle uncorrectable SoC Internal errors Riana Tauro
2026-04-17 8:58 ` [PATCH v4 09/13] drm/xe/xe_ras: Handle uncorrectable device memory errors Riana Tauro
2026-04-21 6:08 ` Upadhyay, Tejas [this message]
2026-05-05 5:03 ` Tauro, Riana
2026-04-17 8:58 ` [PATCH v4 10/13] drm/xe/xe_ras: Add support to offline/decline a page Riana Tauro
2026-04-21 6:21 ` Upadhyay, Tejas
2026-05-05 5:16 ` Tauro, Riana
2026-04-17 8:58 ` [PATCH v4 11/13] drm/xe/xe_ras: Add support for page offline list and queue commands Riana Tauro
2026-04-21 6:19 ` Upadhyay, Tejas
2026-05-05 5:08 ` Tauro, Riana
2026-04-21 9:10 ` Upadhyay, Tejas
2026-05-05 5:17 ` Tauro, Riana
2026-04-17 8:58 ` [PATCH v4 12/13] drm/xe/xe_ras: Query errors from system controller on probe Riana Tauro
2026-04-28 11:46 ` Raag Jadav
2026-05-05 13:50 ` Tauro, Riana
2026-04-17 8:58 ` [PATCH v4 13/13] drm/xe/xe_pci_error: Process errors in mmio_enabled Riana Tauro
2026-04-28 11:39 ` Raag Jadav
2026-05-05 5:31 ` Tauro, Riana
2026-04-30 11:15 ` Gupta, Anshuman
2026-05-02 17:55 ` Raag Jadav
2026-04-20 13:33 ` ✗ CI.checkpatch: warning for Introduce Xe Uncorrectable Error Handling (rev4) Patchwork
2026-04-20 13:35 ` ✓ CI.KUnit: success " Patchwork
2026-04-20 14:42 ` ✓ Xe.CI.BAT: " Patchwork
2026-04-20 17:14 ` ✗ Xe.CI.FULL: failure " Patchwork
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=SN6PR11MB3232AC3177251C7384108B53812C2@SN6PR11MB3232.namprd11.prod.outlook.com \
--to=tejas.upadhyay@intel.com \
--cc=anshuman.gupta@intel.com \
--cc=aravind.iddamsetty@linux.intel.com \
--cc=badal.nilawar@intel.com \
--cc=himal.prasad.ghimiray@intel.com \
--cc=intel-xe@lists.freedesktop.org \
--cc=mallesh.koujalagi@intel.com \
--cc=raag.jadav@intel.com \
--cc=ravi.kishore.koppuravuri@intel.com \
--cc=riana.tauro@intel.com \
--cc=rodrigo.vivi@intel.com \
--cc=soham.purkait@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).