From: Tyler Baicar <baicar@os.amperecomputing.com>
To: patches@amperecomputing.com, abdulhamid@os.amperecomputing.com,
darren@os.amperecomputing.com, catalin.marinas@arm.com,
will@kernel.org, maz@kernel.org, james.morse@arm.com,
alexandru.elisei@arm.com, suzuki.poulose@arm.com,
lorenzo.pieralisi@arm.com, guohanjun@huawei.com,
sudeep.holla@arm.com, rafael@kernel.org, lenb@kernel.org,
tony.luck@intel.com, bp@alien8.de, mark.rutland@arm.com,
anshuman.khandual@arm.com, vincenzo.frascino@arm.com,
tabba@google.com, marcan@marcan.st, keescook@chromium.org,
jthierry@redhat.com, masahiroy@kernel.org,
samitolvanen@google.com, john.garry@huawei.com,
daniel.lezcano@linaro.org, gor@linux.ibm.com,
zhangshaokun@hisilicon.com, tmricht@linux.ibm.com,
dchinner@redhat.com, tglx@linutronix.de,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
kvmarm@lists.cs.columbia.edu, linux-acpi@vger.kernel.org,
linux-edac@vger.kernel.org, ishii.shuuichir@fujitsu.com,
Vineeth.Pillai@microsoft.com
Cc: Tyler Baicar <baicar@os.amperecomputing.com>
Subject: [PATCH 2/2] trace, ras: add ARM RAS extension trace event
Date: Wed, 24 Nov 2021 12:07:08 -0500 [thread overview]
Message-ID: <20211124170708.3874-3-baicar@os.amperecomputing.com> (raw)
In-Reply-To: <20211124170708.3874-1-baicar@os.amperecomputing.com>
Add a trace event for hardware errors reported by the ARMv8
RAS extension registers.
Signed-off-by: Tyler Baicar <baicar@os.amperecomputing.com>
---
arch/arm64/kernel/ras.c | 4 +++
drivers/acpi/arm64/aest.c | 5 ++++
include/ras/ras_event.h | 55 +++++++++++++++++++++++++++++++++++++++
3 files changed, 64 insertions(+)
diff --git a/arch/arm64/kernel/ras.c b/arch/arm64/kernel/ras.c
index 31e2036a4c70..18071790b2a3 100644
--- a/arch/arm64/kernel/ras.c
+++ b/arch/arm64/kernel/ras.c
@@ -6,6 +6,8 @@
#include <asm/cpufeature.h>
#include <asm/ras.h>
+#include <ras/ras_event.h>
+
static bool ras_extn_v1p1(void)
{
unsigned long fld, reg = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
@@ -95,6 +97,8 @@ void arch_arm_ras_report_error(u64 implemented, bool clear_misc)
arch_arm_ras_print_error(®s, i, misc23_present);
+ trace_arm_ras_ext_event(0, cpu_num, 0, i, ®s);
+
/*
* In the future, we will treat UER conditions as potentially
* recoverable.
diff --git a/drivers/acpi/arm64/aest.c b/drivers/acpi/arm64/aest.c
index 2df4f2377e51..7ef1750f91b3 100644
--- a/drivers/acpi/arm64/aest.c
+++ b/drivers/acpi/arm64/aest.c
@@ -14,6 +14,8 @@
#include <asm/ras.h>
+#include <ras/ras_event.h>
+
#undef pr_fmt
#define pr_fmt(fmt) "ACPI AEST: " fmt
@@ -126,6 +128,9 @@ static void aest_proc(struct aest_node_data *data)
aest_print(data, regs, i, misc23_present);
+ trace_arm_ras_ext_event(data->node_type, data->data.vendor.acpi_hid,
+ data->data.vendor.acpi_uid, i, ®s);
+
if (regs.err_status & ERR_STATUS_UE)
fatal = true;
diff --git a/include/ras/ras_event.h b/include/ras/ras_event.h
index 0bdbc0d17d2f..27b2be9f950d 100644
--- a/include/ras/ras_event.h
+++ b/include/ras/ras_event.h
@@ -338,6 +338,61 @@ TRACE_EVENT(aer_event,
"Not available")
);
+/*
+ * ARM RAS Extension Events Report
+ *
+ * This event is generated when an error reported by the ARM RAS extension
+ * hardware is detected.
+ */
+
+#ifdef CONFIG_ARM64_RAS_EXTN
+#include <asm/ras.h>
+TRACE_EVENT(arm_ras_ext_event,
+
+ TP_PROTO(u8 type, u32 id0, u32 id1, u32 index, struct ras_ext_regs *regs),
+
+ TP_ARGS(type, id0, id1, index, regs),
+
+ TP_STRUCT__entry(
+ __field(u8, type)
+ __field(u32, id0)
+ __field(u32, id1)
+ __field(u32, index)
+ __field(u64, err_fr)
+ __field(u64, err_ctlr)
+ __field(u64, err_status)
+ __field(u64, err_addr)
+ __field(u64, err_misc0)
+ __field(u64, err_misc1)
+ __field(u64, err_misc2)
+ __field(u64, err_misc3)
+ ),
+
+ TP_fast_assign(
+ __entry->type = type;
+ __entry->id0 = id0;
+ __entry->id1 = id1;
+ __entry->index = index;
+ __entry->err_fr = regs->err_fr;
+ __entry->err_ctlr = regs->err_ctlr;
+ __entry->err_status = regs->err_status;
+ __entry->err_addr = regs->err_addr;
+ __entry->err_misc0 = regs->err_misc0;
+ __entry->err_misc1 = regs->err_misc1;
+ __entry->err_misc2 = regs->err_misc2;
+ __entry->err_misc3 = regs->err_misc3;
+ ),
+
+ TP_printk("type: %d; id0: %d; id1: %d; index: %d; ERR_FR: %llx; ERR_CTLR: %llx; "
+ "ERR_STATUS: %llx; ERR_ADDR: %llx; ERR_MISC0: %llx; ERR_MISC1: %llx; "
+ "ERR_MISC2: %llx; ERR_MISC3: %llx",
+ __entry->type, __entry->id0, __entry->id1, __entry->index, __entry->err_fr,
+ __entry->err_ctlr, __entry->err_status, __entry->err_addr,
+ __entry->err_misc0, __entry->err_misc1, __entry->err_misc2,
+ __entry->err_misc3)
+);
+#endif
+
/*
* memory-failure recovery action result event
*
--
2.33.1
next prev parent reply other threads:[~2021-11-24 17:07 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-24 17:07 [PATCH 0/2] ARM Error Source Table Support Tyler Baicar
2021-11-24 17:07 ` [PATCH 1/2] ACPI/AEST: Initial AEST driver Tyler Baicar
2021-11-24 18:09 ` Marc Zyngier
2021-11-29 20:39 ` Darren Hart
2021-11-30 9:45 ` Marc Zyngier
2021-11-30 16:41 ` Darren Hart
2021-12-16 22:05 ` Tyler Baicar
2021-12-16 23:42 ` Sudeep Holla
2021-11-24 18:51 ` Mark Rutland
2021-12-16 23:22 ` Tyler Baicar
2021-12-09 8:10 ` ishii.shuuichir
2021-12-16 23:33 ` Tyler Baicar
2022-04-20 7:54 ` ishii.shuuichir
2022-05-09 13:37 ` Tyler Baicar
2022-05-09 23:23 ` ishii.shuuichir
2022-12-07 5:44 ` Ruidong Tian
2021-11-24 17:07 ` Tyler Baicar [this message]
-- strict thread matches above, loose matches on Subject: below --
2024-03-04 11:15 [PATCH 0/2] ARM Error Source Table V1 Support Ruidong Tian
2024-03-04 11:15 ` [PATCH 2/2] trace, ras: add ARM RAS extension trace event Ruidong Tian
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20211124170708.3874-3-baicar@os.amperecomputing.com \
--to=baicar@os.amperecomputing.com \
--cc=Vineeth.Pillai@microsoft.com \
--cc=abdulhamid@os.amperecomputing.com \
--cc=alexandru.elisei@arm.com \
--cc=anshuman.khandual@arm.com \
--cc=bp@alien8.de \
--cc=catalin.marinas@arm.com \
--cc=daniel.lezcano@linaro.org \
--cc=darren@os.amperecomputing.com \
--cc=dchinner@redhat.com \
--cc=gor@linux.ibm.com \
--cc=guohanjun@huawei.com \
--cc=ishii.shuuichir@fujitsu.com \
--cc=james.morse@arm.com \
--cc=john.garry@huawei.com \
--cc=jthierry@redhat.com \
--cc=keescook@chromium.org \
--cc=kvmarm@lists.cs.columbia.edu \
--cc=lenb@kernel.org \
--cc=linux-acpi@vger.kernel.org \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-edac@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=lorenzo.pieralisi@arm.com \
--cc=marcan@marcan.st \
--cc=mark.rutland@arm.com \
--cc=masahiroy@kernel.org \
--cc=maz@kernel.org \
--cc=patches@amperecomputing.com \
--cc=rafael@kernel.org \
--cc=samitolvanen@google.com \
--cc=sudeep.holla@arm.com \
--cc=suzuki.poulose@arm.com \
--cc=tabba@google.com \
--cc=tglx@linutronix.de \
--cc=tmricht@linux.ibm.com \
--cc=tony.luck@intel.com \
--cc=vincenzo.frascino@arm.com \
--cc=will@kernel.org \
--cc=zhangshaokun@hisilicon.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).