From: Sunil V L <sunilvl@ventanamicro.com>
To: linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
linux-acpi@vger.kernel.org, linux-pci@vger.kernel.org,
acpica-devel@lists.linux.dev
Cc: "Catalin Marinas" <catalin.marinas@arm.com>,
"Will Deacon" <will@kernel.org>,
"Paul Walmsley" <paul.walmsley@sifive.com>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Albert Ou" <aou@eecs.berkeley.edu>,
"Rafael J . Wysocki" <rafael@kernel.org>,
"Len Brown" <lenb@kernel.org>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Anup Patel" <anup@brainfault.org>,
"Thomas Gleixner" <tglx@linutronix.de>,
"Samuel Holland" <samuel.holland@sifive.com>,
"Robert Moore" <robert.moore@intel.com>,
"Haibo1 Xu" <haibo1.xu@intel.com>,
"Conor Dooley" <conor.dooley@microchip.com>,
"Andrew Jones" <ajones@ventanamicro.com>,
"Atish Kumar Patra" <atishp@rivosinc.com>,
"Andrei Warkentin" <andrei.warkentin@intel.com>,
"Marc Zyngier" <maz@kernel.org>, "Björn Töpel" <bjorn@kernel.org>,
"Sunil V L" <sunilvl@ventanamicro.com>
Subject: [RFC PATCH v4 05/20] ACPI: RISC-V: Implement arch function to reorder irqchip probe entries
Date: Mon, 15 Apr 2024 22:30:58 +0530 [thread overview]
Message-ID: <20240415170113.662318-6-sunilvl@ventanamicro.com> (raw)
In-Reply-To: <20240415170113.662318-1-sunilvl@ventanamicro.com>
ACPI MADT entries for interrupt controllers don't have a way to describe
the hierarchy. However, the hierarchy is known to the architecture and
on RISC-V platforms, the MADT sub table types are ordered in the
incremental order from the root controller which is RINTC. So, add
architecture function for RISC-V to reorder the interrupt controller
probing as per the hierarchy as below.
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
---
drivers/acpi/riscv/Makefile | 2 +-
drivers/acpi/riscv/irq.c | 32 ++++++++++++++++++++++++++++++++
2 files changed, 33 insertions(+), 1 deletion(-)
create mode 100644 drivers/acpi/riscv/irq.c
diff --git a/drivers/acpi/riscv/Makefile b/drivers/acpi/riscv/Makefile
index 86b0925f612d..dceec808cfab 100644
--- a/drivers/acpi/riscv/Makefile
+++ b/drivers/acpi/riscv/Makefile
@@ -1,4 +1,4 @@
# SPDX-License-Identifier: GPL-2.0-only
-obj-y += rhct.o
+obj-y += rhct.o irq.o
obj-$(CONFIG_ACPI_PROCESSOR_IDLE) += cpuidle.o
obj-$(CONFIG_ACPI_CPPC_LIB) += cppc.o
diff --git a/drivers/acpi/riscv/irq.c b/drivers/acpi/riscv/irq.c
new file mode 100644
index 000000000000..36e0525b3235
--- /dev/null
+++ b/drivers/acpi/riscv/irq.c
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2023, Ventana Micro Systems Inc
+ * Author: Sunil V L <sunilvl@ventanamicro.com>
+ *
+ */
+
+#include <linux/acpi.h>
+#include <linux/sort.h>
+
+static int irqchip_cmp_func(const void *in0, const void *in1)
+{
+ struct acpi_probe_entry *elem0 = (struct acpi_probe_entry *)in0;
+ struct acpi_probe_entry *elem1 = (struct acpi_probe_entry *)in1;
+
+ return (elem0->type > elem1->type) - (elem0->type < elem1->type);
+}
+
+/*
+ * RISC-V irqchips in MADT of ACPI spec are defined in the same order how
+ * they should be probed. Since IRQCHIP_ACPI_DECLARE doesn't define any
+ * order, this arch function will reorder the probe functions as per the
+ * required order for the architecture.
+ */
+void arch_sort_irqchip_probe(struct acpi_probe_entry *ap_head, int nr)
+{
+ struct acpi_probe_entry *ape = ap_head;
+
+ if (nr == 1 || !ACPI_COMPARE_NAMESEG(ACPI_SIG_MADT, ape->id))
+ return;
+ sort(ape, nr, sizeof(*ape), irqchip_cmp_func, NULL);
+}
--
2.40.1
next prev parent reply other threads:[~2024-04-15 17:01 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-15 17:00 [RFC PATCH v4 00/20] RISC-V: ACPI: Add external interrupt controller support Sunil V L
2024-04-15 17:00 ` [RFC PATCH v4 01/20] arm64: PCI: Migrate ACPI related functions to pci-acpi.c Sunil V L
2024-04-15 17:00 ` [RFC PATCH v4 02/20] RISC-V: ACPI: Implement PCI related functionality Sunil V L
2024-04-15 17:00 ` [RFC PATCH v4 03/20] PCI: Make pci_create_root_bus() declare its reliance on MSI domains Sunil V L
2024-04-15 23:15 ` Bjorn Helgaas
2024-04-16 8:24 ` Sunil V L
2024-04-16 20:46 ` Bjorn Helgaas
2024-04-17 15:33 ` Sunil V L
2024-04-18 11:45 ` Sunil V L
2024-04-15 17:00 ` [RFC PATCH v4 04/20] ACPI: scan.c: Add weak arch specific function to reorder the IRQCHIP probe Sunil V L
2024-04-15 17:00 ` Sunil V L [this message]
2024-04-15 17:00 ` [RFC PATCH v4 06/20] ACPI: bus: Add acpi_riscv_init function Sunil V L
2024-04-15 17:01 ` [RFC PATCH v4 07/20] RISC-V: Kconfig: Select deferred GSI probe for ACPI systems Sunil V L
2024-04-15 17:01 ` [RFC PATCH v4 08/20] ACPI: scan: Refactor dependency creation Sunil V L
2024-04-15 17:01 ` [RFC PATCH v4 09/20] drivers/acpi/scan.c: Update _DEP honor list Sunil V L
2024-04-15 17:01 ` [RFC PATCH v4 10/20] RISC-V: ACPI: Initialize GSI mapping structures Sunil V L
2024-04-15 17:01 ` [RFC PATCH v4 11/20] ACPI: scan.c: Define weak function to populate dependencies Sunil V L
2024-04-15 17:01 ` [RFC PATCH v4 12/20] RISC-V: ACPI: Implement function to add implicit dependencies Sunil V L
2024-04-15 17:01 ` [RFC PATCH v4 13/20] ACPI/PNP: Initialize PNP devices skipped due to _DEP Sunil V L
2024-04-15 17:01 ` [RFC PATCH v4 14/20] irqchip: riscv-intc: Add ACPI support for AIA Sunil V L
2024-04-15 17:01 ` [RFC PATCH v4 15/20] irqchip: riscv-imsic: Add ACPI support Sunil V L
2024-04-15 17:01 ` [RFC PATCH v4 16/20] irqchip: riscv-aplic: " Sunil V L
2024-04-15 17:01 ` [RFC PATCH v4 17/20] irqchip: irq-sifive-plic: " Sunil V L
2024-04-15 17:01 ` [RFC PATCH v4 18/20] ACPI: bus: Add RINTC IRQ model for RISC-V Sunil V L
2024-04-15 17:01 ` [RFC PATCH v4 19/20] irqchip: riscv-intc: Set ACPI irqmodel Sunil V L
2024-04-15 17:01 ` [RFC PATCH v4 20/20] ACPI: pci_link: Clear the dependencies after probe Sunil V L
2024-04-18 13:49 ` [RFC PATCH v4 00/20] RISC-V: ACPI: Add external interrupt controller support Björn Töpel
2024-04-18 13:58 ` Sunil V L
2024-04-18 14:20 ` Heinrich Schuchardt
2024-04-22 19:28 ` Rafael J. Wysocki
2024-04-24 17:55 ` Björn Töpel
2024-04-29 6:41 ` Sunil V L
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