From: yunhui cui <cuiyunhui@bytedance.com>
To: Sunil V L <sunilvl@ventanamicro.com>
Cc: rafael@kernel.org, lenb@kernel.org, linux-acpi@vger.kernel.org,
linux-kernel@vger.kernel.org, paul.walmsley@sifive.com,
palmer@dabbelt.com, aou@eecs.berkeley.edu,
linux-riscv@lists.infradead.org, bhelgaas@google.com,
james.morse@arm.com, jhugo@codeaurora.org,
jeremy.linton@arm.com, john.garry@huawei.com,
Jonathan.Cameron@huawei.com, pierre.gondois@arm.com,
sudeep.holla@arm.com, tiantao6@huawei.com
Subject: Re: [External] Re: [PATCH v4 2/3] riscv: cacheinfo: initialize cacheinfo's level and type from ACPI PPTT
Date: Thu, 9 May 2024 14:33:04 +0800 [thread overview]
Message-ID: <CAEEQ3wkTR7BcnOn_iMzmj2_NejeaY=RymoUyu27A8TrXdHtQ9A@mail.gmail.com> (raw)
In-Reply-To: <ZjxMfQOqc8ML8nrD@sunil-laptop>
Hi Sunil,
On Thu, May 9, 2024 at 12:09 PM Sunil V L <sunilvl@ventanamicro.com> wrote:
>
> On Thu, Apr 18, 2024 at 11:43:29AM +0800, Yunhui Cui wrote:
> > Before cacheinfo can be built correctly, we need to initialize level
> > and type. Since RSIC-V currently does not have a register group that
>
> NIT: Typo RISC-V
Okay, I'll update it in v5.
>
> > describes cache-related attributes like ARM64, we cannot obtain them
> > directly, so now we obtain cache leaves from the ACPI PPTT table
> > (acpi_get_cache_info()) and set the cache type through split_levels.
> >
> > Suggested-by: Jeremy Linton <jeremy.linton@arm.com>
> > Suggested-by: Sudeep Holla <sudeep.holla@arm.com>
> > Signed-off-by: Yunhui Cui <cuiyunhui@bytedance.com>
> > ---
> > arch/riscv/kernel/cacheinfo.c | 22 ++++++++++++++++++++++
> > 1 file changed, 22 insertions(+)
> >
> > diff --git a/arch/riscv/kernel/cacheinfo.c b/arch/riscv/kernel/cacheinfo.c
> > index 30a6878287ad..e47a1e6bd3fe 100644
> > --- a/arch/riscv/kernel/cacheinfo.c
> > +++ b/arch/riscv/kernel/cacheinfo.c
> > @@ -6,6 +6,7 @@
> > #include <linux/cpu.h>
> > #include <linux/of.h>
> > #include <asm/cacheinfo.h>
> > +#include <linux/acpi.h>
> >
> Can this be added in the order? Like, include acpi.h prior to cpu.h?
Okay, I'll update it in v5.
>
> > static struct riscv_cacheinfo_ops *rv_cache_ops;
> >
> > @@ -78,6 +79,27 @@ int populate_cache_leaves(unsigned int cpu)
> > struct device_node *prev = NULL;
> > int levels = 1, level = 1;
> >
> > + if (!acpi_disabled) {
> > + int ret, fw_levels, split_levels;
> > +
> > + ret = acpi_get_cache_info(cpu, &fw_levels, &split_levels);
> > + if (ret)
> > + return ret;
> > +
> > + BUG_ON((split_levels > fw_levels) ||
> > + (split_levels + fw_levels > this_cpu_ci->num_leaves));
> > +
> > + for (; level <= this_cpu_ci->num_levels; level++) {
> > + if (level <= split_levels) {
> > + ci_leaf_init(this_leaf++, CACHE_TYPE_DATA, level);
> > + ci_leaf_init(this_leaf++, CACHE_TYPE_INST, level);
> > + } else {
> > + ci_leaf_init(this_leaf++, CACHE_TYPE_UNIFIED, level);
> > + }
> > + }
> > + return 0;
> > + }
> > +
> Other than above nits, it looks good to me. Thanks for the patch!
>
> Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
Thanks,
Yunhui
next prev parent reply other threads:[~2024-05-09 6:33 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-18 3:43 [PATCH v4 1/3] riscv: cacheinfo: remove the useless input parameter (node) of ci_leaf_init() Yunhui Cui
2024-04-18 3:43 ` [PATCH v4 2/3] riscv: cacheinfo: initialize cacheinfo's level and type from ACPI PPTT Yunhui Cui
2024-04-18 8:41 ` Sudeep Holla
2024-04-19 6:27 ` [External] " yunhui cui
2024-04-19 15:28 ` Jeremy Linton
2024-04-23 11:03 ` [External] " yunhui cui
2024-04-30 3:16 ` yunhui cui
2024-05-02 16:37 ` Conor Dooley
2024-05-08 11:19 ` [External] " yunhui cui
2024-05-08 14:53 ` Palmer Dabbelt
2024-05-09 4:09 ` Sunil V L
2024-05-09 6:33 ` yunhui cui [this message]
2024-04-18 3:43 ` [PATCH v4 3/3] RISC-V: Select ACPI PPTT drivers Yunhui Cui
2024-05-02 16:28 ` [PATCH v4 1/3] riscv: cacheinfo: remove the useless input parameter (node) of ci_leaf_init() Conor Dooley
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