From: Rob Herring <robh@kernel.org>
To: Robin Murphy <robin.murphy@arm.com>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
James Morse <james.morse@arm.com>,
Jeremy Linton <jeremy.linton@arm.com>,
linux-arm-kernel <linux-arm-kernel@lists.infradead.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
Sudeep Holla <sudeep.holla@arm.com>,
"Rafael J. Wysocki" <rafael@kernel.org>,
Len Brown <lenb@kernel.org>,
devicetree@vger.kernel.org,
"open list:ACPI FOR ARM64 (ACPI/arm64)"
<linux-acpi@vger.kernel.org>
Subject: Re: [PATCH 2/6] cacheinfo: Set cache 'id' based on DT data
Date: Fri, 17 Dec 2021 13:35:27 -0600 [thread overview]
Message-ID: <CAL_JsqJM=dDxqEnnwbRLiemLS0XUqEe6RBZViLem8qoiDbPPjw@mail.gmail.com> (raw)
In-Reply-To: <836fd983-463c-040d-beb3-fee3faf215d6@arm.com>
On Fri, Dec 17, 2021 at 1:08 PM Robin Murphy <robin.murphy@arm.com> wrote:
>
> On 2021-12-17 18:14, Rob Herring wrote:
> > On Fri, Dec 17, 2021 at 10:57 AM Robin Murphy <robin.murphy@arm.com> wrote:
> >>
> >> Hi Rob,
> >>
> >> On 2021-12-16 23:31, Rob Herring wrote:
> >>> Use the minimum CPU h/w id of the CPUs associated with the cache for the
> >>> cache 'id'. This will provide a stable id value for a given system. As
> >>> we need to check all possible CPUs, we can't use the shared_cpu_map
> >>> which is just online CPUs. There's not a cache to CPUs mapping in DT, so
> >>> we have to walk all CPU nodes and then walk cache levels.
> >>
> >> I believe another expected use of the cache ID exposed in sysfs is to
> >> program steering tags for cache stashing (typically in VFIO-based
> >> userspace drivers like DPDK so we can't realistically mediate it any
> >> other way). There were plans afoot last year to ensure that ACPI PPTT
> >> could provide the necessary ID values for arm64 systems which will
> >> typically be fairly arbitrary (but unique) due to reflecting underlying
> >> interconnect routing IDs. Assuming that there will eventually be some
> >> interest in cache stashing on DT-based systems too, we probably want to
> >> allow for an explicit ID property on DT cache nodes in a similar manner.
> >
> > If you have a suggestion for ID values that correspond to the h/w,
> > then we can add them. I'd like a bit more than just trusting that ID
> > is something real.
> >
> > While the ACPI folks may be willing to take an arbitrary index, it's
> > something we (mostly) avoid for DT.
>
> Not really. On the CHI side there are two fields - StashNID, which could
> be any node ID value depending on the interconnect layout, plus
> (optionally) StashLPID to address a specific cache within that node if
> it's something like a CPU cluster. However, how a PCIe TLP steering tag
> translates to those fields in the resulting CHI flit is largely up to
> the root complex.
Knowing next to nothing about CHI, this means pretty much nothing to me. :(
I would guess there is a bit more to supporting CHI in DT systems than
just a cache ID.
> I think it's going to be more like a "reg" property than a nice
> validatable index.
>
> >> That said, I think it does make sense to have some kind of
> >> auto-generated fallback scheme *as well*, since I'm sure there will be
> >> plenty systems which care about MPAM but don't support stashing, and
> >> therefore wouldn't have a meaningful set of IDs to populate their DT
> >> with. Conversely I think that might also matter for ACPI too - one point
> >> I remember from previous discussions is that PPTT may use a compact
> >> representation where a single entry represents all equivalent caches at
> >> that level, so I'm not sure we can necessarily rely on IDs out of that
> >> path being unique either.
> >
> > AIUI, cache ids break the compact representation.
>
> Right, firmware authors can't use it if they do want to specify IDs, but
> that also means that if we find we *are* consuming a compact PPTT, then
> chances are we're not getting meaningful IDs out of it for MPAM to rely on.
Sounds like broken firmware is in our future. ;) Or ACPI can default
to the same id scheme.
Rob
next prev parent reply other threads:[~2021-12-17 19:35 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-12-16 23:31 [PATCH 0/6] cacheinfo: CPU affinity and Devicetree 'id' support Rob Herring
2021-12-16 23:31 ` [PATCH 1/6] cacheinfo: Allow for >32-bit cache 'id' Rob Herring
2021-12-16 23:31 ` [PATCH 2/6] cacheinfo: Set cache 'id' based on DT data Rob Herring
2021-12-17 16:57 ` Robin Murphy
2021-12-17 18:14 ` Rob Herring
2021-12-17 19:03 ` Sudeep Holla
2021-12-17 19:08 ` Sudeep Holla
2021-12-17 19:26 ` Rob Herring
2021-12-17 20:28 ` Jeremy Linton
2021-12-17 19:08 ` Robin Murphy
2021-12-17 19:35 ` Rob Herring [this message]
2021-12-17 20:22 ` Jeremy Linton
2021-12-17 21:13 ` Robin Murphy
2021-12-16 23:31 ` [PATCH 3/6] cacheinfo: Add cpu_affinity_map to store affinity for all CPUs Rob Herring
2021-12-16 23:31 ` [PATCH 4/6] ACPI / PPTT: Populate the cacheinfo.cpu_affinity_map Rob Herring
2021-12-16 23:31 ` [PATCH 5/6] cacheinfo: Use cpu_affinity_map for populating shared_cpu_map Rob Herring
2021-12-16 23:31 ` [PATCH 6/6] cacheinfo: Add cacheinfo_get_cache_affinity() function Rob Herring
2021-12-21 9:31 ` [PATCH 0/6] cacheinfo: CPU affinity and Devicetree 'id' support Greg Kroah-Hartman
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