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From: "Maciej W. Rozycki" <macro@orcam.me.uk>
To: "Paul E. McKenney" <paulmck@kernel.org>
Cc: John Paul Adrian Glaubitz <glaubitz@physik.fu-berlin.de>,
	 Arnd Bergmann <arnd@kernel.org>,
	linux-alpha@vger.kernel.org,  Arnd Bergmann <arnd@arndb.de>,
	 Richard Henderson <richard.henderson@linaro.org>,
	 Ivan Kokshaysky <ink@jurassic.park.msu.ru>,
	 Matt Turner <mattst88@gmail.com>,
	Alexander Viro <viro@zeniv.linux.org.uk>,
	 Marc Zyngier <maz@kernel.org>,
	 Linus Torvalds <torvalds@linux-foundation.org>,
	 linux-kernel@vger.kernel.org, Michael Cree <mcree@orcon.net.nz>,
	 Frank Scheiner <frank.scheiner@web.de>
Subject: Re: [PATCH 00/14] alpha: cleanups for 6.10
Date: Fri, 31 May 2024 04:56:28 +0100 (BST)	[thread overview]
Message-ID: <alpine.DEB.2.21.2405310432190.23854@angie.orcam.me.uk> (raw)
In-Reply-To: <5567ab2e-80af-4c5f-bebb-d979e8a34f49@paulmck-laptop>

On Wed, 29 May 2024, Paul E. McKenney wrote:

> >  Mind that the read-modify-write sequence that software does for sub-word 
> > write accesses with original Alpha hardware is precisely what hardware 
> > would have to do anyway and support for that was deliberately omitted by 
> > the architecture designers from the ISA to give it performance advantages 
> > quoted in the architecture manual.  The only difference here is that with 
> > hardware read-modify-write operations atomicity for sub-word accesses is 
> > guaranteed by the ISA, however for software read-modify-write it has to be 
> > explictly coded using the usual load-locked/store-conditional sequence in 
> > a loop.  I don't think it's a big deal really, it should be trivial to do 
> > in the relevant accessors, along with the memory barriers that are needed 
> > anyway for EV56+ and possibly other ports such as the MIPS one.
> 
> There shouldn't be any memory barriers required, and don't EV56+ have
> single-byte loads and stores?

 I should have commented on this in my original reply.

 You're the RCU expert so you know the answer.  I don't.  If it's OK for
successive writes to get reordered, or readers to see a stale value, then 
you don't need memory barriers.  Otherwise you do.  Whether byte accesses 
are available or not does not matter, the CPU *will* do reordering if it's 
allowed to (or more specifically, it won't do anything to prevent it from 
happening, especially in SMP configurations; I can't remember offhand if 
there are cases with UP).  Also adjacent byte writes may be merged, but I 
suppose it does not matter, or does it?

 NB MIPS has similar architectural arrangements (and a bunch of barriers 
defined in the ISA), it's just most implementations are actually strongly 
ordered, so most people can't see the effects of this.  With MIPS I know 
for sure there are cases of UP reordering, but they only really matter for 
MMIO use cases and not regular memory.

  Maciej

  parent reply	other threads:[~2024-05-31  3:56 UTC|newest]

Thread overview: 56+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-05-03  8:11 [PATCH 00/14] alpha: cleanups for 6.10 Arnd Bergmann
2024-05-03  8:11 ` [PATCH 01/14] alpha: sort scr_mem{cpy,move}w() out Arnd Bergmann
2024-05-03  8:11 ` [PATCH 02/14] alpha: fix modversions for strcpy() et.al Arnd Bergmann
2024-05-03  8:11 ` [PATCH 03/14] alpha: add clone3() support Arnd Bergmann
2024-05-03  8:11 ` [PATCH 04/14] alpha: don't make functions public without a reason Arnd Bergmann
2024-05-03  8:11 ` [PATCH 05/14] alpha: sys_sio: fix misspelled ifdefs Arnd Bergmann
2024-05-03  8:11 ` [PATCH 06/14] alpha: missing includes Arnd Bergmann
2024-05-03  8:11 ` [PATCH 07/14] alpha: core_lca: take the unused functions out Arnd Bergmann
2024-05-03  8:11 ` [PATCH 08/14] alpha: jensen, t2 - make __EXTERN_INLINE same as for the rest Arnd Bergmann
2024-05-03  8:11 ` [PATCH 09/14] alpha: trim the unused stuff from asm-offsets.c Arnd Bergmann
2024-05-03  8:11 ` [PATCH 10/14] alpha: remove DECpc AXP150 (Jensen) support Arnd Bergmann
2024-05-03 16:07   ` Linus Torvalds
2024-05-03 17:00   ` Al Viro
2024-05-03 20:07     ` Arnd Bergmann
2024-05-03  8:11 ` [PATCH 11/14] alpha: sable: remove early machine support Arnd Bergmann
2024-05-03  8:11 ` [PATCH 12/14] alpha: remove LCA and APECS based machines Arnd Bergmann
2024-05-03  8:11 ` [PATCH 13/14] alpha: cabriolet: remove EV5 CPU support Arnd Bergmann
2024-05-03  8:11 ` [PATCH 14/14] alpha: drop pre-EV56 support Arnd Bergmann
2024-05-04 15:00   ` Richard Henderson
2024-05-06 10:06     ` Arnd Bergmann
2024-06-03  6:02   ` Jiri Slaby
2024-06-04 13:58     ` Greg KH
2024-05-03 16:06 ` [PATCH 00/14] alpha: cleanups for 6.10 Matt Turner
2024-05-03 20:15   ` Arnd Bergmann
2024-05-06  9:16     ` Michael Cree
2024-05-06 10:11       ` Arnd Bergmann
2024-05-03 16:53 ` John Paul Adrian Glaubitz
2024-05-03 17:19   ` Paul E. McKenney
2024-05-27 23:49   ` Maciej W. Rozycki
2024-05-28 14:43     ` Paul E. McKenney
2024-05-29 18:50       ` Maciej W. Rozycki
2024-05-29 22:09         ` Paul E. McKenney
2024-05-30 22:59           ` Maciej W. Rozycki
2024-05-31  3:56           ` Maciej W. Rozycki [this message]
2024-05-31 19:33             ` Paul E. McKenney
2024-06-03 16:22               ` Maciej W. Rozycki
2024-06-03 17:08                 ` Paul E. McKenney
2024-07-01 23:50                   ` Maciej W. Rozycki
2024-05-30  1:08         ` Linus Torvalds
2024-05-30 22:57           ` Maciej W. Rozycki
2024-05-31  0:10             ` Linus Torvalds
2024-06-03 11:09               ` Maciej W. Rozycki
2024-06-03 11:36                 ` John Paul Adrian Glaubitz
2024-06-03 16:57                 ` Linus Torvalds
2024-07-01 23:48                   ` Maciej W. Rozycki
2024-11-19 17:54                     ` Maciej W. Rozycki
2024-05-31 15:48         ` Arnd Bergmann
2024-05-31 16:32           ` Linus Torvalds
2024-05-31 16:54             ` Arnd Bergmann
2024-06-01 13:51             ` David Laight
2024-07-01 23:48             ` Maciej W. Rozycki
2024-07-02  1:13               ` Linus Torvalds
2024-07-03  0:12                 ` Maciej W. Rozycki
2024-07-03  0:50                   ` Linus Torvalds
2024-07-04 22:21                     ` Maciej W. Rozycki
2024-06-03 11:33           ` Maciej W. Rozycki

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