From: Huacai Chen <chenhuacai@loongson.cn>
To: Arnd Bergmann <arnd@arndb.de>, Andy Lutomirski <luto@kernel.org>,
Thomas Gleixner <tglx@linutronix.de>,
Peter Zijlstra <peterz@infradead.org>,
Andrew Morton <akpm@linux-foundation.org>,
David Airlie <airlied@linux.ie>, Jonathan Corbet <corbet@lwn.net>,
Linus Torvalds <torvalds@linux-foundation.org>
Cc: linux-arch@vger.kernel.org, linux-doc@vger.kernel.org,
linux-kernel@vger.kernel.org, Xuefeng Li <lixuefeng@loongson.cn>,
Yanteng Si <siyanteng@loongson.cn>,
Huacai Chen <chenhuacai@gmail.com>,
Jiaxun Yang <jiaxun.yang@flygoat.com>,
Huacai Chen <chenhuacai@loongson.cn>
Subject: [PATCH V5 04/22] LoongArch: Add writecombine support for drm
Date: Wed, 13 Oct 2021 14:36:38 +0800 [thread overview]
Message-ID: <20211013063656.3084555-5-chenhuacai@loongson.cn> (raw)
In-Reply-To: <20211013063656.3084555-1-chenhuacai@loongson.cn>
LoongArch maintains cache coherency in hardware, but its WUC attribute
(Weak-ordered UnCached, which is similar to WC) is out of the scope of
cache coherency machanism. This means WUC can only used for write-only
memory regions.
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
---
drivers/gpu/drm/drm_vm.c | 2 +-
drivers/gpu/drm/ttm/ttm_module.c | 2 +-
include/drm/drm_cache.h | 8 ++++++++
3 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/drm_vm.c b/drivers/gpu/drm/drm_vm.c
index e957d4851dc0..f024dc93939e 100644
--- a/drivers/gpu/drm/drm_vm.c
+++ b/drivers/gpu/drm/drm_vm.c
@@ -69,7 +69,7 @@ static pgprot_t drm_io_prot(struct drm_local_map *map,
pgprot_t tmp = vm_get_page_prot(vma->vm_flags);
#if defined(__i386__) || defined(__x86_64__) || defined(__powerpc__) || \
- defined(__mips__)
+ defined(__mips__) || defined(__loongarch__)
if (map->type == _DRM_REGISTERS && !(map->flags & _DRM_WRITE_COMBINING))
tmp = pgprot_noncached(tmp);
else
diff --git a/drivers/gpu/drm/ttm/ttm_module.c b/drivers/gpu/drm/ttm/ttm_module.c
index 7fcdef278c74..3dc43390e76b 100644
--- a/drivers/gpu/drm/ttm/ttm_module.c
+++ b/drivers/gpu/drm/ttm/ttm_module.c
@@ -60,7 +60,7 @@ pgprot_t ttm_prot_from_caching(enum ttm_caching caching, pgprot_t tmp)
tmp = pgprot_noncached(tmp);
#endif
#if defined(__ia64__) || defined(__arm__) || defined(__aarch64__) || \
- defined(__powerpc__) || defined(__mips__)
+ defined(__powerpc__) || defined(__mips__) || defined(__loongarch__)
if (caching == ttm_write_combined)
tmp = pgprot_writecombine(tmp);
else
diff --git a/include/drm/drm_cache.h b/include/drm/drm_cache.h
index cc9de1632dd3..5c1059435369 100644
--- a/include/drm/drm_cache.h
+++ b/include/drm/drm_cache.h
@@ -67,6 +67,14 @@ static inline bool drm_arch_can_wc_memory(void)
* optimization entirely for ARM and arm64.
*/
return false;
+#elif defined(CONFIG_LOONGARCH)
+ /*
+ * LoongArch maintains cache coherency in hardware, but its WUC attribute
+ * (Weak-ordered UnCached, which is similar to WC) is out of the scope of
+ * cache coherency machanism. This means WUC can only used for write-only
+ * memory regions.
+ */
+ return false;
#else
return true;
#endif
--
2.27.0
next prev parent reply other threads:[~2021-10-13 6:41 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-13 6:36 [PATCH V5 00/22] arch: Add basic LoongArch support Huacai Chen
2021-10-13 6:36 ` [PATCH V5 01/22] Documentation: LoongArch: Add basic documentations Huacai Chen
2021-10-13 6:36 ` [PATCH V5 02/22] Documentation/zh_CN: Add basic LoongArch documentations Huacai Chen
2021-10-13 6:36 ` [PATCH V5 03/22] LoongArch: Add elf-related definitions Huacai Chen
2021-10-13 6:36 ` Huacai Chen [this message]
2021-10-13 6:36 ` [PATCH V5 05/22] LoongArch: Add build infrastructure Huacai Chen
2021-10-13 6:36 ` [PATCH V5 06/22] LoongArch: Add CPU definition headers Huacai Chen
2021-10-13 6:36 ` [PATCH V5 07/22] LoongArch: Add atomic/locking headers Huacai Chen
2021-10-13 6:36 ` [PATCH V5 08/22] LoongArch: Add other common headers Huacai Chen
2021-10-13 6:36 ` [PATCH V5 09/22] LoongArch: Add boot and setup routines Huacai Chen
2021-10-13 6:36 ` [PATCH V5 10/22] LoongArch: Add exception/interrupt handling Huacai Chen
2021-10-13 6:36 ` [PATCH V5 11/22] LoongArch: Add process management Huacai Chen
2021-10-13 6:36 ` [PATCH V5 12/22] LoongArch: Add memory management Huacai Chen
2021-10-13 6:36 ` [PATCH V5 13/22] LoongArch: Add system call support Huacai Chen
2021-10-13 7:11 ` [PATCH V5 14/22] LoongArch: Add signal handling support Huacai Chen
2021-10-13 7:11 ` [PATCH V5 15/22] LoongArch: Add elf and module support Huacai Chen
2021-10-13 12:56 ` Luis Chamberlain
2021-10-14 3:01 ` Huacai Chen
2021-10-13 7:11 ` [PATCH V5 16/22] LoongArch: Add misc common routines Huacai Chen
2021-10-13 7:11 ` [PATCH V5 17/22] LoongArch: Add some library functions Huacai Chen
2021-10-13 7:11 ` [PATCH V5 18/22] LoongArch: Add PCI controller support Huacai Chen
2021-10-13 7:11 ` [PATCH V5 19/22] LoongArch: Add VDSO and VSYSCALL support Huacai Chen
2021-10-13 7:11 ` [PATCH V5 20/22] LoongArch: Add multi-processor (SMP) support Huacai Chen
2021-10-13 7:11 ` [PATCH V5 21/22] LoongArch: Add Non-Uniform Memory Access (NUMA) support Huacai Chen
2021-10-13 7:11 ` [PATCH V5 22/22] LoongArch: Add Loongson-3 default config file Huacai Chen
[not found] ` <722477bcc461238f96c3b038b2e3379ee49efdac.camel@mengyan1223.wang>
2021-12-21 7:53 ` [PATCH V5 00/22] arch: Add basic LoongArch support Huacai Chen
2021-12-28 8:34 ` Xi Ruoyao
2022-01-05 9:40 ` Huacai Chen
2022-01-05 11:51 ` Xi Ruoyao
2022-01-05 17:21 ` Xi Ruoyao
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