From: Deepak Gupta <debug@rivosinc.com>
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Subject: [PATCH v2 05/27] riscv: zicfiss/zicfilp extension csr and bit definitions
Date: Thu, 28 Mar 2024 21:44:37 -0700 [thread overview]
Message-ID: <20240329044459.3990638-6-debug@rivosinc.com> (raw)
In-Reply-To: <20240329044459.3990638-1-debug@rivosinc.com>
zicfiss and zicfilp extension gets enabled via b3 and b2 in *envcfg CSR.
menvcfg controls enabling for S/HS mode. henvcfg control enabling for VS while
senvcfg controls enabling for U/VU mode.
zicfilp extension extends *status CSR to hold `expected landing pad` bit.
A trap or interrupt can occur between an indirect jmp/call and target instr.
`expected landing pad` bit from CPU is recorded into xstatus CSR so that when
supervisor performs xret, `expected landing pad` state of CPU can be restored.
zicfiss adds one new CSR
- CSR_SSP: CSR_SSP contains current shadow stack pointer.
Signed-off-by: Deepak Gupta <debug@rivosinc.com>
---
arch/riscv/include/asm/csr.h | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h
index bbd2207adb39..3bb126d1c5ff 100644
--- a/arch/riscv/include/asm/csr.h
+++ b/arch/riscv/include/asm/csr.h
@@ -18,6 +18,15 @@
#define SR_MPP _AC(0x00001800, UL) /* Previously Machine */
#define SR_SUM _AC(0x00040000, UL) /* Supervisor User Memory Access */
+/* zicfilp landing pad status bit */
+#define SR_SPELP _AC(0x00800000, UL)
+#define SR_MPELP _AC(0x020000000000, UL)
+#ifdef CONFIG_RISCV_M_MODE
+#define SR_ELP SR_MPELP
+#else
+#define SR_ELP SR_SPELP
+#endif
+
#define SR_FS _AC(0x00006000, UL) /* Floating-point Status */
#define SR_FS_OFF _AC(0x00000000, UL)
#define SR_FS_INITIAL _AC(0x00002000, UL)
@@ -196,6 +205,8 @@
#define ENVCFG_PBMTE (_AC(1, ULL) << 62)
#define ENVCFG_CBZE (_AC(1, UL) << 7)
#define ENVCFG_CBCFE (_AC(1, UL) << 6)
+#define ENVCFG_LPE (_AC(1, UL) << 2)
+#define ENVCFG_SSE (_AC(1, UL) << 3)
#define ENVCFG_CBIE_SHIFT 4
#define ENVCFG_CBIE (_AC(0x3, UL) << ENVCFG_CBIE_SHIFT)
#define ENVCFG_CBIE_ILL _AC(0x0, UL)
@@ -216,6 +227,11 @@
#define SMSTATEEN0_HSENVCFG (_ULL(1) << SMSTATEEN0_HSENVCFG_SHIFT)
#define SMSTATEEN0_SSTATEEN0_SHIFT 63
#define SMSTATEEN0_SSTATEEN0 (_ULL(1) << SMSTATEEN0_SSTATEEN0_SHIFT)
+/*
+ * zicfiss user mode csr
+ * CSR_SSP holds current shadow stack pointer.
+ */
+#define CSR_SSP 0x011
/* symbolic CSR names: */
#define CSR_CYCLE 0xc00
--
2.43.2
next prev parent reply other threads:[~2024-03-29 4:46 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-03-29 4:44 [PATCH v2 00/27] riscv control-flow integrity for usermode Deepak Gupta
2024-03-29 4:44 ` [PATCH v2 01/27] riscv: envcfg save and restore on task switching Deepak Gupta
2024-03-29 4:44 ` [PATCH v2 02/27] riscv: define default value for envcfg Deepak Gupta
2024-03-29 4:44 ` [PATCH v2 03/27] riscv/Kconfig: enable HAVE_EXIT_THREAD for riscv Deepak Gupta
2024-03-29 4:44 ` [PATCH v2 04/27] riscv: zicfiss/zicfilp enumeration Deepak Gupta
2024-03-29 5:08 ` Stefan O'Rear
2024-03-29 5:13 ` Deepak Gupta
2024-03-29 7:24 ` Conor Dooley
2024-03-29 4:44 ` Deepak Gupta [this message]
2024-03-29 4:44 ` [PATCH v2 06/27] riscv: usercfi state for task and save/restore of CSR_SSP on trap entry/exit Deepak Gupta
2024-03-29 4:44 ` [PATCH v2 07/27] mm: Define VM_SHADOW_STACK for RISC-V Deepak Gupta
2024-03-29 4:44 ` [PATCH v2 08/27] mm: abstract shadow stack vma behind `arch_is_shadow_stack` Deepak Gupta
2024-03-29 4:44 ` [PATCH v2 09/27] riscv/mm : ensure PROT_WRITE leads to VM_READ | VM_WRITE Deepak Gupta
2024-03-29 4:44 ` [PATCH v2 10/27] riscv mm: manufacture shadow stack pte Deepak Gupta
2024-03-29 4:44 ` [PATCH v2 11/27] riscv mmu: teach pte_mkwrite to manufacture shadow stack PTEs Deepak Gupta
2024-03-29 5:15 ` Deepak Gupta
2024-03-29 4:44 ` [PATCH v2 12/27] riscv mmu: write protect and shadow stack Deepak Gupta
2024-03-29 4:44 ` [PATCH v2 13/27] riscv/mm: Implement map_shadow_stack() syscall Deepak Gupta
2024-03-29 4:44 ` [PATCH v2 14/27] riscv/shstk: If needed allocate a new shadow stack on clone Deepak Gupta
2024-03-29 4:44 ` [PATCH v2 15/27] prctl: arch-agnostic prctl for shadow stack Deepak Gupta
2024-03-29 4:44 ` [PATCH v2 16/27] prctl: arch-agnostic prtcl for indirect branch tracking Deepak Gupta
2024-03-29 4:44 ` [PATCH v2 17/27] riscv: Implements arch agnostic shadow stack prctls Deepak Gupta
2024-03-29 4:44 ` [PATCH v2 18/27] riscv: Implements arch argnostic indirect branch tracking prctls Deepak Gupta
2024-03-29 4:44 ` [PATCH v2 19/27] riscv/kernel: update __show_regs to print shadow stack register Deepak Gupta
2024-03-29 4:44 ` [PATCH v2 20/27] riscv/traps: Introduce software check exception Deepak Gupta
2024-03-29 4:44 ` [PATCH v2 21/27] riscv sigcontext: adding cfi state field in sigcontext Deepak Gupta
2024-03-29 4:44 ` [PATCH v2 22/27] riscv signal: Save and restore of shadow stack for signal Deepak Gupta
2024-03-29 4:44 ` [PATCH v2 23/27] riscv/ptrace: riscv cfi status and state via ptrace and in core files Deepak Gupta
2024-03-29 4:44 ` [PATCH v2 24/27] riscv: create a config for shadow stack and landing pad instr support Deepak Gupta
2024-03-29 4:44 ` [PATCH v2 25/27] riscv: Documentation for landing pad / indirect branch tracking Deepak Gupta
2024-03-29 4:44 ` [PATCH v2 26/27] riscv: Documentation for shadow stack on riscv Deepak Gupta
2024-03-29 4:44 ` [PATCH v2 27/27] kselftest/riscv: kselftest for user mode cfi Deepak Gupta
2024-03-29 19:50 ` Muhammad Usama Anjum
2024-03-29 20:02 ` Deepak Gupta
2024-04-01 9:46 ` Muhammad Usama Anjum
2024-04-01 17:34 ` Deepak Gupta
2024-04-01 17:55 ` Deepak Gupta
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