[PATCH v9 0/4] PCI: brcmstb: Configure appropriate HW CLKREQ# mode

From: Jim Quinlan <james.quinlan@broadcom.com>
To: linux-pci@vger.kernel.org,
	Nicolas Saenz Julienne <nsaenz@kernel.org>,
	Bjorn Helgaas <bhelgaas@google.com>,
	Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
	Cyril Brulebois <kibi@debian.org>,
	Phil Elwell <phil@raspberrypi.com>,
	bcm-kernel-feedback-list@broadcom.com,
	james.quinlan@broadcom.com
Cc: "Conor Dooley" <conor+dt@kernel.org>,
	devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND
	FLATTENED DEVICE TREE BINDINGS),
	"Florian Fainelli" <florian.fainelli@broadcom.com>,
	"Jim Quinlan" <jim2101024@gmail.com>,
	"Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>,
	"Krzysztof Wilczyński" <kw@linux.com>,
	linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM
	BCM2711/BCM2835 ARM ARCHITECTURE),
	linux-kernel@vger.kernel.org (open list),
	linux-rpi-kernel@lists.infradead.org (moderated list:BROADCOM
	BCM2711/BCM2835 ARM ARCHITECTURE),
	"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
	"Rob Herring" <robh@kernel.org>
Subject: [PATCH v9 0/4] PCI: brcmstb: Configure appropriate HW CLKREQ# mode
Date: Wed,  3 Apr 2024 17:38:57 -0400	[thread overview]
Message-ID: <20240403213902.26391-1-james.quinlan@broadcom.com> (raw)


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v9 -- v8 was setting an internal bus timeout to accomodate large L1 exit
      latencies.  After meeting the PCIe HW team it was revealed that the
      HW default timeout value was set low for the purposes of HW debugging
      convenience; for nominal operation it needs to be set to a higher
      value independent of this submission's purpose.  This is now a
      separate commit.

   -- With v8, Bjorne asked what was preventing a device from exceeding the
      time required for the above internal bus timeout.  The answer to this
      is for us to set the endpoints' max latency {no-,}snoop value to
      something below this internal timeout value.  If the endpoint
      respects this value as it should, it will not send an LTR request
      with a larger latency value and not put itself in a situation
      that requires more latency than is possible for the platform.

      Typically, ACPI or FW sets these max latency values.  In most of our
      systems we do not have this happening so it is up to the RC driver to
      set these values in the endpoint devices.  If the endpoints already
      have non-zero values that are lower than what we are setting, we let
      them be, as it is possible ACPI or FW set them and knows something
      that we do not.

   -- The "clkreq" commit has only been changed to remove the code that was
      setting the timeout value, as this code is now its own commit.

v8 -- Un-advertise L1SS capability when in "no-l1ss" mode (Bjorn)
   -- Squashed last two commits of v7 (Bjorn)
   -- Fix DT binding description text wrapping (Bjorn)
   -- Fix incorrect Spec reference (Bjorn)
         s/PCIe Spec/PCIe Express Mini CEM 2.1 specification/
   -- Text substitutions (Bjorn)
         s/WRT/With respect to/ 
         s/Tclron/T_CLRon/

v7 -- Manivannan Sadhasivam suggested (a) making the property look like a
      network phy-mode and (b) keeping the code simple (not counting clkreq
      signal appearances, un-advertising capabilites, etc).  This is
      what I have done.  The property is now "brcm,clkreq-mode" and
      the values may be one of "safe", "default", and "no-l1ss".  The
      default setting is to employ the most capable power savings mode.

v6 -- No code has been changed.
   -- Changed commit subject and comment in "#PERST" commit (Bjorn, Cyril)
   -- Changed sign-off and author email address for all commits.
      This was due to a change in Broadcom's upstreaming policy.

v5 -- Remove DT property "brcm,completion-timeout-us" from	 
      "DT bindings" commit.  Although this error may be reported	 
      as a completion timeout, its cause was traced to an	 
      internal bus timeout which may occur even when there is	 
      no PCIe access being processed.  We set a timeout of four	 
      seconds only if we are operating in "L1SS CLKREQ#" mode.
   -- Correct CEM 2.0 reference provided by HW engineer,
      s/3.2.5.2.5/3.2.5.2.2/ (Bjorn)
   -- Add newline to dev_info() string (Stefan)
   -- Change variable rval to unsigned (Stefan)
   -- s/implementaion/implementation/ (Bjorn)
   -- s/superpowersave/powersupersave/ (Bjorn)
   -- Slightly modify message on "PERST#" commit.
   -- Rebase to torvalds master

v4 -- New commit that asserts PERST# for 2711/RPi SOCs at PCIe RC
      driver probe() time.  This is done in Raspian Linux and its
      absence may be the cause of a failing test case.
   -- New commit that removes stale comment.

v3 -- Rewrote commit msgs and comments refering panics if L1SS
      is enabled/disabled; the code snippet that unadvertises L1SS
      eliminates the panic scenario. (Bjorn)
   -- Add reference for "400ns of CLKREQ# assertion" blurb (Bjorn)
   -- Put binding names in DT commit Subject (Bjorn)
   -- Add a verb to a commit's subject line (Bjorn)
   -- s/accomodat(\w+)/accommodat$1/g (Bjorn)
   -- Rewrote commit msgs and comments refering panics if L1SS
      is enabled/disabled; the code snippet that unadvertises L1SS
      eliminates the panic scenario. (Bjorn)

v2 -- Changed binding property 'brcm,completion-timeout-msec' to
      'brcm,completion-timeout-us'.  (StefanW for standard suffix).
   -- Warn when clamping timeout value, and include clamped
      region in message. Also add min and max in YAML. (StefanW)
   -- Qualify description of "brcm,completion-timeout-us" so that
      it refers to PCIe transactions. (StefanW)
   -- Remvove mention of Linux specifics in binding description. (StefanW)
   -- s/clkreq#/CLKREQ#/g (Bjorn)
   -- Refactor completion-timeout-us code to compare max and min to
      value given by the property (as opposed to the computed value).

v1 -- The current driver assumes the downstream devices can
      provide CLKREQ# for ASPM.  These commits accomodate devices
      w/ or w/o clkreq# and also handle L1SS-capable devices.

   -- The Raspian Linux folks have already been using a PCIe RC
      property "brcm,enable-l1ss".  These commits use the same
      property, in a backward-compatible manner, and the implementaion
      adds more detail and also automatically identifies devices w/o
      a clkreq# signal, i.e. most devices plugged into an RPi CM4
      IO board.

Jim Quinlan (4):
  dt-bindings: PCI: brcmstb: Add property "brcm,clkreq-mode"
  PCI: brcmstb: Set reasonable value for internal bus timeout
  PCI: brcmstb: Set downstream maximum {no-}snoop LTR values
  PCI: brcmstb: Configure HW CLKREQ# mode appropriate for downstream
    device

 .../bindings/pci/brcm,stb-pcie.yaml           |  18 ++
 drivers/pci/controller/pcie-brcmstb.c         | 161 +++++++++++++++++-
 2 files changed, 170 insertions(+), 9 deletions(-)


base-commit: 9f8413c4a66f2fb776d3dc3c9ed20bf435eb305e
-- 
2.17.1


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