From: Frank Li <Frank.Li@nxp.com>
To: "Richard Zhu" <hongxing.zhu@nxp.com>,
"Lucas Stach" <l.stach@pengutronix.de>,
"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
"Krzysztof Wilczyński" <kw@linux.com>,
"Rob Herring" <robh@kernel.org>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Shawn Guo" <shawnguo@kernel.org>,
"Sascha Hauer" <s.hauer@pengutronix.de>,
"Pengutronix Kernel Team" <kernel@pengutronix.de>,
"Fabio Estevam" <festevam@gmail.com>,
"NXP Linux Team" <linux-imx@nxp.com>,
"Philipp Zabel" <p.zabel@pengutronix.de>,
"Liam Girdwood" <lgirdwood@gmail.com>,
"Mark Brown" <broonie@kernel.org>,
"Manivannan Sadhasivam" <manivannan.sadhasivam@linaro.org>,
"Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>,
"Conor Dooley" <conor+dt@kernel.org>
Cc: linux-pci@vger.kernel.org, imx@lists.linux.dev,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, bpf@vger.kernel.org,
devicetree@vger.kernel.org, Frank Li <Frank.Li@nxp.com>
Subject: [PATCH v4 12/12] PCI: imx6: Add i.MX8Q PCIe root complex (RC) support
Date: Tue, 07 May 2024 14:45:50 -0400 [thread overview]
Message-ID: <20240507-pci2_upstream-v4-12-e8c80d874057@nxp.com> (raw)
In-Reply-To: <20240507-pci2_upstream-v4-0-e8c80d874057@nxp.com>
From: Richard Zhu <hongxing.zhu@nxp.com>
Implement i.MX8Q (i.MX8QM, i.MX8QXP, and i.MX8DXL) PCIe RC support. While
the controller resembles that of iMX8MP, the PHY differs significantly.
Notably, there's a distinction between PCI bus addresses and CPU addresses.
Introduce IMX_PCIE_FLAG_CPU_ADDR_FIXUP in drvdata::flags to indicate driver
need the cpu_addr_fixup() callback to facilitate CPU address to PCI bus
address conversion according to "range" property.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
drivers/pci/controller/dwc/pci-imx6.c | 35 +++++++++++++++++++++++++++++++++++
1 file changed, 35 insertions(+)
diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
index df623977d8fe6..a5af3e874613d 100644
--- a/drivers/pci/controller/dwc/pci-imx6.c
+++ b/drivers/pci/controller/dwc/pci-imx6.c
@@ -82,6 +82,7 @@ enum imx_pcie_variants {
IMX8MQ,
IMX8MM,
IMX8MP,
+ IMX8Q,
IMX95,
IMX8MQ_EP,
IMX8MM_EP,
@@ -98,6 +99,7 @@ enum imx_pcie_variants {
#define IMX_PCIE_FLAG_HAS_SERDES BIT(6)
#define IMX_PCIE_FLAG_SUPPORT_64BIT BIT(7)
#define IMX_PCIE_FLAG_MONITOR_DEV BIT(8)
+#define IMX_PCIE_FLAG_CPU_ADDR_FIXUP BIT(9)
#define imx_check_flag(pci, val) (pci->drvdata->flags & val)
@@ -1091,6 +1093,22 @@ static void imx_pcie_host_exit(struct dw_pcie_rp *pp)
regulator_disable(imx_pcie->vpcie);
}
+static u64 imx_pcie_cpu_addr_fixup(struct dw_pcie *pcie, u64 cpu_addr)
+{
+ struct imx_pcie *imx_pcie = to_imx_pcie(pcie);
+ struct dw_pcie_rp *pp = &pcie->pp;
+ struct resource_entry *entry;
+ unsigned int offset;
+
+ if (!(imx_pcie->drvdata->flags & IMX_PCIE_FLAG_CPU_ADDR_FIXUP))
+ return cpu_addr;
+
+ entry = resource_list_first_type(&pp->bridge->windows, IORESOURCE_MEM);
+ offset = entry->offset;
+
+ return (cpu_addr - offset);
+}
+
static const struct dw_pcie_host_ops imx_pcie_host_ops = {
.init = imx_pcie_host_init,
.deinit = imx_pcie_host_exit,
@@ -1099,6 +1117,7 @@ static const struct dw_pcie_host_ops imx_pcie_host_ops = {
static const struct dw_pcie_ops dw_pcie_ops = {
.start_link = imx_pcie_start_link,
.stop_link = imx_pcie_stop_link,
+ .cpu_addr_fixup = imx_pcie_cpu_addr_fixup,
};
static void imx_pcie_ep_init(struct dw_pcie_ep *ep)
@@ -1599,6 +1618,13 @@ static int imx_pcie_probe(struct platform_device *pdev)
if (ret < 0)
return ret;
+ if (imx_check_flag(imx_pcie, IMX_PCIE_FLAG_CPU_ADDR_FIXUP)) {
+ if (!resource_list_first_type(&pci->pp.bridge->windows, IORESOURCE_MEM)) {
+ dw_pcie_host_deinit(&pci->pp);
+ return dev_err_probe(dev, -EINVAL, "DTS Miss PCI memory range");
+ }
+ }
+
if (pci_msi_enabled()) {
u8 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_MSI);
@@ -1623,6 +1649,7 @@ static const char * const imx6q_clks[] = {"pcie_bus", "pcie", "pcie_phy"};
static const char * const imx8mm_clks[] = {"pcie_bus", "pcie", "pcie_aux"};
static const char * const imx8mq_clks[] = {"pcie_bus", "pcie", "pcie_phy", "pcie_aux"};
static const char * const imx6sx_clks[] = {"pcie_bus", "pcie", "pcie_phy", "pcie_inbound_axi"};
+static const char * const imx8q_clks[] = {"mstr", "slv", "dbi"};
static const struct imx_pcie_drvdata drvdata[] = {
[IMX6Q] = {
@@ -1726,6 +1753,13 @@ static const struct imx_pcie_drvdata drvdata[] = {
.mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
.set_ref_clk = imx8mm_pcie_set_ref_clk,
},
+ [IMX8Q] = {
+ .variant = IMX8Q,
+ .flags = IMX_PCIE_FLAG_HAS_PHYDRV |
+ IMX_PCIE_FLAG_CPU_ADDR_FIXUP,
+ .clk_names = imx8q_clks,
+ .clks_cnt = ARRAY_SIZE(imx8q_clks),
+ },
[IMX95] = {
.variant = IMX95,
.flags = IMX_PCIE_FLAG_HAS_SERDES |
@@ -1804,6 +1838,7 @@ static const struct of_device_id imx_pcie_of_match[] = {
{ .compatible = "fsl,imx8mq-pcie", .data = &drvdata[IMX8MQ], },
{ .compatible = "fsl,imx8mm-pcie", .data = &drvdata[IMX8MM], },
{ .compatible = "fsl,imx8mp-pcie", .data = &drvdata[IMX8MP], },
+ { .compatible = "fsl,imx8q-pcie", .data = &drvdata[IMX8Q], },
{ .compatible = "fsl,imx95-pcie", .data = &drvdata[IMX95], },
{ .compatible = "fsl,imx8mq-pcie-ep", .data = &drvdata[IMX8MQ_EP], },
{ .compatible = "fsl,imx8mm-pcie-ep", .data = &drvdata[IMX8MM_EP], },
--
2.34.1
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next prev parent reply other threads:[~2024-05-07 19:02 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-05-07 18:45 [PATCH v4 00/12] PCI: imx6: Fix\rename\clean up and add lut information for imx95 Frank Li
2024-05-07 18:45 ` [PATCH v4 01/12] PCI: imx6: Fix establish link failure in EP mode for iMX8MM and iMX8MP Frank Li
2024-05-07 18:45 ` [PATCH v4 02/12] PCI: imx6: Fix i.MX8MP PCIe EP's occasional failure to trigger MSI Frank Li
2024-05-07 18:45 ` [PATCH v4 03/12] PCI: imx6: Rename imx6_* with imx_* Frank Li
2024-05-07 18:45 ` [PATCH v4 04/12] PCI: imx6: Introduce SoC specific callbacks for controlling REFCLK Frank Li
2024-05-07 18:45 ` [PATCH v4 05/12] PCI: imx6: Simplify switch-case logic by involve core_reset callback Frank Li
2024-05-07 18:45 ` [PATCH v4 06/12] PCI: imx6: Improve comment for workaround ERR010728 Frank Li
2024-05-07 18:45 ` [PATCH v4 07/12] PCI: imx6: Add help function imx_pcie_match_device() Frank Li
2024-05-07 18:45 ` [PATCH v4 08/12] PCI: imx6: Config look up table(LUT) to support MSI ITS and IOMMU for i.MX95 Frank Li
2024-05-07 18:45 ` [PATCH v4 09/12] PCI: imx6: Consolidate redundant if-checks Frank Li
2024-05-07 18:45 ` [PATCH v4 10/12] dt-bindings: imx6q-pcie: Add i.MX8Q pcie compatible string Frank Li
2024-05-08 16:55 ` Conor Dooley
2024-05-08 17:52 ` Rob Herring (Arm)
2024-05-07 18:45 ` [PATCH v4 11/12] PCI: imx6: Call: Common PHY API to set mode, speed, and submode Frank Li
2024-05-07 18:45 ` Frank Li [this message]
2024-05-20 15:59 ` [PATCH v4 00/12] PCI: imx6: Fix\rename\clean up and add lut information for imx95 Frank Li
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