From: Bibek Kumar Patro <quic_bibekkum@quicinc.com>
To: <will@kernel.org>, <robin.murphy@arm.com>, <joro@8bytes.org>,
<dmitry.baryshkov@linaro.org>, <konrad.dybcio@linaro.org>,
<jsnitsel@redhat.com>, <quic_bjorande@quicinc.com>,
<mani@kernel.org>, <quic_eberman@quicinc.com>,
<robdclark@chromium.org>, <u.kleine-koenig@pengutronix.de>,
<robh@kernel.org>, <vladimir.oltean@nxp.com>,
<quic_pkondeti@quicinc.com>, <quic_molvera@quicinc.com>
Cc: <linux-arm-msm@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>, <iommu@lists.linux.dev>,
<linux-kernel@vger.kernel.org>,
Bibek Kumar Patro <quic_bibekkum@quicinc.com>
Subject: [PATCH v9 1/5] iommu/arm-smmu: re-enable context caching in smmu reset operation
Date: Tue, 23 Jan 2024 20:15:39 +0530 [thread overview]
Message-ID: <20240123144543.9405-2-quic_bibekkum@quicinc.com> (raw)
In-Reply-To: <20240123144543.9405-1-quic_bibekkum@quicinc.com>
Default MMU-500 reset operation disables context caching in
prefetch buffer. It is however expected for context banks using
the ACTLR register to retain their prefetch value during reset
and runtime suspend.
Replace default MMU-500 reset operation with Qualcomm specific reset
operation which envelope the default reset operation and re-enables
context caching in prefetch buffer for Qualcomm SoCs.
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bibek Kumar Patro <quic_bibekkum@quicinc.com>
---
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 36 ++++++++++++++++++++--
1 file changed, 33 insertions(+), 3 deletions(-)
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
index 549ae4dba3a6..c432e80a69fc 100644
--- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
@@ -14,6 +14,16 @@
#define QCOM_DUMMY_VAL -1
+/*
+ * SMMU-500 TRM defines BIT(0) as CMTLB (Enable context caching in the
+ * macro TLB) and BIT(1) as CPRE (Enable context caching in the prefetch
+ * buffer). The remaining bits are implementation defined and vary across
+ * SoCs.
+ */
+
+#define CPRE (1 << 1)
+#define CMTLB (1 << 0)
+
static struct qcom_smmu *to_qcom_smmu(struct arm_smmu_device *smmu)
{
return container_of(smmu, struct qcom_smmu, smmu);
@@ -376,11 +386,31 @@ static int qcom_smmu_def_domain_type(struct device *dev)
return match ? IOMMU_DOMAIN_IDENTITY : 0;
}
+static int qcom_smmu500_reset(struct arm_smmu_device *smmu)
+{
+ int ret;
+ u32 val;
+ int i;
+
+ ret = arm_mmu500_reset(smmu);
+ if (ret)
+ return ret;
+
+ /* arm_mmu500_reset() disables CPRE which is re-enabled here */
+ for (i = 0; i < smmu->num_context_banks; ++i) {
+ val = arm_smmu_cb_read(smmu, i, ARM_SMMU_CB_ACTLR);
+ val |= CPRE;
+ arm_smmu_cb_write(smmu, i, ARM_SMMU_CB_ACTLR, val);
+ }
+
+ return 0;
+}
+
static int qcom_sdm845_smmu500_reset(struct arm_smmu_device *smmu)
{
int ret;
- arm_mmu500_reset(smmu);
+ qcom_smmu500_reset(smmu);
/*
* To address performance degradation in non-real time clients,
@@ -407,7 +437,7 @@ static const struct arm_smmu_impl qcom_smmu_500_impl = {
.init_context = qcom_smmu_init_context,
.cfg_probe = qcom_smmu_cfg_probe,
.def_domain_type = qcom_smmu_def_domain_type,
- .reset = arm_mmu500_reset,
+ .reset = qcom_smmu500_reset,
.write_s2cr = qcom_smmu_write_s2cr,
.tlb_sync = qcom_smmu_tlb_sync,
};
@@ -432,7 +462,7 @@ static const struct arm_smmu_impl qcom_adreno_smmu_v2_impl = {
static const struct arm_smmu_impl qcom_adreno_smmu_500_impl = {
.init_context = qcom_adreno_smmu_init_context,
.def_domain_type = qcom_smmu_def_domain_type,
- .reset = arm_mmu500_reset,
+ .reset = qcom_smmu500_reset,
.alloc_context_bank = qcom_adreno_smmu_alloc_context_bank,
.write_sctlr = qcom_adreno_smmu_write_sctlr,
.tlb_sync = qcom_smmu_tlb_sync,
--
2.17.1
next prev parent reply other threads:[~2024-01-23 14:46 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-01-23 14:45 [PATCH v9 0/5] iommu/arm-smmu: introduction of ACTLR implementation for Qualcomm SoCs Bibek Kumar Patro
2024-01-23 14:45 ` Bibek Kumar Patro [this message]
2024-01-23 14:45 ` [PATCH v9 2/5] iommu/arm-smmu: refactor qcom_smmu structure to include single pointer Bibek Kumar Patro
2024-01-23 14:45 ` [PATCH v9 3/5] iommu/arm-smmu: introduction of ACTLR for custom prefetcher settings Bibek Kumar Patro
2024-02-09 9:55 ` Bibek Kumar Patro
2024-02-09 10:53 ` Dmitry Baryshkov
2024-04-30 19:00 ` Rob Clark
2024-05-10 12:52 ` Bibek Kumar Patro
2024-05-10 13:02 ` Konrad Dybcio
2024-05-15 13:59 ` Bibek Kumar Patro
2024-05-28 12:59 ` Konrad Dybcio
2024-05-28 13:06 ` Dmitry Baryshkov
2024-05-28 16:08 ` Rob Clark
2024-05-28 16:09 ` Dmitry Baryshkov
2024-05-30 9:21 ` Bibek Kumar Patro
2024-05-30 11:18 ` Dmitry Baryshkov
2024-06-04 18:49 ` Rob Clark
2024-06-05 10:52 ` Bibek Kumar Patro
2024-06-05 22:13 ` Rob Clark
2024-06-10 10:12 ` Bibek Kumar Patro
2024-05-30 9:21 ` Bibek Kumar Patro
2024-05-30 9:21 ` Bibek Kumar Patro
2024-05-10 19:48 ` Rob Clark
2024-05-15 13:59 ` Bibek Kumar Patro
2024-01-23 14:45 ` [PATCH v9 4/5] iommu/arm-smmu: add ACTLR data and support for SM8550 Bibek Kumar Patro
2024-01-23 18:42 ` Konrad Dybcio
2024-02-13 13:47 ` Will Deacon
2024-02-21 8:55 ` Bibek Kumar Patro
2024-02-21 13:21 ` Will Deacon
2024-03-11 8:42 ` Bibek Kumar Patro
2024-01-23 14:45 ` [PATCH v9 5/5] iommu/arm-smmu: add ACTLR data and support for SC7280 Bibek Kumar Patro
2024-01-23 18:42 ` Konrad Dybcio
2024-04-30 17:59 ` [PATCH v9 0/5] iommu/arm-smmu: introduction of ACTLR implementation for Qualcomm SoCs Dmitry Baryshkov
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