From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
To: Rob Clark <robdclark@gmail.com>
Cc: Konrad Dybcio <konrad.dybcio@linaro.org>,
Bibek Kumar Patro <quic_bibekkum@quicinc.com>,
will@kernel.org, robin.murphy@arm.com, joro@8bytes.org,
jsnitsel@redhat.com, quic_bjorande@quicinc.com, mani@kernel.org,
quic_eberman@quicinc.com, robdclark@chromium.org,
u.kleine-koenig@pengutronix.de, robh@kernel.org,
vladimir.oltean@nxp.com, quic_pkondeti@quicinc.com,
quic_molvera@quicinc.com, linux-arm-msm@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v9 3/5] iommu/arm-smmu: introduction of ACTLR for custom prefetcher settings
Date: Tue, 28 May 2024 19:09:04 +0300 [thread overview]
Message-ID: <CAA8EJprW8fTf0tWDWq+aVVauJnK0NqBke-JNELm_GMPvoWa7vA@mail.gmail.com> (raw)
In-Reply-To: <CAF6AEGub2b5SRw7kDUGfKQQ35VSsMkQ9LNExSkyHHczdFa2T4Q@mail.gmail.com>
On Tue, 28 May 2024 at 19:08, Rob Clark <robdclark@gmail.com> wrote:
>
> On Tue, May 28, 2024 at 6:06 AM Dmitry Baryshkov
> <dmitry.baryshkov@linaro.org> wrote:
> >
> > On Tue, May 28, 2024 at 02:59:51PM +0200, Konrad Dybcio wrote:
> > >
> > >
> > > On 5/15/24 15:59, Bibek Kumar Patro wrote:
> > > >
> > > >
> > > > On 5/10/2024 6:32 PM, Konrad Dybcio wrote:
> > > > > On 10.05.2024 2:52 PM, Bibek Kumar Patro wrote:
> > > > > >
> > > > > >
> > > > > > On 5/1/2024 12:30 AM, Rob Clark wrote:
> > > > > > > On Tue, Jan 23, 2024 at 7:00 AM Bibek Kumar Patro
> > > > > > > <quic_bibekkum@quicinc.com> wrote:
> > > > > > > >
> > > > > > > > Currently in Qualcomm SoCs the default prefetch is set to 1 which allows
> > > > > > > > the TLB to fetch just the next page table. MMU-500 features ACTLR
> > > > > > > > register which is implementation defined and is used for Qualcomm SoCs
> > > > > > > > to have a custom prefetch setting enabling TLB to prefetch the next set
> > > > > > > > of page tables accordingly allowing for faster translations.
> > > > > > > >
> > > > > > > > ACTLR value is unique for each SMR (Stream matching register) and stored
> > > > > > > > in a pre-populated table. This value is set to the register during
> > > > > > > > context bank initialisation.
> > > > > > > >
> > > > > > > > Signed-off-by: Bibek Kumar Patro <quic_bibekkum@quicinc.com>
> > > > > > > > ---
> > > > >
> > > > > [...]
> > > > >
> > > > > > > > +
> > > > > > > > + for_each_cfg_sme(cfg, fwspec, j, idx) {
> > > > > > > > + smr = &smmu->smrs[idx];
> > > > > > > > + if (smr_is_subset(smr, id, mask)) {
> > > > > > > > + arm_smmu_cb_write(smmu, cbndx, ARM_SMMU_CB_ACTLR,
> > > > > > > > + actlrcfg[i].actlr);
> > > > > > >
> > > > > > > So, this makes ACTLR look like kind of a FIFO. But I'm looking at
> > > > > > > downstream kgsl's PRR thing (which we'll need to implement vulkan
> > > > > > > sparse residency), and it appears to be wanting to set BIT(5) in ACTLR
> > > > > > > to enable PRR.
> > > > > > >
> > > > > > > val = KGSL_IOMMU_GET_CTX_REG(ctx, KGSL_IOMMU_CTX_ACTLR);
> > > > > > > val |= FIELD_PREP(KGSL_IOMMU_ACTLR_PRR_ENABLE, 1);
> > > > > > > KGSL_IOMMU_SET_CTX_REG(ctx, KGSL_IOMMU_CTX_ACTLR, val);
> > > > > > >
> > > > > > > Any idea how this works? And does it need to be done before or after
> > > > > > > the ACTLR programming done in this patch?
> > > > > > >
> > > > > > > BR,
> > > > > > > -R
> > > > > > >
> > > > > >
> > > > > > Hi Rob,
> > > > > >
> > > > > > Can you please help provide some more clarification on the FIFO part? By FIFO are you referring to the storing of ACTLR data in the table?
> > > > > >
> > > > > > Thanks for pointing to the downstream implementation of kgsl driver for
> > > > > > the PRR bit. Since kgsl driver is already handling this PRR bit's
> > > > > > setting, this makes setting the PRR BIT(5) by SMMU driver redundant.
> > > > >
> > > > > The kgsl driver is not present upstream.
> > > > >
> > > >
> > > > Right kgsl is not present upstream, it would be better to avoid configuring the PRR bit and can be handled by kgsl directly in downstream.
> > >
> > > No! Upstream is not a dumping ground to reduce your technical debt.
> > >
> > > There is no kgsl driver upstream, so this ought to be handled here, in
> > > the iommu driver (as poking at hardware A from driver B is usually not good
> > > practice).
> >
> > I'd second the request here. If another driver has to control the
> > behaviour of another driver, please add corresponding API for that.
>
> We have adreno_smmu_priv for this purpose ;-)
Exactly
>
> BR,
> -R
>
> > >
> > > >
> > > > > > Thanks for bringing up this point.
> > > > > > I will send v10 patch series removing this BIT(5) setting from the ACTLR
> > > > > > table.
> > > > >
> > > > > I think it's generally saner to configure the SMMU from the SMMU driver..
> > > >
> > > > Yes, agree on this. But since PRR bit is not directly related to SMMU
> > > > configuration so I think it would be better to remove this PRR bit
> > > > setting from SMMU driver based on my understanding.
> > >
> > > Why is it not related? We still don't know what it does.
> > >
> > > Konrad
> >
> > --
> > With best wishes
> > Dmitry
--
With best wishes
Dmitry
next prev parent reply other threads:[~2024-05-28 16:09 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-01-23 14:45 [PATCH v9 0/5] iommu/arm-smmu: introduction of ACTLR implementation for Qualcomm SoCs Bibek Kumar Patro
2024-01-23 14:45 ` [PATCH v9 1/5] iommu/arm-smmu: re-enable context caching in smmu reset operation Bibek Kumar Patro
2024-01-23 14:45 ` [PATCH v9 2/5] iommu/arm-smmu: refactor qcom_smmu structure to include single pointer Bibek Kumar Patro
2024-01-23 14:45 ` [PATCH v9 3/5] iommu/arm-smmu: introduction of ACTLR for custom prefetcher settings Bibek Kumar Patro
2024-02-09 9:55 ` Bibek Kumar Patro
2024-02-09 10:53 ` Dmitry Baryshkov
2024-04-30 19:00 ` Rob Clark
2024-05-10 12:52 ` Bibek Kumar Patro
2024-05-10 13:02 ` Konrad Dybcio
2024-05-15 13:59 ` Bibek Kumar Patro
2024-05-28 12:59 ` Konrad Dybcio
2024-05-28 13:06 ` Dmitry Baryshkov
2024-05-28 16:08 ` Rob Clark
2024-05-28 16:09 ` Dmitry Baryshkov [this message]
2024-05-30 9:21 ` Bibek Kumar Patro
2024-05-30 11:18 ` Dmitry Baryshkov
2024-06-04 18:49 ` Rob Clark
2024-06-05 10:52 ` Bibek Kumar Patro
2024-06-05 22:13 ` Rob Clark
2024-06-10 10:12 ` Bibek Kumar Patro
2024-05-30 9:21 ` Bibek Kumar Patro
2024-05-30 9:21 ` Bibek Kumar Patro
2024-05-10 19:48 ` Rob Clark
2024-05-15 13:59 ` Bibek Kumar Patro
2024-01-23 14:45 ` [PATCH v9 4/5] iommu/arm-smmu: add ACTLR data and support for SM8550 Bibek Kumar Patro
2024-01-23 18:42 ` Konrad Dybcio
2024-02-13 13:47 ` Will Deacon
2024-02-21 8:55 ` Bibek Kumar Patro
2024-02-21 13:21 ` Will Deacon
2024-03-11 8:42 ` Bibek Kumar Patro
2024-01-23 14:45 ` [PATCH v9 5/5] iommu/arm-smmu: add ACTLR data and support for SC7280 Bibek Kumar Patro
2024-01-23 18:42 ` Konrad Dybcio
2024-04-30 17:59 ` [PATCH v9 0/5] iommu/arm-smmu: introduction of ACTLR implementation for Qualcomm SoCs Dmitry Baryshkov
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