From: Chen Wang <unicornxw@gmail.com>
To: aou@eecs.berkeley.edu, chao.wei@sophgo.com, conor@kernel.org,
krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com,
palmer@dabbelt.com, paul.walmsley@sifive.com,
richardcochran@gmail.com, robh+dt@kernel.org, sboyd@kernel.org,
devicetree@vger.kernel.org, linux-clk@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
haijiao.liu@sophgo.com, xiaoguang.xing@sophgo.com,
guoren@kernel.org, jszhang@kernel.org, inochiama@outlook.com,
samuel.holland@sifive.com
Cc: Chen Wang <unicorn_wang@outlook.com>
Subject: [PATCH v15 5/5] riscv: dts: add clock generator for Sophgo SG2042 SoC
Date: Fri, 26 Apr 2024 11:35:42 +0800 [thread overview]
Message-ID: <165c49ca3823043a14420e3001c2657f0a1b9802.1714101547.git.unicorn_wang@outlook.com> (raw)
In-Reply-To: <cover.1714101547.git.unicorn_wang@outlook.com>
From: Chen Wang <unicorn_wang@outlook.com>
Add clock generator node to device tree for SG2042, and enable clock for
uart.
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Reviewed-by: Guo Ren <guoren@kernel.org>
---
.../boot/dts/sophgo/sg2042-milkv-pioneer.dts | 12 ++++
arch/riscv/boot/dts/sophgo/sg2042.dtsi | 55 ++++++++++++++++++-
2 files changed, 66 insertions(+), 1 deletion(-)
diff --git a/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts b/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts
index 49b4b9c2c101..80cb017974d8 100644
--- a/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts
+++ b/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts
@@ -14,6 +14,18 @@ chosen {
};
};
+&cgi_main {
+ clock-frequency = <25000000>;
+};
+
+&cgi_dpll0 {
+ clock-frequency = <25000000>;
+};
+
+&cgi_dpll1 {
+ clock-frequency = <25000000>;
+};
+
&uart0 {
status = "okay";
};
diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
index 81fda312f988..34c802bd3f9b 100644
--- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi
+++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
@@ -4,8 +4,10 @@
*/
/dts-v1/;
+#include <dt-bindings/clock/sophgo,sg2042-clkgen.h>
+#include <dt-bindings/clock/sophgo,sg2042-pll.h>
+#include <dt-bindings/clock/sophgo,sg2042-rpgate.h>
#include <dt-bindings/interrupt-controller/irq.h>
-
#include <dt-bindings/reset/sophgo,sg2042-reset.h>
#include "sg2042-cpus.dtsi"
@@ -20,12 +22,60 @@ aliases {
serial0 = &uart0;
};
+ cgi_main: oscillator0 {
+ compatible = "fixed-clock";
+ clock-output-names = "cgi_main";
+ #clock-cells = <0>;
+ };
+
+ cgi_dpll0: oscillator1 {
+ compatible = "fixed-clock";
+ clock-output-names = "cgi_dpll0";
+ #clock-cells = <0>;
+ };
+
+ cgi_dpll1: oscillator2 {
+ compatible = "fixed-clock";
+ clock-output-names = "cgi_dpll1";
+ #clock-cells = <0>;
+ };
+
soc: soc {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges;
+ pllclk: clock-controller@70300100c0 {
+ compatible = "sophgo,sg2042-pll";
+ reg = <0x70 0x300100c0 0x0 0x40>;
+ clocks = <&cgi_main>, <&cgi_dpll0>, <&cgi_dpll1>;
+ clock-names = "cgi_main", "cgi_dpll0", "cgi_dpll1";
+ #clock-cells = <1>;
+ };
+
+ rpgate: clock-controller@7030010368 {
+ compatible = "sophgo,sg2042-rpgate";
+ reg = <0x70 0x30010368 0x0 0x98>;
+ clocks = <&clkgen GATE_CLK_RP_CPU_NORMAL>;
+ clock-names = "rpgate";
+ #clock-cells = <1>;
+ };
+
+ clkgen: clock-controller@7030012000 {
+ compatible = "sophgo,sg2042-clkgen";
+ reg = <0x70 0x30012000 0x0 0x1000>;
+ clocks = <&pllclk MPLL_CLK>,
+ <&pllclk FPLL_CLK>,
+ <&pllclk DPLL0_CLK>,
+ <&pllclk DPLL1_CLK>;
+ clock-names = "mpll",
+ "fpll",
+ "dpll0",
+ "dpll1";
+ #clock-cells = <1>;
+ };
+
clint_mswi: interrupt-controller@7094000000 {
compatible = "sophgo,sg2042-aclint-mswi", "thead,c900-aclint-mswi";
reg = <0x00000070 0x94000000 0x00000000 0x00004000>;
@@ -341,6 +391,9 @@ uart0: serial@7040000000 {
interrupt-parent = <&intc>;
interrupts = <112 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <500000000>;
+ clocks = <&clkgen GATE_CLK_UART_500M>,
+ <&clkgen GATE_CLK_APB_UART>;
+ clock-names = "baudclk", "apb_pclk";
reg-shift = <2>;
reg-io-width = <4>;
resets = <&rstgen RST_UART0>;
--
2.25.1
next prev parent reply other threads:[~2024-04-26 3:35 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-26 3:32 [PATCH v15 0/5] riscv: sophgo: add clock support for sg2042 Chen Wang
2024-04-26 3:33 ` [PATCH v15 1/5] dt-bindings: clock: sophgo: add pll clocks for SG2042 Chen Wang
2024-04-26 3:34 ` [PATCH v15 2/5] dt-bindings: clock: sophgo: add RP gate " Chen Wang
2024-04-26 3:35 ` [PATCH v15 3/5] dt-bindings: clock: sophgo: add clkgen " Chen Wang
2024-04-26 3:35 ` [PATCH v15 4/5] clk: sophgo: Add SG2042 clock driver Chen Wang
2024-04-30 0:29 ` Chen Wang
2024-04-30 7:48 ` Emil Renner Berthing
2024-06-06 5:57 ` Chen Wang
2024-04-26 3:35 ` Chen Wang [this message]
2024-04-26 3:40 ` [PATCH v15 0/5] riscv: sophgo: add clock support for sg2042 Chen Wang
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