From: Lucas Stach <l.stach@pengutronix.de>
To: Heiko Stuebner <heiko@sntech.de>
Cc: linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-rockchip@lists.infradead.org, kernel@pengutronix.de,
patchwork-lst@pengutronix.de
Subject: [PATCH] clk: rockchip: rk3568: Add PLL rate for 724 MHz
Date: Fri, 3 May 2024 17:33:29 +0200 [thread overview]
Message-ID: <20240503153329.3906030-1-l.stach@pengutronix.de> (raw)
This rate allows to provide a low-jitter 72,4 MHz pixelclock
for a custom eDP panel from the VPLL.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
drivers/clk/rockchip/clk-rk3568.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/clk/rockchip/clk-rk3568.c b/drivers/clk/rockchip/clk-rk3568.c
index 8cb21d10beca..292f2ef32958 100644
--- a/drivers/clk/rockchip/clk-rk3568.c
+++ b/drivers/clk/rockchip/clk-rk3568.c
@@ -64,6 +64,7 @@ static struct rockchip_pll_rate_table rk3568_pll_rates[] = {
RK3036_PLL_RATE(912000000, 1, 76, 2, 1, 1, 0),
RK3036_PLL_RATE(816000000, 1, 68, 2, 1, 1, 0),
RK3036_PLL_RATE(800000000, 3, 200, 2, 1, 1, 0),
+ RK3036_PLL_RATE(724000000, 3, 181, 2, 1, 1, 0),
RK3036_PLL_RATE(700000000, 3, 350, 4, 1, 1, 0),
RK3036_PLL_RATE(696000000, 1, 116, 4, 1, 1, 0),
RK3036_PLL_RATE(600000000, 1, 100, 4, 1, 1, 0),
--
2.39.2
next reply other threads:[~2024-05-03 15:33 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-05-03 15:33 Lucas Stach [this message]
2024-05-04 10:51 ` [PATCH] clk: rockchip: rk3568: Add PLL rate for 724 MHz Heiko Stuebner
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