From: Gabor Juhos <j4g8y7@gmail.com>
To: Bjorn Andersson <andersson@kernel.org>,
Konrad Dybcio <konrad.dybcio@linaro.org>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
Kathiravan T <quic_kathirav@quicinc.com>,
Dmitry Baryshkov <dmitry.baryshkov@linaro.org>,
Varadarajan Narayanan <quic_varada@quicinc.com>
Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org,
linux-kernel@vger.kernel.org, Gabor Juhos <j4g8y7@gmail.com>
Subject: [PATCH] clk: qcom: clk-alpha-pll: set ALPHA_EN bit for Stromer Plus PLLs
Date: Wed, 08 May 2024 22:34:14 +0200 [thread overview]
Message-ID: <20240508-stromer-plus-alpha-en-v1-1-6639ce01ca5b@gmail.com> (raw)
The clk_alpha_pll_stromer_plus_set_rate() function does not
sets the ALPHA_EN bit in the USER_CTL register, so setting
rates which requires using alpha mode works only if the bit
gets set already prior calling the function.
Extend the function to set the ALPHA_EN bit in order to allow
using fractional rates regardless whether the bit gets set
previously or not.
Fixes: 84da48921a97 ("clk: qcom: clk-alpha-pll: introduce stromer plus ops")
Signed-off-by: Gabor Juhos <j4g8y7@gmail.com>
---
Based on 'qcom-clk-for-6.10'
---
---
drivers/clk/qcom/clk-alpha-pll.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c
index d4227909d1fe..c51647e37df8 100644
--- a/drivers/clk/qcom/clk-alpha-pll.c
+++ b/drivers/clk/qcom/clk-alpha-pll.c
@@ -2574,6 +2574,9 @@ static int clk_alpha_pll_stromer_plus_set_rate(struct clk_hw *hw,
regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll),
a >> ALPHA_BITWIDTH);
+ regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
+ PLL_ALPHA_EN, PLL_ALPHA_EN);
+
regmap_write(pll->clkr.regmap, PLL_MODE(pll), PLL_BYPASSNL);
/* Wait five micro seconds or more */
---
base-commit: 3c5b3e17b8fd1f1add5a9477306c355fab126977
change-id: 20240508-stromer-plus-alpha-en-0a4a4c6df28c
Best regards,
--
Gabor Juhos <j4g8y7@gmail.com>
reply other threads:[~2024-05-08 20:34 UTC|newest]
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