From: Alex Bee <knaerzche@gmail.com>
To: "Sandy Huang" <hjc@rock-chips.com>,
"Heiko Stübner" <heiko@sntech.de>,
"Andy Yan" <andy.yan@rock-chips.com>,
"Maarten Lankhorst" <maarten.lankhorst@linux.intel.com>,
"Maxime Ripard" <mripard@kernel.org>,
"Thomas Zimmermann" <tzimmermann@suse.de>,
"David Airlie" <airlied@gmail.com>,
"Daniel Vetter" <daniel@ffwll.ch>,
"Rob Herring" <robh@kernel.org>,
"Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>,
"Conor Dooley" <conor+dt@kernel.org>,
"Michael Turquette" <mturquette@baylibre.com>,
"Stephen Boyd" <sboyd@kernel.org>
Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org,
linux-clk@vger.kernel.org, Alex Bee <knaerzche@gmail.com>
Subject: [PATCH v3 6/7] ARM: dts: rockchip: Add D-PHY for RK3128
Date: Thu, 9 May 2024 16:06:52 +0200 [thread overview]
Message-ID: <20240509140653.168591-7-knaerzche@gmail.com> (raw)
In-Reply-To: <20240509140653.168591-1-knaerzche@gmail.com>
The InnoSilicon D-PHY found in RK3128 SoCs supports DSI/LVDS/TTL with a
maximum transfer rate of 1 Gbps per lane. While adding it, also add it's
clocks to RK3128_PD_VIO powerdomain as the phy is part of it.
Signed-off-by: Alex Bee <knaerzche@gmail.com>
---
changes since v1:
- also added SCLK_MIPI_24M to powerdomain
- reword commit message
arch/arm/boot/dts/rockchip/rk3128.dtsi | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/arch/arm/boot/dts/rockchip/rk3128.dtsi b/arch/arm/boot/dts/rockchip/rk3128.dtsi
index fb98873fd94e..fbd95bb08cd3 100644
--- a/arch/arm/boot/dts/rockchip/rk3128.dtsi
+++ b/arch/arm/boot/dts/rockchip/rk3128.dtsi
@@ -216,6 +216,8 @@ power-domain@RK3128_PD_VIO {
<&cru ACLK_LCDC0>,
<&cru HCLK_LCDC0>,
<&cru PCLK_MIPI>,
+ <&cru PCLK_MIPIPHY>,
+ <&cru SCLK_MIPI_24M>,
<&cru ACLK_RGA>,
<&cru HCLK_RGA>,
<&cru ACLK_VIO0>,
@@ -496,6 +498,18 @@ hdmi_out: port@1 {
};
};
+ dphy: phy@20038000 {
+ compatible = "rockchip,rk3128-dsi-dphy";
+ reg = <0x20038000 0x4000>;
+ clocks = <&cru SCLK_MIPI_24M>, <&cru PCLK_MIPIPHY>;
+ clock-names = "ref", "pclk";
+ resets = <&cru SRST_MIPIPHY_P>;
+ reset-names = "apb";
+ power-domains = <&power RK3128_PD_VIO>;
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
timer0: timer@20044000 {
compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer";
reg = <0x20044000 0x20>;
--
2.43.2
next prev parent reply other threads:[~2024-05-09 14:07 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-05-09 14:06 [PATCH v3 0/7] Add DSI support for RK3128 Alex Bee
2024-05-09 14:06 ` [PATCH v3 1/7] dt-bindings: display: rockchip,dw-mipi-dsi: Document RK3128 DSI Alex Bee
2024-05-09 14:06 ` [PATCH v3 2/7] dt-bindings: clock: rk3128: Add PCLK_MIPIPHY Alex Bee
2024-05-09 14:06 ` [PATCH v3 3/7] clk: rockchip: rk3128: Export PCLK_MIPIPHY Alex Bee
2024-05-09 14:06 ` [PATCH v3 4/7] clk: rockchip: rk3128: Add hclk_vio_h2p to critical clocks Alex Bee
2024-05-09 14:06 ` [PATCH v3 5/7] drm/rockchip: dsi: Add support for RK3128 Alex Bee
2024-05-09 14:06 ` Alex Bee [this message]
2024-05-09 14:06 ` [PATCH v3 7/7] ARM: dts: rockchip: Add DSI " Alex Bee
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