From: Dmitry Rokosov <ddrokosov@salutedevices.com>
To: Conor Dooley <conor@kernel.org>
Cc: <neil.armstrong@linaro.org>, <jbrunet@baylibre.com>,
<mturquette@baylibre.com>, <sboyd@kernel.org>,
<robh+dt@kernel.org>, <krzysztof.kozlowski+dt@linaro.org>,
<khilman@baylibre.com>, <martin.blumenstingl@googlemail.com>,
<jian.hu@amlogic.com>, <kernel@sberdevices.ru>,
<rockosov@gmail.com>, <linux-amlogic@lists.infradead.org>,
<linux-clk@vger.kernel.org>, <devicetree@vger.kernel.org>,
<linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>
Subject: Re: [PATCH v2 2/7] dt-bindings: clock: meson: a1: pll: introduce new syspll bindings
Date: Mon, 13 May 2024 21:30:12 +0300 [thread overview]
Message-ID: <20240513183012.652mwhivasqihiqc@CAB-WSD-L081021> (raw)
In-Reply-To: <20240513-epic-magnifier-8dd83db81c4c@spud>
On Mon, May 13, 2024 at 04:48:33PM +0100, Conor Dooley wrote:
> On Mon, May 13, 2024 at 12:18:02PM +0300, Dmitry Rokosov wrote:
> > Hello Conor,
> >
> > Thank you for quick review!
> >
> > On Sat, May 11, 2024 at 02:08:03PM +0100, Conor Dooley wrote:
> > > On Fri, May 10, 2024 at 12:08:54PM +0300, Dmitry Rokosov wrote:
> > > > The 'syspll' PLL is a general-purpose PLL designed specifically for the
> > > > CPU clock. It is capable of producing output frequencies within the
> > > > range of 768MHz to 1536MHz.
> > > >
> > > > The clock source sys_pll_div16, being one of the GEN clock parents,
> > > > plays a crucial role and cannot be tagged as "optional". Unfortunately,
> > > > it was not implemented earlier due to the cpu clock ctrl driver's
> > > > pending status on the TODO list.
> > >
> > > It's fine to not mark it optional in the binding, but it should be
> > > optional in the driver as otherwise backwards compatibility will be
> > > broken. Given this is an integral clock driver, sounds like it would
> > > quite likely break booting on these devices if the driver doesn't treat
> > > syspll_in as optional.
> > > A lesson perhaps in describing the hardware entirely, even if the
> > > drivers don't make use of all the information yet?
> >
> > Yes, it's definitely the right lesson for me. However, without syspll or
> > syspll_in, we cannot utilize CPU power management at all.
>
> That's the status-quo, right? The incorrect dts would continue to not
> support CPU power management and the new one with the correct description
> would?
Hmmm, correct. Okay, I see, I will support sys_pll as optional
connection :)
--
Thank you,
Dmitry
next prev parent reply other threads:[~2024-05-13 18:30 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-05-10 9:08 [PATCH v2 0/7] clk: meson: introduce Amlogic A1 SoC Family CPU clock controller driver Dmitry Rokosov
2024-05-10 9:08 ` [PATCH v2 1/7] clk: meson: introduce 'INIT_ONCE' flag to eliminate init for enabled PLL Dmitry Rokosov
2024-05-13 12:44 ` Jerome Brunet
2024-05-13 21:47 ` Dmitry Rokosov
2024-05-15 13:12 ` Jerome Brunet
2024-05-10 9:08 ` [PATCH v2 2/7] dt-bindings: clock: meson: a1: pll: introduce new syspll bindings Dmitry Rokosov
2024-05-11 13:08 ` Conor Dooley
2024-05-13 9:18 ` Dmitry Rokosov
2024-05-13 15:48 ` Conor Dooley
2024-05-13 18:30 ` Dmitry Rokosov [this message]
2024-05-15 13:15 ` Jerome Brunet
2024-05-13 12:04 ` Jerome Brunet
2024-05-13 15:42 ` Conor Dooley
2024-05-10 9:08 ` [PATCH v2 3/7] clk: meson: a1: pll: support 'syspll' general-purpose PLL for CPU clock Dmitry Rokosov
2024-05-13 12:48 ` Jerome Brunet
2024-05-13 21:25 ` Dmitry Rokosov
2024-05-10 9:08 ` [PATCH v2 4/7] dt-bindings: clock: meson: a1: peripherals: support sys_pll_div16 input Dmitry Rokosov
2024-05-11 13:03 ` Conor Dooley
2024-05-13 12:02 ` Jerome Brunet
2024-05-10 9:08 ` [PATCH v2 5/7] clk: meson: a1: peripherals: support 'sys_pll_div16' clock as GEN input Dmitry Rokosov
2024-05-10 9:08 ` [PATCH v2 6/7] dt-bindings: clock: meson: add A1 CPU clock controller bindings Dmitry Rokosov
2024-05-10 9:08 ` [PATCH v2 7/7] clk: meson: a1: add Amlogic A1 CPU clock controller driver Dmitry Rokosov
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