From: Geert Uytterhoeven <geert@linux-m68k.org>
To: Claudiu <claudiu.beznea@tuxon.dev>
Cc: mturquette@baylibre.com, robh@kernel.org, krzk+dt@kernel.org,
conor+dt@kernel.org, magnus.damm@gmail.com,
ulf.hansson@linaro.org, linux-renesas-soc@vger.kernel.org,
linux-clk@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org,
Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Subject: Re: [PATCH v4 6/8] clk: renesas: rzg2l: Extend power domain support
Date: Wed, 24 Apr 2024 16:09:58 +0200 [thread overview]
Message-ID: <CAMuHMdXvcRRmCSFB9tM81CjsgyhJ=48WShpqw0cxT7aA=EYNGw@mail.gmail.com> (raw)
In-Reply-To: <20240422105355.1622177-7-claudiu.beznea.uj@bp.renesas.com>
On Mon, Apr 22, 2024 at 12:54 PM Claudiu <claudiu.beznea@tuxon.dev> wrote:
> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>
> RZ/{G2L, V2L, G3S}-based CPG versions have support for saving extra
> power when clocks are disabled by activating module standby. This is done
> through MSTOP-specific registers that are part of CPG. Each individual
> module has one or more bits associated with one MSTOP register (see table
> "Registers for Module Standby Mode" from HW manuals). Hardware manual
> associates modules' clocks with one or more MSTOP bits. There are 3
> mappings available (identified by researching RZ/G2L, RZ/G3S, RZ/V2L HW
> manuals):
>
> case 1: N clocks mapped to N MSTOP bits (with N={0, ..., X})
> case 2: N clocks mapped to 1 MSTOP bit (with N={0, ..., X})
> case 3: N clocks mapped to M MSTOP bits (with N={0, ..., X}, M={0, ..., Y})
>
> Case 3 has been currently identified on RZ/V2L for the VCPL4 module.
>
> To cover all three cases, the individual platform drivers will provide to
> clock driver MSTOP register offset and associated bits in this register
> as a bitmask and the clock driver will apply this bitmask to proper
> MSTOP register.
>
> The MSTOP was implemented through power domains. Platform-specific clock
> drivers will register an array of type
> struct rzg2l_cpg_pm_domain_init_data, which will be used to instantiate
> properly the power domains.
>
> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> ---
>
> Changes in v2:
s/v2/v4/
> - dropped the pwrdn functionality until it is better understanded;
> at the same time kept the code ready for pwrd being added by keeping
> struct rzg2l_cpg_pm_domain_conf, DEF_REG_CONF(); please let me know
> if you prefer otherwise
> - @Geert, @Ulf: I dropped your previous Rb tags due to dropping pwrdn
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
next prev parent reply other threads:[~2024-04-24 14:10 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-22 10:53 [PATCH v4 0/8] clk: renesas: rzg2l: Add support for power domains Claudiu
2024-04-22 10:53 ` [PATCH v4 1/8] dt-bindings: clock: r9a07g043-cpg: Add power domain IDs Claudiu
2024-04-22 10:53 ` [PATCH v4 2/8] dt-bindings: clock: r9a07g044-cpg: " Claudiu
2024-04-22 10:53 ` [PATCH v4 3/8] dt-bindings: clock: r9a07g054-cpg: " Claudiu
2024-04-22 10:53 ` [PATCH v4 4/8] dt-bindings: clock: r9a08g045-cpg: " Claudiu
2024-04-22 10:53 ` [PATCH v4 5/8] dt-bindings: clock: renesas,rzg2l-cpg: Update #power-domain-cells = <1> for RZ/G3S Claudiu
2024-04-22 10:53 ` [PATCH v4 6/8] clk: renesas: rzg2l: Extend power domain support Claudiu
2024-04-24 14:09 ` Geert Uytterhoeven [this message]
2024-04-22 10:53 ` [PATCH v4 7/8] clk: renesas: r9a08g045: Add support for power domains Claudiu
2024-04-24 14:10 ` Geert Uytterhoeven
2024-04-22 10:53 ` [PATCH v4 8/8] arm64: dts: renesas: r9a08g045: Update #power-domain-cells = <1> Claudiu
2024-04-24 14:33 ` [PATCH v4 0/8] clk: renesas: rzg2l: Add support for power domains Geert Uytterhoeven
2024-04-25 16:44 ` Ulf Hansson
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