From: Chen Wang <unicorn_wang@outlook.com>
To: Inochi Amaoto <inochiama@outlook.com>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>
Cc: linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org,
kernel test robot <lkp@intel.com>
Subject: Re: [PATCH] clk: sophgo: Use div64 for fpll rate calculation
Date: Sat, 13 Apr 2024 11:01:58 +0800 [thread overview]
Message-ID: <MA0P287MB2822856646A116E713BCE716FE0B2@MA0P287MB2822.INDP287.PROD.OUTLOOK.COM> (raw)
In-Reply-To: <IA1PR20MB4953CB4FCCDE82AB25F6880EBB0B2@IA1PR20MB4953.namprd20.prod.outlook.com>
Just a minor suggestion to add soc name in email title to differ against
other sophgo products. This can be handled in later patch if any.
Reviewed-by: Chen Wang <unicorn_wang@outlook.com>
On 2024/4/13 8:53, Inochi Amaoto wrote:
> The CV1800 SoC needs to use 64-bit division for fpll rate
> calculation, which will cause problem on 32-bit system.
> Use div64 series function to avoid this problem.
>
> Fixes: 80fd61ec4612 ("clk: sophgo: Add clock support for CV1800 SoC")
> Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
> Reported-by: kernel test robot <lkp@intel.com>
> Closes: https://lore.kernel.org/oe-kbuild-all/202404122344.d5pb2N1I-lkp@intel.com/
> ---
> drivers/clk/sophgo/clk-cv18xx-pll.c | 9 +++++----
> 1 file changed, 5 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/clk/sophgo/clk-cv18xx-pll.c b/drivers/clk/sophgo/clk-cv18xx-pll.c
> index c546dad1791c..65aba3b95cf7 100644
> --- a/drivers/clk/sophgo/clk-cv18xx-pll.c
> +++ b/drivers/clk/sophgo/clk-cv18xx-pll.c
> @@ -6,6 +6,7 @@
> #include <linux/clk-provider.h>
> #include <linux/io.h>
> #include <linux/limits.h>
> +#include <linux/math64.h>
> #include <linux/spinlock.h>
>
> #include "clk-cv18xx-pll.h"
> @@ -202,18 +203,18 @@ static unsigned long fpll_calc_rate(unsigned long parent_rate,
> {
> u64 dividend = parent_rate * div_sel;
> u64 factor = ssc_syn_set * pre_div_sel * post_div_sel;
> + u64 remainder;
> unsigned long rate;
>
> dividend <<= PLL_SYN_FACTOR_DOT_POS - 1;
> - rate = dividend / factor;
> - dividend %= factor;
> + rate = div64_u64_rem(dividend, factor, &remainder);
>
> if (is_full_parent) {
> - dividend <<= 1;
> + remainder <<= 1;
> rate <<= 1;
> }
>
> - rate += DIV64_U64_ROUND_CLOSEST(dividend, factor);
> + rate += DIV64_U64_ROUND_CLOSEST(remainder, factor);
>
> return rate;
> }
> --
> 2.44.0
>
next prev parent reply other threads:[~2024-04-13 3:02 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-13 0:53 [PATCH] clk: sophgo: Use div64 for fpll rate calculation Inochi Amaoto
2024-04-13 3:01 ` Chen Wang [this message]
2024-04-14 0:13 ` Inochi Amaoto
2024-04-17 11:08 ` Inochi Amaoto
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