From: Chen Wang <unicornxw@gmail.com>
To: aou@eecs.berkeley.edu, chao.wei@sophgo.com, conor@kernel.org,
krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com,
palmer@dabbelt.com, paul.walmsley@sifive.com,
richardcochran@gmail.com, robh+dt@kernel.org, sboyd@kernel.org,
devicetree@vger.kernel.org, linux-clk@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
haijiao.liu@sophgo.com, xiaoguang.xing@sophgo.com,
guoren@kernel.org, jszhang@kernel.org, inochiama@outlook.com,
samuel.holland@sifive.com
Cc: Chen Wang <unicorn_wang@outlook.com>, Rob Herring <robh@kernel.org>
Subject: [PATCH v14 1/5] dt-bindings: clock: sophgo: add pll clocks for SG2042
Date: Mon, 15 Apr 2024 15:22:18 +0800 [thread overview]
Message-ID: <cb4ccaad1d3637a6ebb0413dbe45bb0fd12ed401.1713164546.git.unicorn_wang@outlook.com> (raw)
In-Reply-To: <cover.1713164546.git.unicorn_wang@outlook.com>
From: Chen Wang <unicorn_wang@outlook.com>
Add bindings for the pll clocks for Sophgo SG2042.
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Guo Ren <guoren@kernel.org>
---
.../bindings/clock/sophgo,sg2042-pll.yaml | 45 +++++++++++++++++++
include/dt-bindings/clock/sophgo,sg2042-pll.h | 14 ++++++
2 files changed, 59 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/sophgo,sg2042-pll.yaml
create mode 100644 include/dt-bindings/clock/sophgo,sg2042-pll.h
diff --git a/Documentation/devicetree/bindings/clock/sophgo,sg2042-pll.yaml b/Documentation/devicetree/bindings/clock/sophgo,sg2042-pll.yaml
new file mode 100644
index 000000000000..b9af733e8a73
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/sophgo,sg2042-pll.yaml
@@ -0,0 +1,45 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/sophgo,sg2042-pll.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Sophgo SG2042 PLL Clock Generator
+
+maintainers:
+ - Chen Wang <unicorn_wang@outlook.com>
+
+properties:
+ compatible:
+ const: sophgo,sg2042-pll
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: Oscillator(Clock Generation IC) for Main/Fixed PLL (25 MHz)
+ - description: Oscillator(Clock Generation IC) for DDR PLL 0 (25 MHz)
+ - description: Oscillator(Clock Generation IC) for DDR PLL 1 (25 MHz)
+
+ '#clock-cells':
+ const: 1
+ description:
+ See <dt-bindings/clock/sophgo,sg2042-pll.h> for valid indices.
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - '#clock-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ clock-controller@10000000 {
+ compatible = "sophgo,sg2042-pll";
+ reg = <0x10000000 0x10000>;
+ clocks = <&cgi_main>, <&cgi_dpll0>, <&cgi_dpll1>;
+ #clock-cells = <1>;
+ };
diff --git a/include/dt-bindings/clock/sophgo,sg2042-pll.h b/include/dt-bindings/clock/sophgo,sg2042-pll.h
new file mode 100644
index 000000000000..2d519b3bf51c
--- /dev/null
+++ b/include/dt-bindings/clock/sophgo,sg2042-pll.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
+/*
+ * Copyright (C) 2023 Sophgo Technology Inc. All rights reserved.
+ */
+
+#ifndef __DT_BINDINGS_SOPHGO_SG2042_PLL_H__
+#define __DT_BINDINGS_SOPHGO_SG2042_PLL_H__
+
+#define MPLL_CLK 0
+#define FPLL_CLK 1
+#define DPLL0_CLK 2
+#define DPLL1_CLK 3
+
+#endif /* __DT_BINDINGS_SOPHGO_SG2042_PLL_H__ */
--
2.25.1
next prev parent reply other threads:[~2024-04-15 7:22 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-15 7:21 [PATCH v14 0/5] riscv: sophgo: add clock support for sg2042 Chen Wang
2024-04-15 7:22 ` Chen Wang [this message]
2024-04-15 7:22 ` [PATCH v14 2/5] dt-bindings: clock: sophgo: add RP gate clocks for SG2042 Chen Wang
2024-04-15 7:23 ` [PATCH v14 3/5] dt-bindings: clock: sophgo: add clkgen " Chen Wang
2024-04-15 7:23 ` [PATCH v14 4/5] clk: sophgo: Add SG2042 clock driver Chen Wang
2024-04-22 9:07 ` Chen Wang
2024-04-23 0:47 ` Stephen Boyd
2024-04-15 7:23 ` [PATCH v14 5/5] riscv: dts: add clock generator for Sophgo SG2042 SoC Chen Wang
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