From: Konrad Dybcio <konrad.dybcio@linaro.org>
To: Abel Vesa <abel.vesa@linaro.org>,
Bjorn Andersson <andersson@kernel.org>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
Dmitry Baryshkov <dmitry.baryshkov@linaro.org>,
Rajendra Nayak <quic_rjendra@quicinc.com>
Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH] clk: qcom: dispcc-x1e80100: Drop the reconfiguring of PLL0 on probe
Date: Thu, 18 Apr 2024 13:33:19 +0200 [thread overview]
Message-ID: <e5c60b6f-3cab-4265-87fc-7eeab03795ec@linaro.org> (raw)
In-Reply-To: <20240418-x1e80100-dispcc-drop-pll0-reconfigure-v1-1-453e4e70e940@linaro.org>
On 18.04.2024 12:51 PM, Abel Vesa wrote:
> Currently, PLL0 is configured by the bootloader is the parent of the
> mdp_clk_src. Reconfiguring it on probe leaves the PLL0 in "stand-by"
> state (unlocked), which will trigger RCG child clocks to not update
> their config,
Sounds like this is the problem that should be fixed instead.
which then breaks eDP on all x1e80100 boards. So rely
> on the bootloader for now. Drop the config values as well. Also add
> a comment to explain why the PLL0 is not configured alongside PLL1.
>
> Fixes: ee3f0739035f ("clk: qcom: Add dispcc clock driver for x1e80100")
> Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
> ---
This works, because you have (at least) partially configured hardware, but
we shouldn't assume this to be the case.
Konrad
next prev parent reply other threads:[~2024-04-18 11:33 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-18 10:51 [PATCH] clk: qcom: dispcc-x1e80100: Drop the reconfiguring of PLL0 on probe Abel Vesa
2024-04-18 11:33 ` Konrad Dybcio [this message]
2024-04-18 12:08 ` Abel Vesa
2024-04-18 13:52 ` Abel Vesa
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