From: Dan Williams <dan.j.williams@intel.com>
To: Robert Richter <rrichter@amd.com>,
Dan Williams <dan.j.williams@intel.com>
Cc: Davidlohr Bueso <dave@stgolabs.net>,
Jonathan Cameron <jonathan.cameron@huawei.com>,
Dave Jiang <dave.jiang@intel.com>,
"Alison Schofield" <alison.schofield@intel.com>,
Vishal Verma <vishal.l.verma@intel.com>,
Ira Weiny <ira.weiny@intel.com>, <linux-cxl@vger.kernel.org>,
<linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v2] cxl/pci: Fix disabling memory if DVSEC CXL Range does not match a CFMWS window
Date: Fri, 16 Feb 2024 19:07:05 -0800 [thread overview]
Message-ID: <65d022d9b02f5_5c76294ed@dwillia2-mobl3.amr.corp.intel.com.notmuch> (raw)
In-Reply-To: <Zc_b_F5TSRSBwrNZ@rric.localdomain>
Robert Richter wrote:
> On 16.02.24 19:09:30, Robert Richter wrote:
> > On 16.02.24 10:02:51, Dan Williams wrote:
> > > Robert Richter wrote:
> > > > The Linux CXL subsystem is built on the assumption that HPA == SPA.
> > > > That is, the host physical address (HPA) the HDM decoder registers are
> > > > programmed with are system physical addresses (SPA).
> > > >
> > > > During HDM decoder setup, the DVSEC CXL range registers (cxl-3.1,
> > > > 8.1.3.8) are checked if the memory is enabled and the CXL range is in
> > > > a HPA window that is described in a CFMWS structure of the CXL host
> > > > bridge (cxl-3.1, 9.18.1.3).
> > > >
> > > > Now, if the HPA is not an SPA, the CXL range does not match a CFMWS
> > > > window and the CXL memory range will be disabled then. The HDM decoder
> > > > stops working which causes system memory being disabled and further a
> > > > system hang during HDM decoder initialization, typically when a CXL
> > > > enabled kernel boots.
> > > >
> > > > Prevent a system hang and do not disable the HDM decoder if the
> > > > decoder's CXL range is not found in a CFMWS window.
> > > >
> > > > Note the change only fixes a hardware hang, but does not implement
> > > > HPA/SPA translation. Support for this can be added in a follow on
> > > > patch series.
> > > >
>
> Fixes: 9de321e93c3b ("cxl/pci: Refactor cxl_hdm_decode_init()")
This patch just moves the memory-disable call from one place to another.
> Fixes: 34e37b4c432c ("cxl/port: Enable HDM Capability after validating DVSEC Ranges")
This is the proper Fixes tag.
> Cc: stable@vger.kernel.org
Added.
next prev parent reply other threads:[~2024-02-17 3:07 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-02-16 16:01 [PATCH v2] cxl/pci: Fix disabling memory if DVSEC CXL Range does not match a CFMWS window Robert Richter
2024-02-16 18:02 ` Dan Williams
2024-02-16 18:09 ` Robert Richter
2024-02-16 22:04 ` Robert Richter
2024-02-17 3:07 ` Dan Williams [this message]
2024-02-17 4:22 ` Dan Williams
2024-02-17 21:27 ` Robert Richter
2024-03-22 3:15 ` [Problem ?] cxl list show nothing after reboot " Zhijian Li (Fujitsu)
2024-03-26 8:26 ` Zhijian Li (Fujitsu)
2024-04-05 16:57 ` Jonathan Cameron
2024-04-07 3:51 ` Zhijian Li (Fujitsu)
2024-04-08 23:14 ` Dan Williams
2024-04-09 6:53 ` Zhijian Li (Fujitsu)
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